Update version for v3.1.0-rc4 release
[qemu.git] / hw / i2c / pm_smbus.c
1 /*
2 * PC SMBus implementation
3 * splitted from acpi.c
4 *
5 * Copyright (c) 2006 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License version 2 as published by the Free Software Foundation.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "hw/hw.h"
22 #include "hw/i2c/pm_smbus.h"
23 #include "hw/i2c/smbus.h"
24
25 #define SMBHSTSTS 0x00
26 #define SMBHSTCNT 0x02
27 #define SMBHSTCMD 0x03
28 #define SMBHSTADD 0x04
29 #define SMBHSTDAT0 0x05
30 #define SMBHSTDAT1 0x06
31 #define SMBBLKDAT 0x07
32 #define SMBAUXCTL 0x0d
33
34 #define STS_HOST_BUSY (1 << 0)
35 #define STS_INTR (1 << 1)
36 #define STS_DEV_ERR (1 << 2)
37 #define STS_BUS_ERR (1 << 3)
38 #define STS_FAILED (1 << 4)
39 #define STS_SMBALERT (1 << 5)
40 #define STS_INUSE_STS (1 << 6)
41 #define STS_BYTE_DONE (1 << 7)
42 /* Signs of successfully transaction end :
43 * ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
44 */
45
46 #define CTL_INTREN (1 << 0)
47 #define CTL_KILL (1 << 1)
48 #define CTL_LAST_BYTE (1 << 5)
49 #define CTL_START (1 << 6)
50 #define CTL_PEC_EN (1 << 7)
51 #define CTL_RETURN_MASK 0x1f
52
53 #define PROT_QUICK 0
54 #define PROT_BYTE 1
55 #define PROT_BYTE_DATA 2
56 #define PROT_WORD_DATA 3
57 #define PROT_PROC_CALL 4
58 #define PROT_BLOCK_DATA 5
59 #define PROT_I2C_BLOCK_READ 6
60
61 #define AUX_PEC (1 << 0)
62 #define AUX_BLK (1 << 1)
63 #define AUX_MASK 0x3
64
65 /*#define DEBUG*/
66
67 #ifdef DEBUG
68 # define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
69 #else
70 # define SMBUS_DPRINTF(format, ...) do { } while (0)
71 #endif
72
73
74 static void smb_transaction(PMSMBus *s)
75 {
76 uint8_t prot = (s->smb_ctl >> 2) & 0x07;
77 uint8_t read = s->smb_addr & 0x01;
78 uint8_t cmd = s->smb_cmd;
79 uint8_t addr = s->smb_addr >> 1;
80 I2CBus *bus = s->smbus;
81 int ret;
82
83 SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
84 /* Transaction isn't exec if STS_DEV_ERR bit set */
85 if ((s->smb_stat & STS_DEV_ERR) != 0) {
86 goto error;
87 }
88
89 switch(prot) {
90 case PROT_QUICK:
91 ret = smbus_quick_command(bus, addr, read);
92 goto done;
93 case PROT_BYTE:
94 if (read) {
95 ret = smbus_receive_byte(bus, addr);
96 goto data8;
97 } else {
98 ret = smbus_send_byte(bus, addr, cmd);
99 goto done;
100 }
101 case PROT_BYTE_DATA:
102 if (read) {
103 ret = smbus_read_byte(bus, addr, cmd);
104 goto data8;
105 } else {
106 ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
107 goto done;
108 }
109 break;
110 case PROT_WORD_DATA:
111 if (read) {
112 ret = smbus_read_word(bus, addr, cmd);
113 goto data16;
114 } else {
115 ret = smbus_write_word(bus, addr, cmd,
116 (s->smb_data1 << 8) | s->smb_data0);
117 goto done;
118 }
119 break;
120 case PROT_I2C_BLOCK_READ:
121 if (read) {
122 int xfersize = s->smb_data0;
123 if (xfersize > sizeof(s->smb_data)) {
124 xfersize = sizeof(s->smb_data);
125 }
126 ret = smbus_read_block(bus, addr, s->smb_data1, s->smb_data,
127 xfersize, false, true);
128 goto data8;
129 } else {
130 /* The manual says the behavior is undefined, just set DEV_ERR. */
131 goto error;
132 }
133 break;
134 case PROT_BLOCK_DATA:
135 if (read) {
136 ret = smbus_read_block(bus, addr, cmd, s->smb_data,
137 sizeof(s->smb_data), !s->i2c_enable,
138 !s->i2c_enable);
139 if (ret < 0) {
140 goto error;
141 }
142 s->smb_index = 0;
143 s->op_done = false;
144 if (s->smb_auxctl & AUX_BLK) {
145 s->smb_stat |= STS_INTR;
146 } else {
147 s->smb_blkdata = s->smb_data[0];
148 s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
149 }
150 s->smb_data0 = ret;
151 goto out;
152 } else {
153 if (s->smb_auxctl & AUX_BLK) {
154 if (s->smb_index != s->smb_data0) {
155 s->smb_index = 0;
156 goto error;
157 }
158 /* Data is already all written to the queue, just do
159 the operation. */
160 s->smb_index = 0;
161 ret = smbus_write_block(bus, addr, cmd, s->smb_data,
162 s->smb_data0, !s->i2c_enable);
163 if (ret < 0) {
164 goto error;
165 }
166 s->op_done = true;
167 s->smb_stat |= STS_INTR;
168 s->smb_stat &= ~STS_HOST_BUSY;
169 } else {
170 s->op_done = false;
171 s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
172 s->smb_data[0] = s->smb_blkdata;
173 s->smb_index = 0;
174 ret = 0;
175 }
176 goto out;
177 }
178 break;
179 default:
180 goto error;
181 }
182 abort();
183
184 data16:
185 if (ret < 0) {
186 goto error;
187 }
188 s->smb_data1 = ret >> 8;
189 data8:
190 if (ret < 0) {
191 goto error;
192 }
193 s->smb_data0 = ret;
194 done:
195 if (ret < 0) {
196 goto error;
197 }
198 s->smb_stat |= STS_INTR;
199 out:
200 return;
201
202 error:
203 s->smb_stat |= STS_DEV_ERR;
204 return;
205 }
206
207 static void smb_transaction_start(PMSMBus *s)
208 {
209 if (s->smb_ctl & CTL_INTREN) {
210 smb_transaction(s);
211 } else {
212 /* Do not execute immediately the command; it will be
213 * executed when guest will read SMB_STAT register. This
214 * is to work around a bug in AMIBIOS (that is working
215 * around another bug in some specific hardware) where
216 * it waits for STS_HOST_BUSY to be set before waiting
217 * checking for status. If STS_HOST_BUSY doesn't get
218 * set, it gets stuck. */
219 s->smb_stat |= STS_HOST_BUSY;
220 }
221 }
222
223 static bool
224 smb_irq_value(PMSMBus *s)
225 {
226 return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN);
227 }
228
229 static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
230 unsigned width)
231 {
232 PMSMBus *s = opaque;
233
234 SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
235 " val=0x%02" PRIx64 "\n", addr, val);
236 switch(addr) {
237 case SMBHSTSTS:
238 s->smb_stat &= ~(val & ~STS_HOST_BUSY);
239 if (!s->op_done && !(s->smb_auxctl & AUX_BLK)) {
240 uint8_t read = s->smb_addr & 0x01;
241
242 s->smb_index++;
243 if (!read && s->smb_index == s->smb_data0) {
244 uint8_t prot = (s->smb_ctl >> 2) & 0x07;
245 uint8_t cmd = s->smb_cmd;
246 uint8_t addr = s->smb_addr >> 1;
247 int ret;
248
249 if (prot == PROT_I2C_BLOCK_READ) {
250 s->smb_stat |= STS_DEV_ERR;
251 goto out;
252 }
253
254 ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data,
255 s->smb_data0, !s->i2c_enable);
256 if (ret < 0) {
257 s->smb_stat |= STS_DEV_ERR;
258 goto out;
259 }
260 s->op_done = true;
261 s->smb_stat |= STS_INTR;
262 s->smb_stat &= ~STS_HOST_BUSY;
263 } else if (!read) {
264 s->smb_data[s->smb_index] = s->smb_blkdata;
265 s->smb_stat |= STS_BYTE_DONE;
266 } else if (s->smb_ctl & CTL_LAST_BYTE) {
267 s->op_done = true;
268 s->smb_blkdata = s->smb_data[s->smb_index];
269 s->smb_index = 0;
270 s->smb_stat |= STS_INTR;
271 s->smb_stat &= ~STS_HOST_BUSY;
272 } else {
273 s->smb_blkdata = s->smb_data[s->smb_index];
274 s->smb_stat |= STS_BYTE_DONE;
275 }
276 }
277 break;
278 case SMBHSTCNT:
279 s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */
280 if (val & CTL_START) {
281 if (!s->op_done) {
282 s->smb_index = 0;
283 s->op_done = true;
284 }
285 smb_transaction_start(s);
286 }
287 if (s->smb_ctl & CTL_KILL) {
288 s->op_done = true;
289 s->smb_index = 0;
290 s->smb_stat |= STS_FAILED;
291 s->smb_stat &= ~STS_HOST_BUSY;
292 }
293 break;
294 case SMBHSTCMD:
295 s->smb_cmd = val;
296 break;
297 case SMBHSTADD:
298 s->smb_addr = val;
299 break;
300 case SMBHSTDAT0:
301 s->smb_data0 = val;
302 break;
303 case SMBHSTDAT1:
304 s->smb_data1 = val;
305 break;
306 case SMBBLKDAT:
307 if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
308 s->smb_index = 0;
309 }
310 if (s->smb_auxctl & AUX_BLK) {
311 s->smb_data[s->smb_index++] = val;
312 } else {
313 s->smb_blkdata = val;
314 }
315 break;
316 case SMBAUXCTL:
317 s->smb_auxctl = val & AUX_MASK;
318 break;
319 default:
320 break;
321 }
322
323 out:
324 if (s->set_irq) {
325 s->set_irq(s, smb_irq_value(s));
326 }
327 }
328
329 static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
330 {
331 PMSMBus *s = opaque;
332 uint32_t val;
333
334 switch(addr) {
335 case SMBHSTSTS:
336 val = s->smb_stat;
337 if (s->smb_stat & STS_HOST_BUSY) {
338 /* execute command now */
339 s->smb_stat &= ~STS_HOST_BUSY;
340 smb_transaction(s);
341 }
342 break;
343 case SMBHSTCNT:
344 val = s->smb_ctl & CTL_RETURN_MASK;
345 break;
346 case SMBHSTCMD:
347 val = s->smb_cmd;
348 break;
349 case SMBHSTADD:
350 val = s->smb_addr;
351 break;
352 case SMBHSTDAT0:
353 val = s->smb_data0;
354 break;
355 case SMBHSTDAT1:
356 val = s->smb_data1;
357 break;
358 case SMBBLKDAT:
359 if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
360 s->smb_index = 0;
361 }
362 if (s->smb_auxctl & AUX_BLK) {
363 val = s->smb_data[s->smb_index++];
364 if (!s->op_done && s->smb_index == s->smb_data0) {
365 s->op_done = true;
366 s->smb_index = 0;
367 s->smb_stat &= ~STS_HOST_BUSY;
368 }
369 } else {
370 val = s->smb_blkdata;
371 }
372 break;
373 case SMBAUXCTL:
374 val = s->smb_auxctl;
375 break;
376 default:
377 val = 0;
378 break;
379 }
380 SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n",
381 addr, val);
382
383 if (s->set_irq) {
384 s->set_irq(s, smb_irq_value(s));
385 }
386
387 return val;
388 }
389
390 static void pm_smbus_reset(PMSMBus *s)
391 {
392 s->op_done = true;
393 s->smb_index = 0;
394 s->smb_stat = 0;
395 }
396
397 static const MemoryRegionOps pm_smbus_ops = {
398 .read = smb_ioport_readb,
399 .write = smb_ioport_writeb,
400 .valid.min_access_size = 1,
401 .valid.max_access_size = 1,
402 .endianness = DEVICE_LITTLE_ENDIAN,
403 };
404
405 void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk)
406 {
407 smb->op_done = true;
408 smb->reset = pm_smbus_reset;
409 smb->smbus = i2c_init_bus(parent, "i2c");
410 if (force_aux_blk) {
411 smb->smb_auxctl |= AUX_BLK;
412 }
413 memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
414 "pm-smbus", 64);
415 }