hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / i2c / ppc4xx_i2c.c
1 /*
2 * PPC4xx I2C controller emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 Fran├žois Revol
6 * Copyright (c) 2016-2018 BALATON Zoltan
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu/log.h"
29 #include "qemu/module.h"
30 #include "hw/i2c/ppc4xx_i2c.h"
31 #include "hw/irq.h"
32
33 #define PPC4xx_I2C_MEM_SIZE 18
34
35 enum {
36 IIC_MDBUF = 0,
37 /* IIC_SDBUF = 2, */
38 IIC_LMADR = 4,
39 IIC_HMADR,
40 IIC_CNTL,
41 IIC_MDCNTL,
42 IIC_STS,
43 IIC_EXTSTS,
44 IIC_LSADR,
45 IIC_HSADR,
46 IIC_CLKDIV,
47 IIC_INTRMSK,
48 IIC_XFRCNT,
49 IIC_XTCNTLSS,
50 IIC_DIRECTCNTL
51 /* IIC_INTR */
52 };
53
54 #define IIC_CNTL_PT (1 << 0)
55 #define IIC_CNTL_READ (1 << 1)
56 #define IIC_CNTL_CHT (1 << 2)
57 #define IIC_CNTL_RPST (1 << 3)
58 #define IIC_CNTL_AMD (1 << 6)
59 #define IIC_CNTL_HMT (1 << 7)
60
61 #define IIC_MDCNTL_EINT (1 << 2)
62 #define IIC_MDCNTL_ESM (1 << 3)
63 #define IIC_MDCNTL_FMDB (1 << 6)
64
65 #define IIC_STS_PT (1 << 0)
66 #define IIC_STS_IRQA (1 << 1)
67 #define IIC_STS_ERR (1 << 2)
68 #define IIC_STS_MDBF (1 << 4)
69 #define IIC_STS_MDBS (1 << 5)
70
71 #define IIC_EXTSTS_XFRA (1 << 0)
72 #define IIC_EXTSTS_BCS_FREE (4 << 4)
73 #define IIC_EXTSTS_BCS_BUSY (5 << 4)
74
75 #define IIC_INTRMSK_EIMTC (1 << 0)
76 #define IIC_INTRMSK_EITA (1 << 1)
77 #define IIC_INTRMSK_EIIC (1 << 2)
78 #define IIC_INTRMSK_EIHE (1 << 3)
79
80 #define IIC_XTCNTLSS_SRST (1 << 0)
81
82 #define IIC_DIRECTCNTL_SDAC (1 << 3)
83 #define IIC_DIRECTCNTL_SCLC (1 << 2)
84 #define IIC_DIRECTCNTL_MSDA (1 << 1)
85 #define IIC_DIRECTCNTL_MSCL (1 << 0)
86
87 static void ppc4xx_i2c_reset(DeviceState *s)
88 {
89 PPC4xxI2CState *i2c = PPC4xx_I2C(s);
90
91 i2c->mdidx = -1;
92 memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));
93 /* [hl][ms]addr are not affected by reset */
94 i2c->cntl = 0;
95 i2c->mdcntl = 0;
96 i2c->sts = 0;
97 i2c->extsts = IIC_EXTSTS_BCS_FREE;
98 i2c->clkdiv = 0;
99 i2c->intrmsk = 0;
100 i2c->xfrcnt = 0;
101 i2c->xtcntlss = 0;
102 i2c->directcntl = 0xf; /* all non-reserved bits set */
103 }
104
105 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
106 {
107 PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
108 uint64_t ret;
109 int i;
110
111 switch (addr) {
112 case IIC_MDBUF:
113 if (i2c->mdidx < 0) {
114 ret = 0xff;
115 break;
116 }
117 ret = i2c->mdata[0];
118 if (i2c->mdidx == 3) {
119 i2c->sts &= ~IIC_STS_MDBF;
120 } else if (i2c->mdidx == 0) {
121 i2c->sts &= ~IIC_STS_MDBS;
122 }
123 for (i = 0; i < i2c->mdidx; i++) {
124 i2c->mdata[i] = i2c->mdata[i + 1];
125 }
126 if (i2c->mdidx >= 0) {
127 i2c->mdidx--;
128 }
129 break;
130 case IIC_LMADR:
131 ret = i2c->lmadr;
132 break;
133 case IIC_HMADR:
134 ret = i2c->hmadr;
135 break;
136 case IIC_CNTL:
137 ret = i2c->cntl;
138 break;
139 case IIC_MDCNTL:
140 ret = i2c->mdcntl;
141 break;
142 case IIC_STS:
143 ret = i2c->sts;
144 break;
145 case IIC_EXTSTS:
146 ret = i2c_bus_busy(i2c->bus) ?
147 IIC_EXTSTS_BCS_BUSY : IIC_EXTSTS_BCS_FREE;
148 break;
149 case IIC_LSADR:
150 ret = i2c->lsadr;
151 break;
152 case IIC_HSADR:
153 ret = i2c->hsadr;
154 break;
155 case IIC_CLKDIV:
156 ret = i2c->clkdiv;
157 break;
158 case IIC_INTRMSK:
159 ret = i2c->intrmsk;
160 break;
161 case IIC_XFRCNT:
162 ret = i2c->xfrcnt;
163 break;
164 case IIC_XTCNTLSS:
165 ret = i2c->xtcntlss;
166 break;
167 case IIC_DIRECTCNTL:
168 ret = i2c->directcntl;
169 break;
170 default:
171 if (addr < PPC4xx_I2C_MEM_SIZE) {
172 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
173 HWADDR_PRIx "\n", __func__, addr);
174 } else {
175 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
176 HWADDR_PRIx "\n", __func__, addr);
177 }
178 ret = 0;
179 break;
180 }
181 return ret;
182 }
183
184 static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
185 unsigned int size)
186 {
187 PPC4xxI2CState *i2c = opaque;
188
189 switch (addr) {
190 case IIC_MDBUF:
191 if (i2c->mdidx >= 3) {
192 break;
193 }
194 i2c->mdata[++i2c->mdidx] = value;
195 if (i2c->mdidx == 3) {
196 i2c->sts |= IIC_STS_MDBF;
197 } else if (i2c->mdidx == 0) {
198 i2c->sts |= IIC_STS_MDBS;
199 }
200 break;
201 case IIC_LMADR:
202 i2c->lmadr = value;
203 break;
204 case IIC_HMADR:
205 i2c->hmadr = value;
206 break;
207 case IIC_CNTL:
208 i2c->cntl = value & ~IIC_CNTL_PT;
209 if (value & IIC_CNTL_AMD) {
210 qemu_log_mask(LOG_UNIMP, "%s: only 7 bit addresses supported\n",
211 __func__);
212 }
213 if (value & IIC_CNTL_HMT && i2c_bus_busy(i2c->bus)) {
214 i2c_end_transfer(i2c->bus);
215 if (i2c->mdcntl & IIC_MDCNTL_EINT &&
216 i2c->intrmsk & IIC_INTRMSK_EIHE) {
217 i2c->sts |= IIC_STS_IRQA;
218 qemu_irq_raise(i2c->irq);
219 }
220 } else if (value & IIC_CNTL_PT) {
221 int recv = (value & IIC_CNTL_READ) >> 1;
222 int tct = value >> 4 & 3;
223 int i;
224
225 if (recv && (i2c->lmadr >> 1) >= 0x50 && (i2c->lmadr >> 1) < 0x58) {
226 /* smbus emulation does not like multi byte reads w/o restart */
227 value |= IIC_CNTL_RPST;
228 }
229
230 for (i = 0; i <= tct; i++) {
231 if (!i2c_bus_busy(i2c->bus)) {
232 i2c->extsts = IIC_EXTSTS_BCS_FREE;
233 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, recv)) {
234 i2c->sts |= IIC_STS_ERR;
235 i2c->extsts |= IIC_EXTSTS_XFRA;
236 break;
237 } else {
238 i2c->sts &= ~IIC_STS_ERR;
239 }
240 }
241 if (!(i2c->sts & IIC_STS_ERR) &&
242 i2c_send_recv(i2c->bus, &i2c->mdata[i], !recv)) {
243 i2c->sts |= IIC_STS_ERR;
244 i2c->extsts |= IIC_EXTSTS_XFRA;
245 break;
246 }
247 if (value & IIC_CNTL_RPST || !(value & IIC_CNTL_CHT)) {
248 i2c_end_transfer(i2c->bus);
249 }
250 }
251 i2c->xfrcnt = i;
252 i2c->mdidx = i - 1;
253 if (recv && i2c->mdidx >= 0) {
254 i2c->sts |= IIC_STS_MDBS;
255 }
256 if (recv && i2c->mdidx == 3) {
257 i2c->sts |= IIC_STS_MDBF;
258 }
259 if (i && i2c->mdcntl & IIC_MDCNTL_EINT &&
260 i2c->intrmsk & IIC_INTRMSK_EIMTC) {
261 i2c->sts |= IIC_STS_IRQA;
262 qemu_irq_raise(i2c->irq);
263 }
264 }
265 break;
266 case IIC_MDCNTL:
267 i2c->mdcntl = value & 0x3d;
268 if (value & IIC_MDCNTL_ESM) {
269 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
270 __func__);
271 }
272 if (value & IIC_MDCNTL_FMDB) {
273 i2c->mdidx = -1;
274 memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));
275 i2c->sts &= ~(IIC_STS_MDBF | IIC_STS_MDBS);
276 }
277 break;
278 case IIC_STS:
279 i2c->sts &= ~(value & 0x0a);
280 if (value & IIC_STS_IRQA && i2c->mdcntl & IIC_MDCNTL_EINT) {
281 qemu_irq_lower(i2c->irq);
282 }
283 break;
284 case IIC_EXTSTS:
285 i2c->extsts &= ~(value & 0x8f);
286 break;
287 case IIC_LSADR:
288 i2c->lsadr = value;
289 break;
290 case IIC_HSADR:
291 i2c->hsadr = value;
292 break;
293 case IIC_CLKDIV:
294 i2c->clkdiv = value;
295 break;
296 case IIC_INTRMSK:
297 i2c->intrmsk = value;
298 break;
299 case IIC_XFRCNT:
300 i2c->xfrcnt = value & 0x77;
301 break;
302 case IIC_XTCNTLSS:
303 i2c->xtcntlss &= ~(value & 0xf0);
304 if (value & IIC_XTCNTLSS_SRST) {
305 /* Is it actually a full reset? U-Boot sets some regs before */
306 ppc4xx_i2c_reset(DEVICE(i2c));
307 break;
308 }
309 break;
310 case IIC_DIRECTCNTL:
311 i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);
312 i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);
313 bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SCL,
314 i2c->directcntl & IIC_DIRECTCNTL_MSCL);
315 i2c->directcntl |= bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SDA,
316 (value & IIC_DIRECTCNTL_SDAC) != 0) << 1;
317 break;
318 default:
319 if (addr < PPC4xx_I2C_MEM_SIZE) {
320 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
321 HWADDR_PRIx "\n", __func__, addr);
322 } else {
323 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
324 HWADDR_PRIx "\n", __func__, addr);
325 }
326 break;
327 }
328 }
329
330 static const MemoryRegionOps ppc4xx_i2c_ops = {
331 .read = ppc4xx_i2c_readb,
332 .write = ppc4xx_i2c_writeb,
333 .valid.min_access_size = 1,
334 .valid.max_access_size = 4,
335 .impl.min_access_size = 1,
336 .impl.max_access_size = 1,
337 .endianness = DEVICE_NATIVE_ENDIAN,
338 };
339
340 static void ppc4xx_i2c_init(Object *o)
341 {
342 PPC4xxI2CState *s = PPC4xx_I2C(o);
343
344 memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
345 TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
346 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
347 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
348 s->bus = i2c_init_bus(DEVICE(s), "i2c");
349 bitbang_i2c_init(&s->bitbang, s->bus);
350 }
351
352 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
353 {
354 DeviceClass *dc = DEVICE_CLASS(klass);
355
356 dc->reset = ppc4xx_i2c_reset;
357 }
358
359 static const TypeInfo ppc4xx_i2c_type_info = {
360 .name = TYPE_PPC4xx_I2C,
361 .parent = TYPE_SYS_BUS_DEVICE,
362 .instance_size = sizeof(PPC4xxI2CState),
363 .instance_init = ppc4xx_i2c_init,
364 .class_init = ppc4xx_i2c_class_init,
365 };
366
367 static void ppc4xx_i2c_register_types(void)
368 {
369 type_register_static(&ppc4xx_i2c_type_info);
370 }
371
372 type_init(ppc4xx_i2c_register_types)