Revert "hw/loongarch/virt: Add cfi01 pflash device"
[qemu.git] / hw / i2c / smbus_ich9.c
1 /*
2 * ACPI implementation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/range.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "hw/pci/pci.h"
27 #include "migration/vmstate.h"
28 #include "qemu/module.h"
29
30 #include "hw/i386/ich9.h"
31 #include "qom/object.h"
32 #include "hw/acpi/acpi_aml_interface.h"
33
34 OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE)
35
36 struct ICH9SMBState {
37 PCIDevice dev;
38
39 bool irq_enabled;
40
41 PMSMBus smb;
42 };
43
44 static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
45 {
46 return pm_smbus_vmstate_needed();
47 }
48
49 static const VMStateDescription vmstate_ich9_smbus = {
50 .name = "ich9_smb",
51 .version_id = 1,
52 .minimum_version_id = 1,
53 .fields = (VMStateField[]) {
54 VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
55 VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
56 VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
57 pmsmb_vmstate, PMSMBus),
58 VMSTATE_END_OF_LIST()
59 }
60 };
61
62 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
63 uint32_t val, int len)
64 {
65 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
66
67 pci_default_write_config(d, address, val, len);
68 if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
69 uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
70 if (hostc & ICH9_SMB_HOSTC_HST_EN) {
71 memory_region_set_enabled(&s->smb.io, true);
72 } else {
73 memory_region_set_enabled(&s->smb.io, false);
74 }
75 s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
76 if (hostc & ICH9_SMB_HOSTC_SSRESET) {
77 s->smb.reset(&s->smb);
78 s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
79 }
80 }
81 }
82
83 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
84 {
85 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
86
87 /* TODO? D31IP.SMIP in chipset configuration space */
88 pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
89
90 pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
91 /* TODO bar0, bar1: 64bit BAR support*/
92
93 pm_smbus_init(&d->qdev, &s->smb, false);
94 pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
95 &s->smb.io);
96 }
97
98 static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
99 {
100 BusChild *kid;
101 ICH9SMBState *s = ICH9_SMB_DEVICE(adev);
102 BusState *bus = BUS(s->smb.smbus);
103
104 QTAILQ_FOREACH(kid, &bus->children, sibling) {
105 call_dev_aml_func(DEVICE(kid->child), scope);
106 }
107 }
108
109 static void ich9_smb_class_init(ObjectClass *klass, void *data)
110 {
111 DeviceClass *dc = DEVICE_CLASS(klass);
112 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
113 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
114
115 k->vendor_id = PCI_VENDOR_ID_INTEL;
116 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
117 k->revision = ICH9_A2_SMB_REVISION;
118 k->class_id = PCI_CLASS_SERIAL_SMBUS;
119 dc->vmsd = &vmstate_ich9_smbus;
120 dc->desc = "ICH9 SMBUS Bridge";
121 k->realize = ich9_smbus_realize;
122 k->config_write = ich9_smbus_write_config;
123 /*
124 * Reason: part of ICH9 southbridge, needs to be wired up by
125 * pc_q35_init()
126 */
127 dc->user_creatable = false;
128 adevc->build_dev_aml = build_ich9_smb_aml;
129 }
130
131 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
132 {
133 ICH9SMBState *s = pmsmb->opaque;
134
135 if (enabled == s->irq_enabled) {
136 return;
137 }
138
139 s->irq_enabled = enabled;
140 pci_set_irq(&s->dev, enabled);
141 }
142
143 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
144 {
145 PCIDevice *d =
146 pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
147 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
148 s->smb.set_irq = ich9_smb_set_irq;
149 s->smb.opaque = s;
150 return s->smb.smbus;
151 }
152
153 static const TypeInfo ich9_smb_info = {
154 .name = TYPE_ICH9_SMB_DEVICE,
155 .parent = TYPE_PCI_DEVICE,
156 .instance_size = sizeof(ICH9SMBState),
157 .class_init = ich9_smb_class_init,
158 .interfaces = (InterfaceInfo[]) {
159 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
160 { TYPE_ACPI_DEV_AML_IF },
161 { },
162 },
163 };
164
165 static void ich9_smb_register(void)
166 {
167 type_register_static(&ich9_smb_info);
168 }
169
170 type_init(ich9_smb_register);