acpi: rename cpu_hotplug_defs.h to pc-hotplug.h
[qemu.git] / hw / i386 / acpi-dsdt.dsl
1 /*
2  * Bochs/QEMU ACPI DSDT ASL definition
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License version 2 as published by the Free Software Foundation.
9  *
10  * This library is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * Lesser General Public License for more details.
14  *
15  * You should have received a copy of the GNU Lesser General Public
16  * License along with this library; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18  */
19
20 ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode
21
22 DefinitionBlock (
23     "acpi-dsdt.aml",    // Output Filename
24     "DSDT",             // Signature
25     0x01,               // DSDT Compliance Revision
26     "BXPC",             // OEMID
27     "BXDSDT",           // TABLE ID
28     0x1                 // OEM Revision
29     )
30 {
31
32 #include "acpi-dsdt-dbug.dsl"
33
34
35 /****************************************************************
36  * PCI Bus definition
37  ****************************************************************/
38 #define BOARD_SPECIFIC_PCI_RESOURSES \
39      WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
40          0x0000, \
41          0x0000, \
42          0x0CF7, \
43          0x0000, \
44          0x0CF8, \
45          ,, , TypeStatic) \
46      WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
47          0x0000, \
48          0x0D00, \
49          0xADFF, \
50          0x0000, \
51          0xA100, \
52          ,, , TypeStatic) \
53      /* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \
54      WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
55          0x0000, \
56          0xAE0F, \
57          0xAEFF, \
58          0x0000, \
59          0x00F1, \
60          ,, , TypeStatic) \
61      /* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \
62      WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
63          0x0000, \
64          0xAF20, \
65          0xAFDF, \
66          0x0000, \
67          0x00C0, \
68          ,, , TypeStatic) \
69      /* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
70      WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
71          0x0000, \
72          0xAFE4, \
73          0xFFFF, \
74          0x0000, \
75          0x501C, \
76          ,, , TypeStatic)
77
78     Scope(\_SB) {
79         Device(PCI0) {
80             Name(_HID, EisaId("PNP0A03"))
81             Name(_ADR, 0x00)
82             Name(_UID, 1)
83 //#define PX13 S0B_
84 //            External(PX13, DeviceObj)
85         }
86     }
87
88 #include "acpi-dsdt-pci-crs.dsl"
89 #include "acpi-dsdt-hpet.dsl"
90
91
92 /****************************************************************
93  * PIIX4 PM
94  ****************************************************************/
95
96     Scope(\_SB.PCI0) {
97         Device(PX13) {
98             Name(_ADR, 0x00010003)
99             OperationRegion(P13C, PCI_Config, 0x00, 0xff)
100         }
101     }
102
103
104 /****************************************************************
105  * PIIX3 ISA bridge
106  ****************************************************************/
107
108     Scope(\_SB.PCI0) {
109
110         External(ISA, DeviceObj)
111
112         Device(ISA) {
113             Name(_ADR, 0x00010000)
114
115             /* PIIX PCI to ISA irq remapping */
116             OperationRegion(P40C, PCI_Config, 0x60, 0x04)
117
118             /* enable bits */
119             Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
120                 Offset(0x5f),
121                 , 7,
122                 LPEN, 1,         // LPT
123                 Offset(0x67),
124                 , 3,
125                 CAEN, 1,         // COM1
126                 , 3,
127                 CBEN, 1,         // COM2
128             }
129             Name(FDEN, 1)
130         }
131     }
132
133 #define DSDT_APPLESMC_STA piix_dsdt_applesmc_sta
134 #include "acpi-dsdt-isa.dsl"
135
136
137 /****************************************************************
138  * PCI hotplug
139  ****************************************************************/
140
141     Scope(\_SB.PCI0) {
142         OperationRegion(PCST, SystemIO, 0xae00, 0x08)
143         Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
144             PCIU, 32,
145             PCID, 32,
146         }
147
148         OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
149         Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
150             B0EJ, 32,
151         }
152
153         OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
154         Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
155             BNUM, 32,
156         }
157
158         /* Lock to protect access to fields above. */
159         Mutex(BLCK, 0)
160
161         /* Methods called by bulk generated PCI devices below */
162
163         /* Methods called by hotplug devices */
164         Method(PCEJ, 2, NotSerialized) {
165             // _EJ0 method - eject callback
166             Acquire(BLCK, 0xFFFF)
167             Store(Arg0, BNUM)
168             Store(ShiftLeft(1, Arg1), B0EJ)
169             Release(BLCK)
170             Return (0x0)
171         }
172
173         /* Hotplug notification method supplied by SSDT */
174         External(\_SB.PCI0.PCNT, MethodObj)
175     }
176
177
178 /****************************************************************
179  * PCI IRQs
180  ****************************************************************/
181
182     Scope(\_SB) {
183         Scope(PCI0) {
184             Name(_PRT, Package() {
185                 /* PCI IRQ routing table, example from ACPI 2.0a specification,
186                    section 6.2.8.1 */
187                 /* Note: we provide the same info as the PCI routing
188                    table of the Bochs BIOS */
189
190 #define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
191     Package() { nr##ffff, 0, lnk0, 0 }, \
192     Package() { nr##ffff, 1, lnk1, 0 }, \
193     Package() { nr##ffff, 2, lnk2, 0 }, \
194     Package() { nr##ffff, 3, lnk3, 0 }
195
196 #define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
197 #define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
198 #define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
199 #define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
200
201                 prt_slot0(0x0000),
202                 /* Device 1 is power mgmt device, and can only use irq 9 */
203                 prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
204                 prt_slot2(0x0002),
205                 prt_slot3(0x0003),
206                 prt_slot0(0x0004),
207                 prt_slot1(0x0005),
208                 prt_slot2(0x0006),
209                 prt_slot3(0x0007),
210                 prt_slot0(0x0008),
211                 prt_slot1(0x0009),
212                 prt_slot2(0x000a),
213                 prt_slot3(0x000b),
214                 prt_slot0(0x000c),
215                 prt_slot1(0x000d),
216                 prt_slot2(0x000e),
217                 prt_slot3(0x000f),
218                 prt_slot0(0x0010),
219                 prt_slot1(0x0011),
220                 prt_slot2(0x0012),
221                 prt_slot3(0x0013),
222                 prt_slot0(0x0014),
223                 prt_slot1(0x0015),
224                 prt_slot2(0x0016),
225                 prt_slot3(0x0017),
226                 prt_slot0(0x0018),
227                 prt_slot1(0x0019),
228                 prt_slot2(0x001a),
229                 prt_slot3(0x001b),
230                 prt_slot0(0x001c),
231                 prt_slot1(0x001d),
232                 prt_slot2(0x001e),
233                 prt_slot3(0x001f),
234             })
235         }
236
237         Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
238             PRQ0,   8,
239             PRQ1,   8,
240             PRQ2,   8,
241             PRQ3,   8
242         }
243
244         Method(IQST, 1, NotSerialized) {
245             // _STA method - get status
246             If (And(0x80, Arg0)) {
247                 Return (0x09)
248             }
249             Return (0x0B)
250         }
251         Method(IQCR, 1, Serialized) {
252             // _CRS method - get current settings
253             Name(PRR0, ResourceTemplate() {
254                 Interrupt(, Level, ActiveHigh, Shared) { 0 }
255             })
256             CreateDWordField(PRR0, 0x05, PRRI)
257             If (LLess(Arg0, 0x80)) {
258                 Store(Arg0, PRRI)
259             }
260             Return (PRR0)
261         }
262
263 #define define_link(link, uid, reg)                             \
264         Device(link) {                                          \
265             Name(_HID, EISAID("PNP0C0F"))                       \
266             Name(_UID, uid)                                     \
267             Name(_PRS, ResourceTemplate() {                     \
268                 Interrupt(, Level, ActiveHigh, Shared) {        \
269                     5, 10, 11                                   \
270                 }                                               \
271             })                                                  \
272             Method(_STA, 0, NotSerialized) {                    \
273                 Return (IQST(reg))                              \
274             }                                                   \
275             Method(_DIS, 0, NotSerialized) {                    \
276                 Or(reg, 0x80, reg)                              \
277             }                                                   \
278             Method(_CRS, 0, NotSerialized) {                    \
279                 Return (IQCR(reg))                              \
280             }                                                   \
281             Method(_SRS, 1, NotSerialized) {                    \
282                 CreateDWordField(Arg0, 0x05, PRRI)              \
283                 Store(PRRI, reg)                                \
284             }                                                   \
285         }
286
287         define_link(LNKA, 0, PRQ0)
288         define_link(LNKB, 1, PRQ1)
289         define_link(LNKC, 2, PRQ2)
290         define_link(LNKD, 3, PRQ3)
291
292         Device(LNKS) {
293             Name(_HID, EISAID("PNP0C0F"))
294             Name(_UID, 4)
295             Name(_PRS, ResourceTemplate() {
296                 Interrupt(, Level, ActiveHigh, Shared) { 9 }
297             })
298
299             // The SCI cannot be disabled and is always attached to GSI 9,
300             // so these are no-ops.  We only need this link to override the
301             // polarity to active high and match the content of the MADT.
302             Method(_STA, 0, NotSerialized) { Return (0x0b) }
303             Method(_DIS, 0, NotSerialized) { }
304             Method(_CRS, 0, NotSerialized) { Return (_PRS) }
305             Method(_SRS, 1, NotSerialized) { }
306         }
307     }
308
309 #include "hw/acpi/pc-hotplug.h"
310 #define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE
311 #include "acpi-dsdt-cpu-hotplug.dsl"
312
313
314 /****************************************************************
315  * General purpose events
316  ****************************************************************/
317
318     Scope(\_GPE) {
319         Name(_HID, "ACPI0006")
320
321         Method(_L00) {
322         }
323         Method(_E01) {
324             // PCI hotplug event
325             Acquire(\_SB.PCI0.BLCK, 0xFFFF)
326             \_SB.PCI0.PCNT()
327             Release(\_SB.PCI0.BLCK)
328         }
329         Method(_E02) {
330             // CPU hotplug event
331             \_SB.PRSC()
332         }
333         Method(_L03) {
334         }
335         Method(_L04) {
336         }
337         Method(_L05) {
338         }
339         Method(_L06) {
340         }
341         Method(_L07) {
342         }
343         Method(_L08) {
344         }
345         Method(_L09) {
346         }
347         Method(_L0A) {
348         }
349         Method(_L0B) {
350         }
351         Method(_L0C) {
352         }
353         Method(_L0D) {
354         }
355         Method(_L0E) {
356         }
357         Method(_L0F) {
358         }
359     }
360 }