meson: convert hw/9pfs, cleanup
[qemu.git] / hw / i386 / intel_iommu.c
1 /*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
25 #include "qapi/error.h"
26 #include "hw/sysbus.h"
27 #include "exec/address-spaces.h"
28 #include "intel_iommu_internal.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/i386/pc.h"
33 #include "hw/i386/apic-msidef.h"
34 #include "hw/boards.h"
35 #include "hw/i386/x86-iommu.h"
36 #include "hw/pci-host/q35.h"
37 #include "sysemu/kvm.h"
38 #include "sysemu/sysemu.h"
39 #include "hw/i386/apic_internal.h"
40 #include "kvm_i386.h"
41 #include "migration/vmstate.h"
42 #include "trace.h"
43
44 /* context entry operations */
45 #define VTD_CE_GET_RID2PASID(ce) \
46 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
47 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \
48 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
49
50 /* pe operations */
51 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
52 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
53 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\
54 if (ret_fr) { \
55 ret_fr = -ret_fr; \
56 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \
57 trace_vtd_fault_disabled(); \
58 } else { \
59 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \
60 } \
61 goto error; \
62 } \
63 }
64
65 static void vtd_address_space_refresh_all(IntelIOMMUState *s);
66 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
67
68 static void vtd_panic_require_caching_mode(void)
69 {
70 error_report("We need to set caching-mode=on for intel-iommu to enable "
71 "device assignment with IOMMU protection.");
72 exit(1);
73 }
74
75 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
76 uint64_t wmask, uint64_t w1cmask)
77 {
78 stq_le_p(&s->csr[addr], val);
79 stq_le_p(&s->wmask[addr], wmask);
80 stq_le_p(&s->w1cmask[addr], w1cmask);
81 }
82
83 static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
84 {
85 stq_le_p(&s->womask[addr], mask);
86 }
87
88 static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
89 uint32_t wmask, uint32_t w1cmask)
90 {
91 stl_le_p(&s->csr[addr], val);
92 stl_le_p(&s->wmask[addr], wmask);
93 stl_le_p(&s->w1cmask[addr], w1cmask);
94 }
95
96 static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
97 {
98 stl_le_p(&s->womask[addr], mask);
99 }
100
101 /* "External" get/set operations */
102 static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
103 {
104 uint64_t oldval = ldq_le_p(&s->csr[addr]);
105 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
106 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
107 stq_le_p(&s->csr[addr],
108 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
109 }
110
111 static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
112 {
113 uint32_t oldval = ldl_le_p(&s->csr[addr]);
114 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
115 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
116 stl_le_p(&s->csr[addr],
117 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
118 }
119
120 static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
121 {
122 uint64_t val = ldq_le_p(&s->csr[addr]);
123 uint64_t womask = ldq_le_p(&s->womask[addr]);
124 return val & ~womask;
125 }
126
127 static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
128 {
129 uint32_t val = ldl_le_p(&s->csr[addr]);
130 uint32_t womask = ldl_le_p(&s->womask[addr]);
131 return val & ~womask;
132 }
133
134 /* "Internal" get/set operations */
135 static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
136 {
137 return ldq_le_p(&s->csr[addr]);
138 }
139
140 static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
141 {
142 return ldl_le_p(&s->csr[addr]);
143 }
144
145 static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
146 {
147 stq_le_p(&s->csr[addr], val);
148 }
149
150 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
151 uint32_t clear, uint32_t mask)
152 {
153 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
154 stl_le_p(&s->csr[addr], new_val);
155 return new_val;
156 }
157
158 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
159 uint64_t clear, uint64_t mask)
160 {
161 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
162 stq_le_p(&s->csr[addr], new_val);
163 return new_val;
164 }
165
166 static inline void vtd_iommu_lock(IntelIOMMUState *s)
167 {
168 qemu_mutex_lock(&s->iommu_lock);
169 }
170
171 static inline void vtd_iommu_unlock(IntelIOMMUState *s)
172 {
173 qemu_mutex_unlock(&s->iommu_lock);
174 }
175
176 static void vtd_update_scalable_state(IntelIOMMUState *s)
177 {
178 uint64_t val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
179
180 if (s->scalable_mode) {
181 s->root_scalable = val & VTD_RTADDR_SMT;
182 }
183 }
184
185 /* Whether the address space needs to notify new mappings */
186 static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as)
187 {
188 return as->notifier_flags & IOMMU_NOTIFIER_MAP;
189 }
190
191 /* GHashTable functions */
192 static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
193 {
194 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
195 }
196
197 static guint vtd_uint64_hash(gconstpointer v)
198 {
199 return (guint)*(const uint64_t *)v;
200 }
201
202 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
203 gpointer user_data)
204 {
205 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
206 uint16_t domain_id = *(uint16_t *)user_data;
207 return entry->domain_id == domain_id;
208 }
209
210 /* The shift of an addr for a certain level of paging structure */
211 static inline uint32_t vtd_slpt_level_shift(uint32_t level)
212 {
213 assert(level != 0);
214 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
215 }
216
217 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
218 {
219 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
220 }
221
222 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
223 gpointer user_data)
224 {
225 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
226 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
227 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
228 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
229 return (entry->domain_id == info->domain_id) &&
230 (((entry->gfn & info->mask) == gfn) ||
231 (entry->gfn == gfn_tlb));
232 }
233
234 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
235 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
236 */
237 static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
238 {
239 VTDAddressSpace *vtd_as;
240 VTDBus *vtd_bus;
241 GHashTableIter bus_it;
242 uint32_t devfn_it;
243
244 trace_vtd_context_cache_reset();
245
246 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
247
248 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
249 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
250 vtd_as = vtd_bus->dev_as[devfn_it];
251 if (!vtd_as) {
252 continue;
253 }
254 vtd_as->context_cache_entry.context_cache_gen = 0;
255 }
256 }
257 s->context_cache_gen = 1;
258 }
259
260 /* Must be called with IOMMU lock held. */
261 static void vtd_reset_iotlb_locked(IntelIOMMUState *s)
262 {
263 assert(s->iotlb);
264 g_hash_table_remove_all(s->iotlb);
265 }
266
267 static void vtd_reset_iotlb(IntelIOMMUState *s)
268 {
269 vtd_iommu_lock(s);
270 vtd_reset_iotlb_locked(s);
271 vtd_iommu_unlock(s);
272 }
273
274 static void vtd_reset_caches(IntelIOMMUState *s)
275 {
276 vtd_iommu_lock(s);
277 vtd_reset_iotlb_locked(s);
278 vtd_reset_context_cache_locked(s);
279 vtd_iommu_unlock(s);
280 }
281
282 static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
283 uint32_t level)
284 {
285 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
286 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
287 }
288
289 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
290 {
291 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
292 }
293
294 /* Must be called with IOMMU lock held */
295 static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
296 hwaddr addr)
297 {
298 VTDIOTLBEntry *entry;
299 uint64_t key;
300 int level;
301
302 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
303 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
304 source_id, level);
305 entry = g_hash_table_lookup(s->iotlb, &key);
306 if (entry) {
307 goto out;
308 }
309 }
310
311 out:
312 return entry;
313 }
314
315 /* Must be with IOMMU lock held */
316 static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
317 uint16_t domain_id, hwaddr addr, uint64_t slpte,
318 uint8_t access_flags, uint32_t level)
319 {
320 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
321 uint64_t *key = g_malloc(sizeof(*key));
322 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
323
324 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
325 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
326 trace_vtd_iotlb_reset("iotlb exceeds size limit");
327 vtd_reset_iotlb_locked(s);
328 }
329
330 entry->gfn = gfn;
331 entry->domain_id = domain_id;
332 entry->slpte = slpte;
333 entry->access_flags = access_flags;
334 entry->mask = vtd_slpt_level_page_mask(level);
335 *key = vtd_get_iotlb_key(gfn, source_id, level);
336 g_hash_table_replace(s->iotlb, key, entry);
337 }
338
339 /* Given the reg addr of both the message data and address, generate an
340 * interrupt via MSI.
341 */
342 static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
343 hwaddr mesg_data_reg)
344 {
345 MSIMessage msi;
346
347 assert(mesg_data_reg < DMAR_REG_SIZE);
348 assert(mesg_addr_reg < DMAR_REG_SIZE);
349
350 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
351 msi.data = vtd_get_long_raw(s, mesg_data_reg);
352
353 trace_vtd_irq_generate(msi.address, msi.data);
354
355 apic_get_class()->send_msi(&msi);
356 }
357
358 /* Generate a fault event to software via MSI if conditions are met.
359 * Notice that the value of FSTS_REG being passed to it should be the one
360 * before any update.
361 */
362 static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
363 {
364 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
365 pre_fsts & VTD_FSTS_IQE) {
366 error_report_once("There are previous interrupt conditions "
367 "to be serviced by software, fault event "
368 "is not generated");
369 return;
370 }
371 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
372 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
373 error_report_once("Interrupt Mask set, irq is not generated");
374 } else {
375 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
376 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
377 }
378 }
379
380 /* Check if the Fault (F) field of the Fault Recording Register referenced by
381 * @index is Set.
382 */
383 static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
384 {
385 /* Each reg is 128-bit */
386 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
387 addr += 8; /* Access the high 64-bit half */
388
389 assert(index < DMAR_FRCD_REG_NR);
390
391 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
392 }
393
394 /* Update the PPF field of Fault Status Register.
395 * Should be called whenever change the F field of any fault recording
396 * registers.
397 */
398 static void vtd_update_fsts_ppf(IntelIOMMUState *s)
399 {
400 uint32_t i;
401 uint32_t ppf_mask = 0;
402
403 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
404 if (vtd_is_frcd_set(s, i)) {
405 ppf_mask = VTD_FSTS_PPF;
406 break;
407 }
408 }
409 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
410 trace_vtd_fsts_ppf(!!ppf_mask);
411 }
412
413 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
414 {
415 /* Each reg is 128-bit */
416 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
417 addr += 8; /* Access the high 64-bit half */
418
419 assert(index < DMAR_FRCD_REG_NR);
420
421 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
422 vtd_update_fsts_ppf(s);
423 }
424
425 /* Must not update F field now, should be done later */
426 static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
427 uint16_t source_id, hwaddr addr,
428 VTDFaultReason fault, bool is_write)
429 {
430 uint64_t hi = 0, lo;
431 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
432
433 assert(index < DMAR_FRCD_REG_NR);
434
435 lo = VTD_FRCD_FI(addr);
436 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
437 if (!is_write) {
438 hi |= VTD_FRCD_T;
439 }
440 vtd_set_quad_raw(s, frcd_reg_addr, lo);
441 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
442
443 trace_vtd_frr_new(index, hi, lo);
444 }
445
446 /* Try to collapse multiple pending faults from the same requester */
447 static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
448 {
449 uint32_t i;
450 uint64_t frcd_reg;
451 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
452
453 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
454 frcd_reg = vtd_get_quad_raw(s, addr);
455 if ((frcd_reg & VTD_FRCD_F) &&
456 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
457 return true;
458 }
459 addr += 16; /* 128-bit for each */
460 }
461 return false;
462 }
463
464 /* Log and report an DMAR (address translation) fault to software */
465 static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
466 hwaddr addr, VTDFaultReason fault,
467 bool is_write)
468 {
469 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
470
471 assert(fault < VTD_FR_MAX);
472
473 if (fault == VTD_FR_RESERVED_ERR) {
474 /* This is not a normal fault reason case. Drop it. */
475 return;
476 }
477
478 trace_vtd_dmar_fault(source_id, fault, addr, is_write);
479
480 if (fsts_reg & VTD_FSTS_PFO) {
481 error_report_once("New fault is not recorded due to "
482 "Primary Fault Overflow");
483 return;
484 }
485
486 if (vtd_try_collapse_fault(s, source_id)) {
487 error_report_once("New fault is not recorded due to "
488 "compression of faults");
489 return;
490 }
491
492 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
493 error_report_once("Next Fault Recording Reg is used, "
494 "new fault is not recorded, set PFO field");
495 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
496 return;
497 }
498
499 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
500
501 if (fsts_reg & VTD_FSTS_PPF) {
502 error_report_once("There are pending faults already, "
503 "fault event is not generated");
504 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
505 s->next_frcd_reg++;
506 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
507 s->next_frcd_reg = 0;
508 }
509 } else {
510 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
511 VTD_FSTS_FRI(s->next_frcd_reg));
512 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
513 s->next_frcd_reg++;
514 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
515 s->next_frcd_reg = 0;
516 }
517 /* This case actually cause the PPF to be Set.
518 * So generate fault event (interrupt).
519 */
520 vtd_generate_fault_event(s, fsts_reg);
521 }
522 }
523
524 /* Handle Invalidation Queue Errors of queued invalidation interface error
525 * conditions.
526 */
527 static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
528 {
529 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
530
531 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
532 vtd_generate_fault_event(s, fsts_reg);
533 }
534
535 /* Set the IWC field and try to generate an invalidation completion interrupt */
536 static void vtd_generate_completion_event(IntelIOMMUState *s)
537 {
538 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
539 trace_vtd_inv_desc_wait_irq("One pending, skip current");
540 return;
541 }
542 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
543 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
544 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
545 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
546 "new event not generated");
547 return;
548 } else {
549 /* Generate the interrupt event */
550 trace_vtd_inv_desc_wait_irq("Generating complete event");
551 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
552 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
553 }
554 }
555
556 static inline bool vtd_root_entry_present(IntelIOMMUState *s,
557 VTDRootEntry *re,
558 uint8_t devfn)
559 {
560 if (s->root_scalable && devfn > UINT8_MAX / 2) {
561 return re->hi & VTD_ROOT_ENTRY_P;
562 }
563
564 return re->lo & VTD_ROOT_ENTRY_P;
565 }
566
567 static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
568 VTDRootEntry *re)
569 {
570 dma_addr_t addr;
571
572 addr = s->root + index * sizeof(*re);
573 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
574 re->lo = 0;
575 return -VTD_FR_ROOT_TABLE_INV;
576 }
577 re->lo = le64_to_cpu(re->lo);
578 re->hi = le64_to_cpu(re->hi);
579 return 0;
580 }
581
582 static inline bool vtd_ce_present(VTDContextEntry *context)
583 {
584 return context->lo & VTD_CONTEXT_ENTRY_P;
585 }
586
587 static int vtd_get_context_entry_from_root(IntelIOMMUState *s,
588 VTDRootEntry *re,
589 uint8_t index,
590 VTDContextEntry *ce)
591 {
592 dma_addr_t addr, ce_size;
593
594 /* we have checked that root entry is present */
595 ce_size = s->root_scalable ? VTD_CTX_ENTRY_SCALABLE_SIZE :
596 VTD_CTX_ENTRY_LEGACY_SIZE;
597
598 if (s->root_scalable && index > UINT8_MAX / 2) {
599 index = index & (~VTD_DEVFN_CHECK_MASK);
600 addr = re->hi & VTD_ROOT_ENTRY_CTP;
601 } else {
602 addr = re->lo & VTD_ROOT_ENTRY_CTP;
603 }
604
605 addr = addr + index * ce_size;
606 if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) {
607 return -VTD_FR_CONTEXT_TABLE_INV;
608 }
609
610 ce->lo = le64_to_cpu(ce->lo);
611 ce->hi = le64_to_cpu(ce->hi);
612 if (ce_size == VTD_CTX_ENTRY_SCALABLE_SIZE) {
613 ce->val[2] = le64_to_cpu(ce->val[2]);
614 ce->val[3] = le64_to_cpu(ce->val[3]);
615 }
616 return 0;
617 }
618
619 static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
620 {
621 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
622 }
623
624 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
625 {
626 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
627 }
628
629 /* Whether the pte indicates the address of the page frame */
630 static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
631 {
632 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
633 }
634
635 /* Get the content of a spte located in @base_addr[@index] */
636 static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
637 {
638 uint64_t slpte;
639
640 assert(index < VTD_SL_PT_ENTRY_NR);
641
642 if (dma_memory_read(&address_space_memory,
643 base_addr + index * sizeof(slpte), &slpte,
644 sizeof(slpte))) {
645 slpte = (uint64_t)-1;
646 return slpte;
647 }
648 slpte = le64_to_cpu(slpte);
649 return slpte;
650 }
651
652 /* Given an iova and the level of paging structure, return the offset
653 * of current level.
654 */
655 static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
656 {
657 return (iova >> vtd_slpt_level_shift(level)) &
658 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
659 }
660
661 /* Check Capability Register to see if the @level of page-table is supported */
662 static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
663 {
664 return VTD_CAP_SAGAW_MASK & s->cap &
665 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
666 }
667
668 /* Return true if check passed, otherwise false */
669 static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
670 VTDPASIDEntry *pe)
671 {
672 switch (VTD_PE_GET_TYPE(pe)) {
673 case VTD_SM_PASID_ENTRY_FLT:
674 case VTD_SM_PASID_ENTRY_SLT:
675 case VTD_SM_PASID_ENTRY_NESTED:
676 break;
677 case VTD_SM_PASID_ENTRY_PT:
678 if (!x86_iommu->pt_supported) {
679 return false;
680 }
681 break;
682 default:
683 /* Unknwon type */
684 return false;
685 }
686 return true;
687 }
688
689 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
690 {
691 return pdire->val & 1;
692 }
693
694 /**
695 * Caller of this function should check present bit if wants
696 * to use pdir entry for futher usage except for fpd bit check.
697 */
698 static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,
699 uint32_t pasid,
700 VTDPASIDDirEntry *pdire)
701 {
702 uint32_t index;
703 dma_addr_t addr, entry_size;
704
705 index = VTD_PASID_DIR_INDEX(pasid);
706 entry_size = VTD_PASID_DIR_ENTRY_SIZE;
707 addr = pasid_dir_base + index * entry_size;
708 if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) {
709 return -VTD_FR_PASID_TABLE_INV;
710 }
711
712 return 0;
713 }
714
715 static inline bool vtd_pe_present(VTDPASIDEntry *pe)
716 {
717 return pe->val[0] & VTD_PASID_ENTRY_P;
718 }
719
720 static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
721 uint32_t pasid,
722 dma_addr_t addr,
723 VTDPASIDEntry *pe)
724 {
725 uint32_t index;
726 dma_addr_t entry_size;
727 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
728
729 index = VTD_PASID_TABLE_INDEX(pasid);
730 entry_size = VTD_PASID_ENTRY_SIZE;
731 addr = addr + index * entry_size;
732 if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) {
733 return -VTD_FR_PASID_TABLE_INV;
734 }
735
736 /* Do translation type check */
737 if (!vtd_pe_type_check(x86_iommu, pe)) {
738 return -VTD_FR_PASID_TABLE_INV;
739 }
740
741 if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
742 return -VTD_FR_PASID_TABLE_INV;
743 }
744
745 return 0;
746 }
747
748 /**
749 * Caller of this function should check present bit if wants
750 * to use pasid entry for futher usage except for fpd bit check.
751 */
752 static int vtd_get_pe_from_pdire(IntelIOMMUState *s,
753 uint32_t pasid,
754 VTDPASIDDirEntry *pdire,
755 VTDPASIDEntry *pe)
756 {
757 dma_addr_t addr = pdire->val & VTD_PASID_TABLE_BASE_ADDR_MASK;
758
759 return vtd_get_pe_in_pasid_leaf_table(s, pasid, addr, pe);
760 }
761
762 /**
763 * This function gets a pasid entry from a specified pasid
764 * table (includes dir and leaf table) with a specified pasid.
765 * Sanity check should be done to ensure return a present
766 * pasid entry to caller.
767 */
768 static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
769 dma_addr_t pasid_dir_base,
770 uint32_t pasid,
771 VTDPASIDEntry *pe)
772 {
773 int ret;
774 VTDPASIDDirEntry pdire;
775
776 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base,
777 pasid, &pdire);
778 if (ret) {
779 return ret;
780 }
781
782 if (!vtd_pdire_present(&pdire)) {
783 return -VTD_FR_PASID_TABLE_INV;
784 }
785
786 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe);
787 if (ret) {
788 return ret;
789 }
790
791 if (!vtd_pe_present(pe)) {
792 return -VTD_FR_PASID_TABLE_INV;
793 }
794
795 return 0;
796 }
797
798 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s,
799 VTDContextEntry *ce,
800 VTDPASIDEntry *pe)
801 {
802 uint32_t pasid;
803 dma_addr_t pasid_dir_base;
804 int ret = 0;
805
806 pasid = VTD_CE_GET_RID2PASID(ce);
807 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
808 ret = vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe);
809
810 return ret;
811 }
812
813 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,
814 VTDContextEntry *ce,
815 bool *pe_fpd_set)
816 {
817 int ret;
818 uint32_t pasid;
819 dma_addr_t pasid_dir_base;
820 VTDPASIDDirEntry pdire;
821 VTDPASIDEntry pe;
822
823 pasid = VTD_CE_GET_RID2PASID(ce);
824 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);
825
826 /*
827 * No present bit check since fpd is meaningful even
828 * if the present bit is clear.
829 */
830 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, pasid, &pdire);
831 if (ret) {
832 return ret;
833 }
834
835 if (pdire.val & VTD_PASID_DIR_FPD) {
836 *pe_fpd_set = true;
837 return 0;
838 }
839
840 if (!vtd_pdire_present(&pdire)) {
841 return -VTD_FR_PASID_TABLE_INV;
842 }
843
844 /*
845 * No present bit check since fpd is meaningful even
846 * if the present bit is clear.
847 */
848 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, &pe);
849 if (ret) {
850 return ret;
851 }
852
853 if (pe.val[0] & VTD_PASID_ENTRY_FPD) {
854 *pe_fpd_set = true;
855 }
856
857 return 0;
858 }
859
860 /* Get the page-table level that hardware should use for the second-level
861 * page-table walk from the Address Width field of context-entry.
862 */
863 static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
864 {
865 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
866 }
867
868 static uint32_t vtd_get_iova_level(IntelIOMMUState *s,
869 VTDContextEntry *ce)
870 {
871 VTDPASIDEntry pe;
872
873 if (s->root_scalable) {
874 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
875 return VTD_PE_GET_LEVEL(&pe);
876 }
877
878 return vtd_ce_get_level(ce);
879 }
880
881 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
882 {
883 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
884 }
885
886 static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s,
887 VTDContextEntry *ce)
888 {
889 VTDPASIDEntry pe;
890
891 if (s->root_scalable) {
892 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
893 return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9;
894 }
895
896 return vtd_ce_get_agaw(ce);
897 }
898
899 static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
900 {
901 return ce->lo & VTD_CONTEXT_ENTRY_TT;
902 }
903
904 /* Only for Legacy Mode. Return true if check passed, otherwise false */
905 static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
906 VTDContextEntry *ce)
907 {
908 switch (vtd_ce_get_type(ce)) {
909 case VTD_CONTEXT_TT_MULTI_LEVEL:
910 /* Always supported */
911 break;
912 case VTD_CONTEXT_TT_DEV_IOTLB:
913 if (!x86_iommu->dt_supported) {
914 error_report_once("%s: DT specified but not supported", __func__);
915 return false;
916 }
917 break;
918 case VTD_CONTEXT_TT_PASS_THROUGH:
919 if (!x86_iommu->pt_supported) {
920 error_report_once("%s: PT specified but not supported", __func__);
921 return false;
922 }
923 break;
924 default:
925 /* Unknown type */
926 error_report_once("%s: unknown ce type: %"PRIu32, __func__,
927 vtd_ce_get_type(ce));
928 return false;
929 }
930 return true;
931 }
932
933 static inline uint64_t vtd_iova_limit(IntelIOMMUState *s,
934 VTDContextEntry *ce, uint8_t aw)
935 {
936 uint32_t ce_agaw = vtd_get_iova_agaw(s, ce);
937 return 1ULL << MIN(ce_agaw, aw);
938 }
939
940 /* Return true if IOVA passes range check, otherwise false. */
941 static inline bool vtd_iova_range_check(IntelIOMMUState *s,
942 uint64_t iova, VTDContextEntry *ce,
943 uint8_t aw)
944 {
945 /*
946 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
947 * in CAP_REG and AW in context-entry.
948 */
949 return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1));
950 }
951
952 static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
953 VTDContextEntry *ce)
954 {
955 VTDPASIDEntry pe;
956
957 if (s->root_scalable) {
958 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
959 return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR;
960 }
961
962 return vtd_ce_get_slpt_base(ce);
963 }
964
965 /*
966 * Rsvd field masks for spte:
967 * vtd_spte_rsvd 4k pages
968 * vtd_spte_rsvd_large large pages
969 */
970 static uint64_t vtd_spte_rsvd[5];
971 static uint64_t vtd_spte_rsvd_large[5];
972
973 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
974 {
975 uint64_t rsvd_mask = vtd_spte_rsvd[level];
976
977 if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
978 (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
979 /* large page */
980 rsvd_mask = vtd_spte_rsvd_large[level];
981 }
982
983 return slpte & rsvd_mask;
984 }
985
986 /* Find the VTD address space associated with a given bus number */
987 static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
988 {
989 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
990 GHashTableIter iter;
991
992 if (vtd_bus) {
993 return vtd_bus;
994 }
995
996 /*
997 * Iterate over the registered buses to find the one which
998 * currently holds this bus number and update the bus_num
999 * lookup table.
1000 */
1001 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1002 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
1003 if (pci_bus_num(vtd_bus->bus) == bus_num) {
1004 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
1005 return vtd_bus;
1006 }
1007 }
1008
1009 return NULL;
1010 }
1011
1012 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1013 * of the translation, can be used for deciding the size of large page.
1014 */
1015 static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
1016 uint64_t iova, bool is_write,
1017 uint64_t *slptep, uint32_t *slpte_level,
1018 bool *reads, bool *writes, uint8_t aw_bits)
1019 {
1020 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce);
1021 uint32_t level = vtd_get_iova_level(s, ce);
1022 uint32_t offset;
1023 uint64_t slpte;
1024 uint64_t access_right_check;
1025
1026 if (!vtd_iova_range_check(s, iova, ce, aw_bits)) {
1027 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")",
1028 __func__, iova);
1029 return -VTD_FR_ADDR_BEYOND_MGAW;
1030 }
1031
1032 /* FIXME: what is the Atomics request here? */
1033 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
1034
1035 while (true) {
1036 offset = vtd_iova_level_offset(iova, level);
1037 slpte = vtd_get_slpte(addr, offset);
1038
1039 if (slpte == (uint64_t)-1) {
1040 error_report_once("%s: detected read error on DMAR slpte "
1041 "(iova=0x%" PRIx64 ")", __func__, iova);
1042 if (level == vtd_get_iova_level(s, ce)) {
1043 /* Invalid programming of context-entry */
1044 return -VTD_FR_CONTEXT_ENTRY_INV;
1045 } else {
1046 return -VTD_FR_PAGING_ENTRY_INV;
1047 }
1048 }
1049 *reads = (*reads) && (slpte & VTD_SL_R);
1050 *writes = (*writes) && (slpte & VTD_SL_W);
1051 if (!(slpte & access_right_check)) {
1052 error_report_once("%s: detected slpte permission error "
1053 "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", "
1054 "slpte=0x%" PRIx64 ", write=%d)", __func__,
1055 iova, level, slpte, is_write);
1056 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
1057 }
1058 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
1059 error_report_once("%s: detected splte reserve non-zero "
1060 "iova=0x%" PRIx64 ", level=0x%" PRIx32
1061 "slpte=0x%" PRIx64 ")", __func__, iova,
1062 level, slpte);
1063 return -VTD_FR_PAGING_ENTRY_RSVD;
1064 }
1065
1066 if (vtd_is_last_slpte(slpte, level)) {
1067 *slptep = slpte;
1068 *slpte_level = level;
1069 return 0;
1070 }
1071 addr = vtd_get_slpte_addr(slpte, aw_bits);
1072 level--;
1073 }
1074 }
1075
1076 typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
1077
1078 /**
1079 * Constant information used during page walking
1080 *
1081 * @hook_fn: hook func to be called when detected page
1082 * @private: private data to be passed into hook func
1083 * @notify_unmap: whether we should notify invalid entries
1084 * @as: VT-d address space of the device
1085 * @aw: maximum address width
1086 * @domain: domain ID of the page walk
1087 */
1088 typedef struct {
1089 VTDAddressSpace *as;
1090 vtd_page_walk_hook hook_fn;
1091 void *private;
1092 bool notify_unmap;
1093 uint8_t aw;
1094 uint16_t domain_id;
1095 } vtd_page_walk_info;
1096
1097 static int vtd_page_walk_one(IOMMUTLBEntry *entry, vtd_page_walk_info *info)
1098 {
1099 VTDAddressSpace *as = info->as;
1100 vtd_page_walk_hook hook_fn = info->hook_fn;
1101 void *private = info->private;
1102 DMAMap target = {
1103 .iova = entry->iova,
1104 .size = entry->addr_mask,
1105 .translated_addr = entry->translated_addr,
1106 .perm = entry->perm,
1107 };
1108 DMAMap *mapped = iova_tree_find(as->iova_tree, &target);
1109
1110 if (entry->perm == IOMMU_NONE && !info->notify_unmap) {
1111 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask);
1112 return 0;
1113 }
1114
1115 assert(hook_fn);
1116
1117 /* Update local IOVA mapped ranges */
1118 if (entry->perm) {
1119 if (mapped) {
1120 /* If it's exactly the same translation, skip */
1121 if (!memcmp(mapped, &target, sizeof(target))) {
1122 trace_vtd_page_walk_one_skip_map(entry->iova, entry->addr_mask,
1123 entry->translated_addr);
1124 return 0;
1125 } else {
1126 /*
1127 * Translation changed. Normally this should not
1128 * happen, but it can happen when with buggy guest
1129 * OSes. Note that there will be a small window that
1130 * we don't have map at all. But that's the best
1131 * effort we can do. The ideal way to emulate this is
1132 * atomically modify the PTE to follow what has
1133 * changed, but we can't. One example is that vfio
1134 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no
1135 * interface to modify a mapping (meanwhile it seems
1136 * meaningless to even provide one). Anyway, let's
1137 * mark this as a TODO in case one day we'll have
1138 * a better solution.
1139 */
1140 IOMMUAccessFlags cache_perm = entry->perm;
1141 int ret;
1142
1143 /* Emulate an UNMAP */
1144 entry->perm = IOMMU_NONE;
1145 trace_vtd_page_walk_one(info->domain_id,
1146 entry->iova,
1147 entry->translated_addr,
1148 entry->addr_mask,
1149 entry->perm);
1150 ret = hook_fn(entry, private);
1151 if (ret) {
1152 return ret;
1153 }
1154 /* Drop any existing mapping */
1155 iova_tree_remove(as->iova_tree, &target);
1156 /* Recover the correct permission */
1157 entry->perm = cache_perm;
1158 }
1159 }
1160 iova_tree_insert(as->iova_tree, &target);
1161 } else {
1162 if (!mapped) {
1163 /* Skip since we didn't map this range at all */
1164 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask);
1165 return 0;
1166 }
1167 iova_tree_remove(as->iova_tree, &target);
1168 }
1169
1170 trace_vtd_page_walk_one(info->domain_id, entry->iova,
1171 entry->translated_addr, entry->addr_mask,
1172 entry->perm);
1173 return hook_fn(entry, private);
1174 }
1175
1176 /**
1177 * vtd_page_walk_level - walk over specific level for IOVA range
1178 *
1179 * @addr: base GPA addr to start the walk
1180 * @start: IOVA range start address
1181 * @end: IOVA range end address (start <= addr < end)
1182 * @read: whether parent level has read permission
1183 * @write: whether parent level has write permission
1184 * @info: constant information for the page walk
1185 */
1186 static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
1187 uint64_t end, uint32_t level, bool read,
1188 bool write, vtd_page_walk_info *info)
1189 {
1190 bool read_cur, write_cur, entry_valid;
1191 uint32_t offset;
1192 uint64_t slpte;
1193 uint64_t subpage_size, subpage_mask;
1194 IOMMUTLBEntry entry;
1195 uint64_t iova = start;
1196 uint64_t iova_next;
1197 int ret = 0;
1198
1199 trace_vtd_page_walk_level(addr, level, start, end);
1200
1201 subpage_size = 1ULL << vtd_slpt_level_shift(level);
1202 subpage_mask = vtd_slpt_level_page_mask(level);
1203
1204 while (iova < end) {
1205 iova_next = (iova & subpage_mask) + subpage_size;
1206
1207 offset = vtd_iova_level_offset(iova, level);
1208 slpte = vtd_get_slpte(addr, offset);
1209
1210 if (slpte == (uint64_t)-1) {
1211 trace_vtd_page_walk_skip_read(iova, iova_next);
1212 goto next;
1213 }
1214
1215 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
1216 trace_vtd_page_walk_skip_reserve(iova, iova_next);
1217 goto next;
1218 }
1219
1220 /* Permissions are stacked with parents' */
1221 read_cur = read && (slpte & VTD_SL_R);
1222 write_cur = write && (slpte & VTD_SL_W);
1223
1224 /*
1225 * As long as we have either read/write permission, this is a
1226 * valid entry. The rule works for both page entries and page
1227 * table entries.
1228 */
1229 entry_valid = read_cur | write_cur;
1230
1231 if (!vtd_is_last_slpte(slpte, level) && entry_valid) {
1232 /*
1233 * This is a valid PDE (or even bigger than PDE). We need
1234 * to walk one further level.
1235 */
1236 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
1237 iova, MIN(iova_next, end), level - 1,
1238 read_cur, write_cur, info);
1239 } else {
1240 /*
1241 * This means we are either:
1242 *
1243 * (1) the real page entry (either 4K page, or huge page)
1244 * (2) the whole range is invalid
1245 *
1246 * In either case, we send an IOTLB notification down.
1247 */
1248 entry.target_as = &address_space_memory;
1249 entry.iova = iova & subpage_mask;
1250 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
1251 entry.addr_mask = ~subpage_mask;
1252 /* NOTE: this is only meaningful if entry_valid == true */
1253 entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
1254 ret = vtd_page_walk_one(&entry, info);
1255 }
1256
1257 if (ret < 0) {
1258 return ret;
1259 }
1260
1261 next:
1262 iova = iova_next;
1263 }
1264
1265 return 0;
1266 }
1267
1268 /**
1269 * vtd_page_walk - walk specific IOVA range, and call the hook
1270 *
1271 * @s: intel iommu state
1272 * @ce: context entry to walk upon
1273 * @start: IOVA address to start the walk
1274 * @end: IOVA range end address (start <= addr < end)
1275 * @info: page walking information struct
1276 */
1277 static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce,
1278 uint64_t start, uint64_t end,
1279 vtd_page_walk_info *info)
1280 {
1281 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce);
1282 uint32_t level = vtd_get_iova_level(s, ce);
1283
1284 if (!vtd_iova_range_check(s, start, ce, info->aw)) {
1285 return -VTD_FR_ADDR_BEYOND_MGAW;
1286 }
1287
1288 if (!vtd_iova_range_check(s, end, ce, info->aw)) {
1289 /* Fix end so that it reaches the maximum */
1290 end = vtd_iova_limit(s, ce, info->aw);
1291 }
1292
1293 return vtd_page_walk_level(addr, start, end, level, true, true, info);
1294 }
1295
1296 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState *s,
1297 VTDRootEntry *re)
1298 {
1299 /* Legacy Mode reserved bits check */
1300 if (!s->root_scalable &&
1301 (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits))))
1302 goto rsvd_err;
1303
1304 /* Scalable Mode reserved bits check */
1305 if (s->root_scalable &&
1306 ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) ||
1307 (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits))))
1308 goto rsvd_err;
1309
1310 return 0;
1311
1312 rsvd_err:
1313 error_report_once("%s: invalid root entry: hi=0x%"PRIx64
1314 ", lo=0x%"PRIx64,
1315 __func__, re->hi, re->lo);
1316 return -VTD_FR_ROOT_ENTRY_RSVD;
1317 }
1318
1319 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState *s,
1320 VTDContextEntry *ce)
1321 {
1322 if (!s->root_scalable &&
1323 (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI ||
1324 ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) {
1325 error_report_once("%s: invalid context entry: hi=%"PRIx64
1326 ", lo=%"PRIx64" (reserved nonzero)",
1327 __func__, ce->hi, ce->lo);
1328 return -VTD_FR_CONTEXT_ENTRY_RSVD;
1329 }
1330
1331 if (s->root_scalable &&
1332 (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) ||
1333 ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 ||
1334 ce->val[2] ||
1335 ce->val[3])) {
1336 error_report_once("%s: invalid context entry: val[3]=%"PRIx64
1337 ", val[2]=%"PRIx64
1338 ", val[1]=%"PRIx64
1339 ", val[0]=%"PRIx64" (reserved nonzero)",
1340 __func__, ce->val[3], ce->val[2],
1341 ce->val[1], ce->val[0]);
1342 return -VTD_FR_CONTEXT_ENTRY_RSVD;
1343 }
1344
1345 return 0;
1346 }
1347
1348 static int vtd_ce_rid2pasid_check(IntelIOMMUState *s,
1349 VTDContextEntry *ce)
1350 {
1351 VTDPASIDEntry pe;
1352
1353 /*
1354 * Make sure in Scalable Mode, a present context entry
1355 * has valid rid2pasid setting, which includes valid
1356 * rid2pasid field and corresponding pasid entry setting
1357 */
1358 return vtd_ce_get_rid2pasid_entry(s, ce, &pe);
1359 }
1360
1361 /* Map a device to its corresponding domain (context-entry) */
1362 static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
1363 uint8_t devfn, VTDContextEntry *ce)
1364 {
1365 VTDRootEntry re;
1366 int ret_fr;
1367 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1368
1369 ret_fr = vtd_get_root_entry(s, bus_num, &re);
1370 if (ret_fr) {
1371 return ret_fr;
1372 }
1373
1374 if (!vtd_root_entry_present(s, &re, devfn)) {
1375 /* Not error - it's okay we don't have root entry. */
1376 trace_vtd_re_not_present(bus_num);
1377 return -VTD_FR_ROOT_ENTRY_P;
1378 }
1379
1380 ret_fr = vtd_root_entry_rsvd_bits_check(s, &re);
1381 if (ret_fr) {
1382 return ret_fr;
1383 }
1384
1385 ret_fr = vtd_get_context_entry_from_root(s, &re, devfn, ce);
1386 if (ret_fr) {
1387 return ret_fr;
1388 }
1389
1390 if (!vtd_ce_present(ce)) {
1391 /* Not error - it's okay we don't have context entry. */
1392 trace_vtd_ce_not_present(bus_num, devfn);
1393 return -VTD_FR_CONTEXT_ENTRY_P;
1394 }
1395
1396 ret_fr = vtd_context_entry_rsvd_bits_check(s, ce);
1397 if (ret_fr) {
1398 return ret_fr;
1399 }
1400
1401 /* Check if the programming of context-entry is valid */
1402 if (!s->root_scalable &&
1403 !vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
1404 error_report_once("%s: invalid context entry: hi=%"PRIx64
1405 ", lo=%"PRIx64" (level %d not supported)",
1406 __func__, ce->hi, ce->lo,
1407 vtd_ce_get_level(ce));
1408 return -VTD_FR_CONTEXT_ENTRY_INV;
1409 }
1410
1411 if (!s->root_scalable) {
1412 /* Do translation type check */
1413 if (!vtd_ce_type_check(x86_iommu, ce)) {
1414 /* Errors dumped in vtd_ce_type_check() */
1415 return -VTD_FR_CONTEXT_ENTRY_INV;
1416 }
1417 } else {
1418 /*
1419 * Check if the programming of context-entry.rid2pasid
1420 * and corresponding pasid setting is valid, and thus
1421 * avoids to check pasid entry fetching result in future
1422 * helper function calling.
1423 */
1424 ret_fr = vtd_ce_rid2pasid_check(s, ce);
1425 if (ret_fr) {
1426 return ret_fr;
1427 }
1428 }
1429
1430 return 0;
1431 }
1432
1433 static int vtd_sync_shadow_page_hook(IOMMUTLBEntry *entry,
1434 void *private)
1435 {
1436 memory_region_notify_iommu((IOMMUMemoryRegion *)private, 0, *entry);
1437 return 0;
1438 }
1439
1440 static uint16_t vtd_get_domain_id(IntelIOMMUState *s,
1441 VTDContextEntry *ce)
1442 {
1443 VTDPASIDEntry pe;
1444
1445 if (s->root_scalable) {
1446 vtd_ce_get_rid2pasid_entry(s, ce, &pe);
1447 return VTD_SM_PASID_ENTRY_DID(pe.val[1]);
1448 }
1449
1450 return VTD_CONTEXT_ENTRY_DID(ce->hi);
1451 }
1452
1453 static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as,
1454 VTDContextEntry *ce,
1455 hwaddr addr, hwaddr size)
1456 {
1457 IntelIOMMUState *s = vtd_as->iommu_state;
1458 vtd_page_walk_info info = {
1459 .hook_fn = vtd_sync_shadow_page_hook,
1460 .private = (void *)&vtd_as->iommu,
1461 .notify_unmap = true,
1462 .aw = s->aw_bits,
1463 .as = vtd_as,
1464 .domain_id = vtd_get_domain_id(s, ce),
1465 };
1466
1467 return vtd_page_walk(s, ce, addr, addr + size, &info);
1468 }
1469
1470 static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as)
1471 {
1472 int ret;
1473 VTDContextEntry ce;
1474 IOMMUNotifier *n;
1475
1476 ret = vtd_dev_to_context_entry(vtd_as->iommu_state,
1477 pci_bus_num(vtd_as->bus),
1478 vtd_as->devfn, &ce);
1479 if (ret) {
1480 if (ret == -VTD_FR_CONTEXT_ENTRY_P) {
1481 /*
1482 * It's a valid scenario to have a context entry that is
1483 * not present. For example, when a device is removed
1484 * from an existing domain then the context entry will be
1485 * zeroed by the guest before it was put into another
1486 * domain. When this happens, instead of synchronizing
1487 * the shadow pages we should invalidate all existing
1488 * mappings and notify the backends.
1489 */
1490 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
1491 vtd_address_space_unmap(vtd_as, n);
1492 }
1493 ret = 0;
1494 }
1495 return ret;
1496 }
1497
1498 return vtd_sync_shadow_page_table_range(vtd_as, &ce, 0, UINT64_MAX);
1499 }
1500
1501 /*
1502 * Check if specific device is configed to bypass address
1503 * translation for DMA requests. In Scalable Mode, bypass
1504 * 1st-level translation or 2nd-level translation, it depends
1505 * on PGTT setting.
1506 */
1507 static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
1508 {
1509 IntelIOMMUState *s;
1510 VTDContextEntry ce;
1511 VTDPASIDEntry pe;
1512 int ret;
1513
1514 assert(as);
1515
1516 s = as->iommu_state;
1517 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
1518 as->devfn, &ce);
1519 if (ret) {
1520 /*
1521 * Possibly failed to parse the context entry for some reason
1522 * (e.g., during init, or any guest configuration errors on
1523 * context entries). We should assume PT not enabled for
1524 * safety.
1525 */
1526 return false;
1527 }
1528
1529 if (s->root_scalable) {
1530 ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe);
1531 if (ret) {
1532 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32,
1533 __func__, ret);
1534 return false;
1535 }
1536 return (VTD_PE_GET_TYPE(&pe) == VTD_SM_PASID_ENTRY_PT);
1537 }
1538
1539 return (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH);
1540 }
1541
1542 /* Return whether the device is using IOMMU translation. */
1543 static bool vtd_switch_address_space(VTDAddressSpace *as)
1544 {
1545 bool use_iommu;
1546 /* Whether we need to take the BQL on our own */
1547 bool take_bql = !qemu_mutex_iothread_locked();
1548
1549 assert(as);
1550
1551 use_iommu = as->iommu_state->dmar_enabled && !vtd_dev_pt_enabled(as);
1552
1553 trace_vtd_switch_address_space(pci_bus_num(as->bus),
1554 VTD_PCI_SLOT(as->devfn),
1555 VTD_PCI_FUNC(as->devfn),
1556 use_iommu);
1557
1558 /*
1559 * It's possible that we reach here without BQL, e.g., when called
1560 * from vtd_pt_enable_fast_path(). However the memory APIs need
1561 * it. We'd better make sure we have had it already, or, take it.
1562 */
1563 if (take_bql) {
1564 qemu_mutex_lock_iothread();
1565 }
1566
1567 /* Turn off first then on the other */
1568 if (use_iommu) {
1569 memory_region_set_enabled(&as->nodmar, false);
1570 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true);
1571 } else {
1572 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false);
1573 memory_region_set_enabled(&as->nodmar, true);
1574 }
1575
1576 if (take_bql) {
1577 qemu_mutex_unlock_iothread();
1578 }
1579
1580 return use_iommu;
1581 }
1582
1583 static void vtd_switch_address_space_all(IntelIOMMUState *s)
1584 {
1585 GHashTableIter iter;
1586 VTDBus *vtd_bus;
1587 int i;
1588
1589 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1590 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
1591 for (i = 0; i < PCI_DEVFN_MAX; i++) {
1592 if (!vtd_bus->dev_as[i]) {
1593 continue;
1594 }
1595 vtd_switch_address_space(vtd_bus->dev_as[i]);
1596 }
1597 }
1598 }
1599
1600 static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
1601 {
1602 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
1603 }
1604
1605 static const bool vtd_qualified_faults[] = {
1606 [VTD_FR_RESERVED] = false,
1607 [VTD_FR_ROOT_ENTRY_P] = false,
1608 [VTD_FR_CONTEXT_ENTRY_P] = true,
1609 [VTD_FR_CONTEXT_ENTRY_INV] = true,
1610 [VTD_FR_ADDR_BEYOND_MGAW] = true,
1611 [VTD_FR_WRITE] = true,
1612 [VTD_FR_READ] = true,
1613 [VTD_FR_PAGING_ENTRY_INV] = true,
1614 [VTD_FR_ROOT_TABLE_INV] = false,
1615 [VTD_FR_CONTEXT_TABLE_INV] = false,
1616 [VTD_FR_ROOT_ENTRY_RSVD] = false,
1617 [VTD_FR_PAGING_ENTRY_RSVD] = true,
1618 [VTD_FR_CONTEXT_ENTRY_TT] = true,
1619 [VTD_FR_PASID_TABLE_INV] = false,
1620 [VTD_FR_RESERVED_ERR] = false,
1621 [VTD_FR_MAX] = false,
1622 };
1623
1624 /* To see if a fault condition is "qualified", which is reported to software
1625 * only if the FPD field in the context-entry used to process the faulting
1626 * request is 0.
1627 */
1628 static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
1629 {
1630 return vtd_qualified_faults[fault];
1631 }
1632
1633 static inline bool vtd_is_interrupt_addr(hwaddr addr)
1634 {
1635 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
1636 }
1637
1638 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
1639 {
1640 VTDBus *vtd_bus;
1641 VTDAddressSpace *vtd_as;
1642 bool success = false;
1643
1644 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1645 if (!vtd_bus) {
1646 goto out;
1647 }
1648
1649 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
1650 if (!vtd_as) {
1651 goto out;
1652 }
1653
1654 if (vtd_switch_address_space(vtd_as) == false) {
1655 /* We switched off IOMMU region successfully. */
1656 success = true;
1657 }
1658
1659 out:
1660 trace_vtd_pt_enable_fast_path(source_id, success);
1661 }
1662
1663 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1664 * translation.
1665 *
1666 * Called from RCU critical section.
1667 *
1668 * @bus_num: The bus number
1669 * @devfn: The devfn, which is the combined of device and function number
1670 * @is_write: The access is a write operation
1671 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1672 *
1673 * Returns true if translation is successful, otherwise false.
1674 */
1675 static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1676 uint8_t devfn, hwaddr addr, bool is_write,
1677 IOMMUTLBEntry *entry)
1678 {
1679 IntelIOMMUState *s = vtd_as->iommu_state;
1680 VTDContextEntry ce;
1681 uint8_t bus_num = pci_bus_num(bus);
1682 VTDContextCacheEntry *cc_entry;
1683 uint64_t slpte, page_mask;
1684 uint32_t level;
1685 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
1686 int ret_fr;
1687 bool is_fpd_set = false;
1688 bool reads = true;
1689 bool writes = true;
1690 uint8_t access_flags;
1691 VTDIOTLBEntry *iotlb_entry;
1692
1693 /*
1694 * We have standalone memory region for interrupt addresses, we
1695 * should never receive translation requests in this region.
1696 */
1697 assert(!vtd_is_interrupt_addr(addr));
1698
1699 vtd_iommu_lock(s);
1700
1701 cc_entry = &vtd_as->context_cache_entry;
1702
1703 /* Try to fetch slpte form IOTLB */
1704 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
1705 if (iotlb_entry) {
1706 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
1707 iotlb_entry->domain_id);
1708 slpte = iotlb_entry->slpte;
1709 access_flags = iotlb_entry->access_flags;
1710 page_mask = iotlb_entry->mask;
1711 goto out;
1712 }
1713
1714 /* Try to fetch context-entry from cache first */
1715 if (cc_entry->context_cache_gen == s->context_cache_gen) {
1716 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
1717 cc_entry->context_entry.lo,
1718 cc_entry->context_cache_gen);
1719 ce = cc_entry->context_entry;
1720 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1721 if (!is_fpd_set && s->root_scalable) {
1722 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set);
1723 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1724 }
1725 } else {
1726 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
1727 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1728 if (!ret_fr && !is_fpd_set && s->root_scalable) {
1729 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set);
1730 }
1731 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1732 /* Update context-cache */
1733 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1734 cc_entry->context_cache_gen,
1735 s->context_cache_gen);
1736 cc_entry->context_entry = ce;
1737 cc_entry->context_cache_gen = s->context_cache_gen;
1738 }
1739
1740 /*
1741 * We don't need to translate for pass-through context entries.
1742 * Also, let's ignore IOTLB caching as well for PT devices.
1743 */
1744 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
1745 entry->iova = addr & VTD_PAGE_MASK_4K;
1746 entry->translated_addr = entry->iova;
1747 entry->addr_mask = ~VTD_PAGE_MASK_4K;
1748 entry->perm = IOMMU_RW;
1749 trace_vtd_translate_pt(source_id, entry->iova);
1750
1751 /*
1752 * When this happens, it means firstly caching-mode is not
1753 * enabled, and this is the first passthrough translation for
1754 * the device. Let's enable the fast path for passthrough.
1755 *
1756 * When passthrough is disabled again for the device, we can
1757 * capture it via the context entry invalidation, then the
1758 * IOMMU region can be swapped back.
1759 */
1760 vtd_pt_enable_fast_path(s, source_id);
1761 vtd_iommu_unlock(s);
1762 return true;
1763 }
1764
1765 ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level,
1766 &reads, &writes, s->aw_bits);
1767 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write);
1768
1769 page_mask = vtd_slpt_level_page_mask(level);
1770 access_flags = IOMMU_ACCESS_FLAG(reads, writes);
1771 vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte,
1772 access_flags, level);
1773 out:
1774 vtd_iommu_unlock(s);
1775 entry->iova = addr & page_mask;
1776 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
1777 entry->addr_mask = ~page_mask;
1778 entry->perm = access_flags;
1779 return true;
1780
1781 error:
1782 vtd_iommu_unlock(s);
1783 entry->iova = 0;
1784 entry->translated_addr = 0;
1785 entry->addr_mask = 0;
1786 entry->perm = IOMMU_NONE;
1787 return false;
1788 }
1789
1790 static void vtd_root_table_setup(IntelIOMMUState *s)
1791 {
1792 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1793 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits);
1794
1795 vtd_update_scalable_state(s);
1796
1797 trace_vtd_reg_dmar_root(s->root, s->root_scalable);
1798 }
1799
1800 static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1801 uint32_t index, uint32_t mask)
1802 {
1803 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1804 }
1805
1806 static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1807 {
1808 uint64_t value = 0;
1809 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1810 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
1811 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits);
1812 s->intr_eime = value & VTD_IRTA_EIME;
1813
1814 /* Notify global invalidation */
1815 vtd_iec_notify_all(s, true, 0, 0);
1816
1817 trace_vtd_reg_ir_root(s->intr_root, s->intr_size);
1818 }
1819
1820 static void vtd_iommu_replay_all(IntelIOMMUState *s)
1821 {
1822 VTDAddressSpace *vtd_as;
1823
1824 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
1825 vtd_sync_shadow_page_table(vtd_as);
1826 }
1827 }
1828
1829 static void vtd_context_global_invalidate(IntelIOMMUState *s)
1830 {
1831 trace_vtd_inv_desc_cc_global();
1832 /* Protects context cache */
1833 vtd_iommu_lock(s);
1834 s->context_cache_gen++;
1835 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1836 vtd_reset_context_cache_locked(s);
1837 }
1838 vtd_iommu_unlock(s);
1839 vtd_address_space_refresh_all(s);
1840 /*
1841 * From VT-d spec 6.5.2.1, a global context entry invalidation
1842 * should be followed by a IOTLB global invalidation, so we should
1843 * be safe even without this. Hoewever, let's replay the region as
1844 * well to be safer, and go back here when we need finer tunes for
1845 * VT-d emulation codes.
1846 */
1847 vtd_iommu_replay_all(s);
1848 }
1849
1850 /* Do a context-cache device-selective invalidation.
1851 * @func_mask: FM field after shifting
1852 */
1853 static void vtd_context_device_invalidate(IntelIOMMUState *s,
1854 uint16_t source_id,
1855 uint16_t func_mask)
1856 {
1857 uint16_t mask;
1858 VTDBus *vtd_bus;
1859 VTDAddressSpace *vtd_as;
1860 uint8_t bus_n, devfn;
1861 uint16_t devfn_it;
1862
1863 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1864
1865 switch (func_mask & 3) {
1866 case 0:
1867 mask = 0; /* No bits in the SID field masked */
1868 break;
1869 case 1:
1870 mask = 4; /* Mask bit 2 in the SID field */
1871 break;
1872 case 2:
1873 mask = 6; /* Mask bit 2:1 in the SID field */
1874 break;
1875 case 3:
1876 mask = 7; /* Mask bit 2:0 in the SID field */
1877 break;
1878 }
1879 mask = ~mask;
1880
1881 bus_n = VTD_SID_TO_BUS(source_id);
1882 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
1883 if (vtd_bus) {
1884 devfn = VTD_SID_TO_DEVFN(source_id);
1885 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
1886 vtd_as = vtd_bus->dev_as[devfn_it];
1887 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
1888 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1889 VTD_PCI_FUNC(devfn_it));
1890 vtd_iommu_lock(s);
1891 vtd_as->context_cache_entry.context_cache_gen = 0;
1892 vtd_iommu_unlock(s);
1893 /*
1894 * Do switch address space when needed, in case if the
1895 * device passthrough bit is switched.
1896 */
1897 vtd_switch_address_space(vtd_as);
1898 /*
1899 * So a device is moving out of (or moving into) a
1900 * domain, resync the shadow page table.
1901 * This won't bring bad even if we have no such
1902 * notifier registered - the IOMMU notification
1903 * framework will skip MAP notifications if that
1904 * happened.
1905 */
1906 vtd_sync_shadow_page_table(vtd_as);
1907 }
1908 }
1909 }
1910 }
1911
1912 /* Context-cache invalidation
1913 * Returns the Context Actual Invalidation Granularity.
1914 * @val: the content of the CCMD_REG
1915 */
1916 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1917 {
1918 uint64_t caig;
1919 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1920
1921 switch (type) {
1922 case VTD_CCMD_DOMAIN_INVL:
1923 /* Fall through */
1924 case VTD_CCMD_GLOBAL_INVL:
1925 caig = VTD_CCMD_GLOBAL_INVL_A;
1926 vtd_context_global_invalidate(s);
1927 break;
1928
1929 case VTD_CCMD_DEVICE_INVL:
1930 caig = VTD_CCMD_DEVICE_INVL_A;
1931 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1932 break;
1933
1934 default:
1935 error_report_once("%s: invalid context: 0x%" PRIx64,
1936 __func__, val);
1937 caig = 0;
1938 }
1939 return caig;
1940 }
1941
1942 static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1943 {
1944 trace_vtd_inv_desc_iotlb_global();
1945 vtd_reset_iotlb(s);
1946 vtd_iommu_replay_all(s);
1947 }
1948
1949 static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1950 {
1951 VTDContextEntry ce;
1952 VTDAddressSpace *vtd_as;
1953
1954 trace_vtd_inv_desc_iotlb_domain(domain_id);
1955
1956 vtd_iommu_lock(s);
1957 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1958 &domain_id);
1959 vtd_iommu_unlock(s);
1960
1961 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
1962 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1963 vtd_as->devfn, &ce) &&
1964 domain_id == vtd_get_domain_id(s, &ce)) {
1965 vtd_sync_shadow_page_table(vtd_as);
1966 }
1967 }
1968 }
1969
1970 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1971 uint16_t domain_id, hwaddr addr,
1972 uint8_t am)
1973 {
1974 VTDAddressSpace *vtd_as;
1975 VTDContextEntry ce;
1976 int ret;
1977 hwaddr size = (1 << am) * VTD_PAGE_SIZE;
1978
1979 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
1980 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1981 vtd_as->devfn, &ce);
1982 if (!ret && domain_id == vtd_get_domain_id(s, &ce)) {
1983 if (vtd_as_has_map_notifier(vtd_as)) {
1984 /*
1985 * As long as we have MAP notifications registered in
1986 * any of our IOMMU notifiers, we need to sync the
1987 * shadow page table.
1988 */
1989 vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
1990 } else {
1991 /*
1992 * For UNMAP-only notifiers, we don't need to walk the
1993 * page tables. We just deliver the PSI down to
1994 * invalidate caches.
1995 */
1996 IOMMUTLBEntry entry = {
1997 .target_as = &address_space_memory,
1998 .iova = addr,
1999 .translated_addr = 0,
2000 .addr_mask = size - 1,
2001 .perm = IOMMU_NONE,
2002 };
2003 memory_region_notify_iommu(&vtd_as->iommu, 0, entry);
2004 }
2005 }
2006 }
2007 }
2008
2009 static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
2010 hwaddr addr, uint8_t am)
2011 {
2012 VTDIOTLBPageInvInfo info;
2013
2014 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
2015
2016 assert(am <= VTD_MAMV);
2017 info.domain_id = domain_id;
2018 info.addr = addr;
2019 info.mask = ~((1 << am) - 1);
2020 vtd_iommu_lock(s);
2021 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
2022 vtd_iommu_unlock(s);
2023 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
2024 }
2025
2026 /* Flush IOTLB
2027 * Returns the IOTLB Actual Invalidation Granularity.
2028 * @val: the content of the IOTLB_REG
2029 */
2030 static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
2031 {
2032 uint64_t iaig;
2033 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
2034 uint16_t domain_id;
2035 hwaddr addr;
2036 uint8_t am;
2037
2038 switch (type) {
2039 case VTD_TLB_GLOBAL_FLUSH:
2040 iaig = VTD_TLB_GLOBAL_FLUSH_A;
2041 vtd_iotlb_global_invalidate(s);
2042 break;
2043
2044 case VTD_TLB_DSI_FLUSH:
2045 domain_id = VTD_TLB_DID(val);
2046 iaig = VTD_TLB_DSI_FLUSH_A;
2047 vtd_iotlb_domain_invalidate(s, domain_id);
2048 break;
2049
2050 case VTD_TLB_PSI_FLUSH:
2051 domain_id = VTD_TLB_DID(val);
2052 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
2053 am = VTD_IVA_AM(addr);
2054 addr = VTD_IVA_ADDR(addr);
2055 if (am > VTD_MAMV) {
2056 error_report_once("%s: address mask overflow: 0x%" PRIx64,
2057 __func__, vtd_get_quad_raw(s, DMAR_IVA_REG));
2058 iaig = 0;
2059 break;
2060 }
2061 iaig = VTD_TLB_PSI_FLUSH_A;
2062 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
2063 break;
2064
2065 default:
2066 error_report_once("%s: invalid granularity: 0x%" PRIx64,
2067 __func__, val);
2068 iaig = 0;
2069 }
2070 return iaig;
2071 }
2072
2073 static void vtd_fetch_inv_desc(IntelIOMMUState *s);
2074
2075 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
2076 {
2077 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
2078 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
2079 }
2080
2081 static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
2082 {
2083 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
2084
2085 trace_vtd_inv_qi_enable(en);
2086
2087 if (en) {
2088 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits);
2089 /* 2^(x+8) entries */
2090 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 : 0));
2091 s->qi_enabled = true;
2092 trace_vtd_inv_qi_setup(s->iq, s->iq_size);
2093 /* Ok - report back to driver */
2094 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
2095
2096 if (s->iq_tail != 0) {
2097 /*
2098 * This is a spec violation but Windows guests are known to set up
2099 * Queued Invalidation this way so we allow the write and process
2100 * Invalidation Descriptors right away.
2101 */
2102 trace_vtd_warn_invalid_qi_tail(s->iq_tail);
2103 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
2104 vtd_fetch_inv_desc(s);
2105 }
2106 }
2107 } else {
2108 if (vtd_queued_inv_disable_check(s)) {
2109 /* disable Queued Invalidation */
2110 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
2111 s->iq_head = 0;
2112 s->qi_enabled = false;
2113 /* Ok - report back to driver */
2114 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
2115 } else {
2116 error_report_once("%s: detected improper state when disable QI "
2117 "(head=0x%x, tail=0x%x, last_type=%d)",
2118 __func__,
2119 s->iq_head, s->iq_tail, s->iq_last_desc_type);
2120 }
2121 }
2122 }
2123
2124 /* Set Root Table Pointer */
2125 static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
2126 {
2127 vtd_root_table_setup(s);
2128 /* Ok - report back to driver */
2129 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
2130 vtd_reset_caches(s);
2131 vtd_address_space_refresh_all(s);
2132 }
2133
2134 /* Set Interrupt Remap Table Pointer */
2135 static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
2136 {
2137 vtd_interrupt_remap_table_setup(s);
2138 /* Ok - report back to driver */
2139 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
2140 }
2141
2142 /* Handle Translation Enable/Disable */
2143 static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
2144 {
2145 if (s->dmar_enabled == en) {
2146 return;
2147 }
2148
2149 trace_vtd_dmar_enable(en);
2150
2151 if (en) {
2152 s->dmar_enabled = true;
2153 /* Ok - report back to driver */
2154 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
2155 } else {
2156 s->dmar_enabled = false;
2157
2158 /* Clear the index of Fault Recording Register */
2159 s->next_frcd_reg = 0;
2160 /* Ok - report back to driver */
2161 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
2162 }
2163
2164 vtd_reset_caches(s);
2165 vtd_address_space_refresh_all(s);
2166 }
2167
2168 /* Handle Interrupt Remap Enable/Disable */
2169 static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
2170 {
2171 trace_vtd_ir_enable(en);
2172
2173 if (en) {
2174 s->intr_enabled = true;
2175 /* Ok - report back to driver */
2176 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
2177 } else {
2178 s->intr_enabled = false;
2179 /* Ok - report back to driver */
2180 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
2181 }
2182 }
2183
2184 /* Handle write to Global Command Register */
2185 static void vtd_handle_gcmd_write(IntelIOMMUState *s)
2186 {
2187 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
2188 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
2189 uint32_t changed = status ^ val;
2190
2191 trace_vtd_reg_write_gcmd(status, val);
2192 if (changed & VTD_GCMD_TE) {
2193 /* Translation enable/disable */
2194 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
2195 }
2196 if (val & VTD_GCMD_SRTP) {
2197 /* Set/update the root-table pointer */
2198 vtd_handle_gcmd_srtp(s);
2199 }
2200 if (changed & VTD_GCMD_QIE) {
2201 /* Queued Invalidation Enable */
2202 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
2203 }
2204 if (val & VTD_GCMD_SIRTP) {
2205 /* Set/update the interrupt remapping root-table pointer */
2206 vtd_handle_gcmd_sirtp(s);
2207 }
2208 if (changed & VTD_GCMD_IRE) {
2209 /* Interrupt remap enable/disable */
2210 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
2211 }
2212 }
2213
2214 /* Handle write to Context Command Register */
2215 static void vtd_handle_ccmd_write(IntelIOMMUState *s)
2216 {
2217 uint64_t ret;
2218 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
2219
2220 /* Context-cache invalidation request */
2221 if (val & VTD_CCMD_ICC) {
2222 if (s->qi_enabled) {
2223 error_report_once("Queued Invalidation enabled, "
2224 "should not use register-based invalidation");
2225 return;
2226 }
2227 ret = vtd_context_cache_invalidate(s, val);
2228 /* Invalidation completed. Change something to show */
2229 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
2230 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
2231 ret);
2232 }
2233 }
2234
2235 /* Handle write to IOTLB Invalidation Register */
2236 static void vtd_handle_iotlb_write(IntelIOMMUState *s)
2237 {
2238 uint64_t ret;
2239 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
2240
2241 /* IOTLB invalidation request */
2242 if (val & VTD_TLB_IVT) {
2243 if (s->qi_enabled) {
2244 error_report_once("Queued Invalidation enabled, "
2245 "should not use register-based invalidation");
2246 return;
2247 }
2248 ret = vtd_iotlb_flush(s, val);
2249 /* Invalidation completed. Change something to show */
2250 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
2251 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
2252 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
2253 }
2254 }
2255
2256 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
2257 static bool vtd_get_inv_desc(IntelIOMMUState *s,
2258 VTDInvDesc *inv_desc)
2259 {
2260 dma_addr_t base_addr = s->iq;
2261 uint32_t offset = s->iq_head;
2262 uint32_t dw = s->iq_dw ? 32 : 16;
2263 dma_addr_t addr = base_addr + offset * dw;
2264
2265 if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) {
2266 error_report_once("Read INV DESC failed.");
2267 return false;
2268 }
2269 inv_desc->lo = le64_to_cpu(inv_desc->lo);
2270 inv_desc->hi = le64_to_cpu(inv_desc->hi);
2271 if (dw == 32) {
2272 inv_desc->val[2] = le64_to_cpu(inv_desc->val[2]);
2273 inv_desc->val[3] = le64_to_cpu(inv_desc->val[3]);
2274 }
2275 return true;
2276 }
2277
2278 static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
2279 {
2280 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
2281 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
2282 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64
2283 " (reserved nonzero)", __func__, inv_desc->hi,
2284 inv_desc->lo);
2285 return false;
2286 }
2287 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
2288 /* Status Write */
2289 uint32_t status_data = (uint32_t)(inv_desc->lo >>
2290 VTD_INV_DESC_WAIT_DATA_SHIFT);
2291
2292 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
2293
2294 /* FIXME: need to be masked with HAW? */
2295 dma_addr_t status_addr = inv_desc->hi;
2296 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
2297 status_data = cpu_to_le32(status_data);
2298 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
2299 sizeof(status_data))) {
2300 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
2301 return false;
2302 }
2303 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
2304 /* Interrupt flag */
2305 vtd_generate_completion_event(s);
2306 } else {
2307 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64
2308 " (unknown type)", __func__, inv_desc->hi,
2309 inv_desc->lo);
2310 return false;
2311 }
2312 return true;
2313 }
2314
2315 static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
2316 VTDInvDesc *inv_desc)
2317 {
2318 uint16_t sid, fmask;
2319
2320 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
2321 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
2322 " (reserved nonzero)", __func__, inv_desc->hi,
2323 inv_desc->lo);
2324 return false;
2325 }
2326 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
2327 case VTD_INV_DESC_CC_DOMAIN:
2328 trace_vtd_inv_desc_cc_domain(
2329 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
2330 /* Fall through */
2331 case VTD_INV_DESC_CC_GLOBAL:
2332 vtd_context_global_invalidate(s);
2333 break;
2334
2335 case VTD_INV_DESC_CC_DEVICE:
2336 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
2337 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
2338 vtd_context_device_invalidate(s, sid, fmask);
2339 break;
2340
2341 default:
2342 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64
2343 " (invalid type)", __func__, inv_desc->hi,
2344 inv_desc->lo);
2345 return false;
2346 }
2347 return true;
2348 }
2349
2350 static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
2351 {
2352 uint16_t domain_id;
2353 uint8_t am;
2354 hwaddr addr;
2355
2356 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
2357 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
2358 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2359 ", lo=0x%"PRIx64" (reserved bits unzero)",
2360 __func__, inv_desc->hi, inv_desc->lo);
2361 return false;
2362 }
2363
2364 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
2365 case VTD_INV_DESC_IOTLB_GLOBAL:
2366 vtd_iotlb_global_invalidate(s);
2367 break;
2368
2369 case VTD_INV_DESC_IOTLB_DOMAIN:
2370 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
2371 vtd_iotlb_domain_invalidate(s, domain_id);
2372 break;
2373
2374 case VTD_INV_DESC_IOTLB_PAGE:
2375 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
2376 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
2377 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
2378 if (am > VTD_MAMV) {
2379 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2380 ", lo=0x%"PRIx64" (am=%u > VTD_MAMV=%u)",
2381 __func__, inv_desc->hi, inv_desc->lo,
2382 am, (unsigned)VTD_MAMV);
2383 return false;
2384 }
2385 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
2386 break;
2387
2388 default:
2389 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2390 ", lo=0x%"PRIx64" (type mismatch: 0x%llx)",
2391 __func__, inv_desc->hi, inv_desc->lo,
2392 inv_desc->lo & VTD_INV_DESC_IOTLB_G);
2393 return false;
2394 }
2395 return true;
2396 }
2397
2398 static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
2399 VTDInvDesc *inv_desc)
2400 {
2401 trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
2402 inv_desc->iec.index,
2403 inv_desc->iec.index_mask);
2404
2405 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
2406 inv_desc->iec.index,
2407 inv_desc->iec.index_mask);
2408 return true;
2409 }
2410
2411 static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
2412 VTDInvDesc *inv_desc)
2413 {
2414 VTDAddressSpace *vtd_dev_as;
2415 IOMMUTLBEntry entry;
2416 struct VTDBus *vtd_bus;
2417 hwaddr addr;
2418 uint64_t sz;
2419 uint16_t sid;
2420 uint8_t devfn;
2421 bool size;
2422 uint8_t bus_num;
2423
2424 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
2425 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
2426 devfn = sid & 0xff;
2427 bus_num = sid >> 8;
2428 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
2429
2430 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
2431 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
2432 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64
2433 ", lo=%"PRIx64" (reserved nonzero)", __func__,
2434 inv_desc->hi, inv_desc->lo);
2435 return false;
2436 }
2437
2438 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
2439 if (!vtd_bus) {
2440 goto done;
2441 }
2442
2443 vtd_dev_as = vtd_bus->dev_as[devfn];
2444 if (!vtd_dev_as) {
2445 goto done;
2446 }
2447
2448 /* According to ATS spec table 2.4:
2449 * S = 0, bits 15:12 = xxxx range size: 4K
2450 * S = 1, bits 15:12 = xxx0 range size: 8K
2451 * S = 1, bits 15:12 = xx01 range size: 16K
2452 * S = 1, bits 15:12 = x011 range size: 32K
2453 * S = 1, bits 15:12 = 0111 range size: 64K
2454 * ...
2455 */
2456 if (size) {
2457 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
2458 addr &= ~(sz - 1);
2459 } else {
2460 sz = VTD_PAGE_SIZE;
2461 }
2462
2463 entry.target_as = &vtd_dev_as->as;
2464 entry.addr_mask = sz - 1;
2465 entry.iova = addr;
2466 entry.perm = IOMMU_NONE;
2467 entry.translated_addr = 0;
2468 memory_region_notify_iommu(&vtd_dev_as->iommu, 0, entry);
2469
2470 done:
2471 return true;
2472 }
2473
2474 static bool vtd_process_inv_desc(IntelIOMMUState *s)
2475 {
2476 VTDInvDesc inv_desc;
2477 uint8_t desc_type;
2478
2479 trace_vtd_inv_qi_head(s->iq_head);
2480 if (!vtd_get_inv_desc(s, &inv_desc)) {
2481 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2482 return false;
2483 }
2484
2485 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
2486 /* FIXME: should update at first or at last? */
2487 s->iq_last_desc_type = desc_type;
2488
2489 switch (desc_type) {
2490 case VTD_INV_DESC_CC:
2491 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
2492 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
2493 return false;
2494 }
2495 break;
2496
2497 case VTD_INV_DESC_IOTLB:
2498 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
2499 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
2500 return false;
2501 }
2502 break;
2503
2504 /*
2505 * TODO: the entity of below two cases will be implemented in future series.
2506 * To make guest (which integrates scalable mode support patch set in
2507 * iommu driver) work, just return true is enough so far.
2508 */
2509 case VTD_INV_DESC_PC:
2510 break;
2511
2512 case VTD_INV_DESC_PIOTLB:
2513 break;
2514
2515 case VTD_INV_DESC_WAIT:
2516 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
2517 if (!vtd_process_wait_desc(s, &inv_desc)) {
2518 return false;
2519 }
2520 break;
2521
2522 case VTD_INV_DESC_IEC:
2523 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
2524 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
2525 return false;
2526 }
2527 break;
2528
2529 case VTD_INV_DESC_DEVICE:
2530 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
2531 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
2532 return false;
2533 }
2534 break;
2535
2536 default:
2537 error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64
2538 " (unknown type)", __func__, inv_desc.hi,
2539 inv_desc.lo);
2540 return false;
2541 }
2542 s->iq_head++;
2543 if (s->iq_head == s->iq_size) {
2544 s->iq_head = 0;
2545 }
2546 return true;
2547 }
2548
2549 /* Try to fetch and process more Invalidation Descriptors */
2550 static void vtd_fetch_inv_desc(IntelIOMMUState *s)
2551 {
2552 int qi_shift;
2553
2554 /* Refer to 10.4.23 of VT-d spec 3.0 */
2555 qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4;
2556
2557 trace_vtd_inv_qi_fetch();
2558
2559 if (s->iq_tail >= s->iq_size) {
2560 /* Detects an invalid Tail pointer */
2561 error_report_once("%s: detected invalid QI tail "
2562 "(tail=0x%x, size=0x%x)",
2563 __func__, s->iq_tail, s->iq_size);
2564 vtd_handle_inv_queue_error(s);
2565 return;
2566 }
2567 while (s->iq_head != s->iq_tail) {
2568 if (!vtd_process_inv_desc(s)) {
2569 /* Invalidation Queue Errors */
2570 vtd_handle_inv_queue_error(s);
2571 break;
2572 }
2573 /* Must update the IQH_REG in time */
2574 vtd_set_quad_raw(s, DMAR_IQH_REG,
2575 (((uint64_t)(s->iq_head)) << qi_shift) &
2576 VTD_IQH_QH_MASK);
2577 }
2578 }
2579
2580 /* Handle write to Invalidation Queue Tail Register */
2581 static void vtd_handle_iqt_write(IntelIOMMUState *s)
2582 {
2583 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
2584
2585 if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) {
2586 error_report_once("%s: RSV bit is set: val=0x%"PRIx64,
2587 __func__, val);
2588 return;
2589 }
2590 s->iq_tail = VTD_IQT_QT(s->iq_dw, val);
2591 trace_vtd_inv_qi_tail(s->iq_tail);
2592
2593 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
2594 /* Process Invalidation Queue here */
2595 vtd_fetch_inv_desc(s);
2596 }
2597 }
2598
2599 static void vtd_handle_fsts_write(IntelIOMMUState *s)
2600 {
2601 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
2602 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
2603 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
2604
2605 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
2606 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
2607 trace_vtd_fsts_clear_ip();
2608 }
2609 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2610 * Descriptors if there are any when Queued Invalidation is enabled?
2611 */
2612 }
2613
2614 static void vtd_handle_fectl_write(IntelIOMMUState *s)
2615 {
2616 uint32_t fectl_reg;
2617 /* FIXME: when software clears the IM field, check the IP field. But do we
2618 * need to compare the old value and the new value to conclude that
2619 * software clears the IM field? Or just check if the IM field is zero?
2620 */
2621 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
2622
2623 trace_vtd_reg_write_fectl(fectl_reg);
2624
2625 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
2626 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
2627 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
2628 }
2629 }
2630
2631 static void vtd_handle_ics_write(IntelIOMMUState *s)
2632 {
2633 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
2634 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
2635
2636 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
2637 trace_vtd_reg_ics_clear_ip();
2638 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
2639 }
2640 }
2641
2642 static void vtd_handle_iectl_write(IntelIOMMUState *s)
2643 {
2644 uint32_t iectl_reg;
2645 /* FIXME: when software clears the IM field, check the IP field. But do we
2646 * need to compare the old value and the new value to conclude that
2647 * software clears the IM field? Or just check if the IM field is zero?
2648 */
2649 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
2650
2651 trace_vtd_reg_write_iectl(iectl_reg);
2652
2653 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
2654 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
2655 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
2656 }
2657 }
2658
2659 static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
2660 {
2661 IntelIOMMUState *s = opaque;
2662 uint64_t val;
2663
2664 trace_vtd_reg_read(addr, size);
2665
2666 if (addr + size > DMAR_REG_SIZE) {
2667 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2668 " size=0x%u", __func__, addr, size);
2669 return (uint64_t)-1;
2670 }
2671
2672 switch (addr) {
2673 /* Root Table Address Register, 64-bit */
2674 case DMAR_RTADDR_REG:
2675 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
2676 if (size == 4) {
2677 val = val & ((1ULL << 32) - 1);
2678 }
2679 break;
2680
2681 case DMAR_RTADDR_REG_HI:
2682 assert(size == 4);
2683 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;
2684 break;
2685
2686 /* Invalidation Queue Address Register, 64-bit */
2687 case DMAR_IQA_REG:
2688 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
2689 if (size == 4) {
2690 val = val & ((1ULL << 32) - 1);
2691 }
2692 break;
2693
2694 case DMAR_IQA_REG_HI:
2695 assert(size == 4);
2696 val = s->iq >> 32;
2697 break;
2698
2699 default:
2700 if (size == 4) {
2701 val = vtd_get_long(s, addr);
2702 } else {
2703 val = vtd_get_quad(s, addr);
2704 }
2705 }
2706
2707 return val;
2708 }
2709
2710 static void vtd_mem_write(void *opaque, hwaddr addr,
2711 uint64_t val, unsigned size)
2712 {
2713 IntelIOMMUState *s = opaque;
2714
2715 trace_vtd_reg_write(addr, size, val);
2716
2717 if (addr + size > DMAR_REG_SIZE) {
2718 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2719 " size=0x%u", __func__, addr, size);
2720 return;
2721 }
2722
2723 switch (addr) {
2724 /* Global Command Register, 32-bit */
2725 case DMAR_GCMD_REG:
2726 vtd_set_long(s, addr, val);
2727 vtd_handle_gcmd_write(s);
2728 break;
2729
2730 /* Context Command Register, 64-bit */
2731 case DMAR_CCMD_REG:
2732 if (size == 4) {
2733 vtd_set_long(s, addr, val);
2734 } else {
2735 vtd_set_quad(s, addr, val);
2736 vtd_handle_ccmd_write(s);
2737 }
2738 break;
2739
2740 case DMAR_CCMD_REG_HI:
2741 assert(size == 4);
2742 vtd_set_long(s, addr, val);
2743 vtd_handle_ccmd_write(s);
2744 break;
2745
2746 /* IOTLB Invalidation Register, 64-bit */
2747 case DMAR_IOTLB_REG:
2748 if (size == 4) {
2749 vtd_set_long(s, addr, val);
2750 } else {
2751 vtd_set_quad(s, addr, val);
2752 vtd_handle_iotlb_write(s);
2753 }
2754 break;
2755
2756 case DMAR_IOTLB_REG_HI:
2757 assert(size == 4);
2758 vtd_set_long(s, addr, val);
2759 vtd_handle_iotlb_write(s);
2760 break;
2761
2762 /* Invalidate Address Register, 64-bit */
2763 case DMAR_IVA_REG:
2764 if (size == 4) {
2765 vtd_set_long(s, addr, val);
2766 } else {
2767 vtd_set_quad(s, addr, val);
2768 }
2769 break;
2770
2771 case DMAR_IVA_REG_HI:
2772 assert(size == 4);
2773 vtd_set_long(s, addr, val);
2774 break;
2775
2776 /* Fault Status Register, 32-bit */
2777 case DMAR_FSTS_REG:
2778 assert(size == 4);
2779 vtd_set_long(s, addr, val);
2780 vtd_handle_fsts_write(s);
2781 break;
2782
2783 /* Fault Event Control Register, 32-bit */
2784 case DMAR_FECTL_REG:
2785 assert(size == 4);
2786 vtd_set_long(s, addr, val);
2787 vtd_handle_fectl_write(s);
2788 break;
2789
2790 /* Fault Event Data Register, 32-bit */
2791 case DMAR_FEDATA_REG:
2792 assert(size == 4);
2793 vtd_set_long(s, addr, val);
2794 break;
2795
2796 /* Fault Event Address Register, 32-bit */
2797 case DMAR_FEADDR_REG:
2798 if (size == 4) {
2799 vtd_set_long(s, addr, val);
2800 } else {
2801 /*
2802 * While the register is 32-bit only, some guests (Xen...) write to
2803 * it with 64-bit.
2804 */
2805 vtd_set_quad(s, addr, val);
2806 }
2807 break;
2808
2809 /* Fault Event Upper Address Register, 32-bit */
2810 case DMAR_FEUADDR_REG:
2811 assert(size == 4);
2812 vtd_set_long(s, addr, val);
2813 break;
2814
2815 /* Protected Memory Enable Register, 32-bit */
2816 case DMAR_PMEN_REG:
2817 assert(size == 4);
2818 vtd_set_long(s, addr, val);
2819 break;
2820
2821 /* Root Table Address Register, 64-bit */
2822 case DMAR_RTADDR_REG:
2823 if (size == 4) {
2824 vtd_set_long(s, addr, val);
2825 } else {
2826 vtd_set_quad(s, addr, val);
2827 }
2828 break;
2829
2830 case DMAR_RTADDR_REG_HI:
2831 assert(size == 4);
2832 vtd_set_long(s, addr, val);
2833 break;
2834
2835 /* Invalidation Queue Tail Register, 64-bit */
2836 case DMAR_IQT_REG:
2837 if (size == 4) {
2838 vtd_set_long(s, addr, val);
2839 } else {
2840 vtd_set_quad(s, addr, val);
2841 }
2842 vtd_handle_iqt_write(s);
2843 break;
2844
2845 case DMAR_IQT_REG_HI:
2846 assert(size == 4);
2847 vtd_set_long(s, addr, val);
2848 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2849 break;
2850
2851 /* Invalidation Queue Address Register, 64-bit */
2852 case DMAR_IQA_REG:
2853 if (size == 4) {
2854 vtd_set_long(s, addr, val);
2855 } else {
2856 vtd_set_quad(s, addr, val);
2857 }
2858 if (s->ecap & VTD_ECAP_SMTS &&
2859 val & VTD_IQA_DW_MASK) {
2860 s->iq_dw = true;
2861 } else {
2862 s->iq_dw = false;
2863 }
2864 break;
2865
2866 case DMAR_IQA_REG_HI:
2867 assert(size == 4);
2868 vtd_set_long(s, addr, val);
2869 break;
2870
2871 /* Invalidation Completion Status Register, 32-bit */
2872 case DMAR_ICS_REG:
2873 assert(size == 4);
2874 vtd_set_long(s, addr, val);
2875 vtd_handle_ics_write(s);
2876 break;
2877
2878 /* Invalidation Event Control Register, 32-bit */
2879 case DMAR_IECTL_REG:
2880 assert(size == 4);
2881 vtd_set_long(s, addr, val);
2882 vtd_handle_iectl_write(s);
2883 break;
2884
2885 /* Invalidation Event Data Register, 32-bit */
2886 case DMAR_IEDATA_REG:
2887 assert(size == 4);
2888 vtd_set_long(s, addr, val);
2889 break;
2890
2891 /* Invalidation Event Address Register, 32-bit */
2892 case DMAR_IEADDR_REG:
2893 assert(size == 4);
2894 vtd_set_long(s, addr, val);
2895 break;
2896
2897 /* Invalidation Event Upper Address Register, 32-bit */
2898 case DMAR_IEUADDR_REG:
2899 assert(size == 4);
2900 vtd_set_long(s, addr, val);
2901 break;
2902
2903 /* Fault Recording Registers, 128-bit */
2904 case DMAR_FRCD_REG_0_0:
2905 if (size == 4) {
2906 vtd_set_long(s, addr, val);
2907 } else {
2908 vtd_set_quad(s, addr, val);
2909 }
2910 break;
2911
2912 case DMAR_FRCD_REG_0_1:
2913 assert(size == 4);
2914 vtd_set_long(s, addr, val);
2915 break;
2916
2917 case DMAR_FRCD_REG_0_2:
2918 if (size == 4) {
2919 vtd_set_long(s, addr, val);
2920 } else {
2921 vtd_set_quad(s, addr, val);
2922 /* May clear bit 127 (Fault), update PPF */
2923 vtd_update_fsts_ppf(s);
2924 }
2925 break;
2926
2927 case DMAR_FRCD_REG_0_3:
2928 assert(size == 4);
2929 vtd_set_long(s, addr, val);
2930 /* May clear bit 127 (Fault), update PPF */
2931 vtd_update_fsts_ppf(s);
2932 break;
2933
2934 case DMAR_IRTA_REG:
2935 if (size == 4) {
2936 vtd_set_long(s, addr, val);
2937 } else {
2938 vtd_set_quad(s, addr, val);
2939 }
2940 break;
2941
2942 case DMAR_IRTA_REG_HI:
2943 assert(size == 4);
2944 vtd_set_long(s, addr, val);
2945 break;
2946
2947 default:
2948 if (size == 4) {
2949 vtd_set_long(s, addr, val);
2950 } else {
2951 vtd_set_quad(s, addr, val);
2952 }
2953 }
2954 }
2955
2956 static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
2957 IOMMUAccessFlags flag, int iommu_idx)
2958 {
2959 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2960 IntelIOMMUState *s = vtd_as->iommu_state;
2961 IOMMUTLBEntry iotlb = {
2962 /* We'll fill in the rest later. */
2963 .target_as = &address_space_memory,
2964 };
2965 bool success;
2966
2967 if (likely(s->dmar_enabled)) {
2968 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
2969 addr, flag & IOMMU_WO, &iotlb);
2970 } else {
2971 /* DMAR disabled, passthrough, use 4k-page*/
2972 iotlb.iova = addr & VTD_PAGE_MASK_4K;
2973 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
2974 iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
2975 iotlb.perm = IOMMU_RW;
2976 success = true;
2977 }
2978
2979 if (likely(success)) {
2980 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
2981 VTD_PCI_SLOT(vtd_as->devfn),
2982 VTD_PCI_FUNC(vtd_as->devfn),
2983 iotlb.iova, iotlb.translated_addr,
2984 iotlb.addr_mask);
2985 } else {
2986 error_report_once("%s: detected translation failure "
2987 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")",
2988 __func__, pci_bus_num(vtd_as->bus),
2989 VTD_PCI_SLOT(vtd_as->devfn),
2990 VTD_PCI_FUNC(vtd_as->devfn),
2991 addr);
2992 }
2993
2994 return iotlb;
2995 }
2996
2997 static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
2998 IOMMUNotifierFlag old,
2999 IOMMUNotifierFlag new,
3000 Error **errp)
3001 {
3002 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
3003 IntelIOMMUState *s = vtd_as->iommu_state;
3004
3005 /* Update per-address-space notifier flags */
3006 vtd_as->notifier_flags = new;
3007
3008 if (old == IOMMU_NOTIFIER_NONE) {
3009 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next);
3010 } else if (new == IOMMU_NOTIFIER_NONE) {
3011 QLIST_REMOVE(vtd_as, next);
3012 }
3013 return 0;
3014 }
3015
3016 static int vtd_post_load(void *opaque, int version_id)
3017 {
3018 IntelIOMMUState *iommu = opaque;
3019
3020 /*
3021 * Memory regions are dynamically turned on/off depending on
3022 * context entry configurations from the guest. After migration,
3023 * we need to make sure the memory regions are still correct.
3024 */
3025 vtd_switch_address_space_all(iommu);
3026
3027 /*
3028 * We don't need to migrate the root_scalable because we can
3029 * simply do the calculation after the loading is complete. We
3030 * can actually do similar things with root, dmar_enabled, etc.
3031 * however since we've had them already so we'd better keep them
3032 * for compatibility of migration.
3033 */
3034 vtd_update_scalable_state(iommu);
3035
3036 return 0;
3037 }
3038
3039 static const VMStateDescription vtd_vmstate = {
3040 .name = "iommu-intel",
3041 .version_id = 1,
3042 .minimum_version_id = 1,
3043 .priority = MIG_PRI_IOMMU,
3044 .post_load = vtd_post_load,
3045 .fields = (VMStateField[]) {
3046 VMSTATE_UINT64(root, IntelIOMMUState),
3047 VMSTATE_UINT64(intr_root, IntelIOMMUState),
3048 VMSTATE_UINT64(iq, IntelIOMMUState),
3049 VMSTATE_UINT32(intr_size, IntelIOMMUState),
3050 VMSTATE_UINT16(iq_head, IntelIOMMUState),
3051 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
3052 VMSTATE_UINT16(iq_size, IntelIOMMUState),
3053 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
3054 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
3055 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
3056 VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d */
3057 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
3058 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
3059 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
3060 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
3061 VMSTATE_END_OF_LIST()
3062 }
3063 };
3064
3065 static const MemoryRegionOps vtd_mem_ops = {
3066 .read = vtd_mem_read,
3067 .write = vtd_mem_write,
3068 .endianness = DEVICE_LITTLE_ENDIAN,
3069 .impl = {
3070 .min_access_size = 4,
3071 .max_access_size = 8,
3072 },
3073 .valid = {
3074 .min_access_size = 4,
3075 .max_access_size = 8,
3076 },
3077 };
3078
3079 static Property vtd_properties[] = {
3080 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
3081 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
3082 ON_OFF_AUTO_AUTO),
3083 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
3084 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
3085 VTD_HOST_ADDRESS_WIDTH),
3086 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
3087 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
3088 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
3089 DEFINE_PROP_END_OF_LIST(),
3090 };
3091
3092 /* Read IRTE entry with specific index */
3093 static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
3094 VTD_IR_TableEntry *entry, uint16_t sid)
3095 {
3096 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
3097 {0xffff, 0xfffb, 0xfff9, 0xfff8};
3098 dma_addr_t addr = 0x00;
3099 uint16_t mask, source_id;
3100 uint8_t bus, bus_max, bus_min;
3101
3102 if (index >= iommu->intr_size) {
3103 error_report_once("%s: index too large: ind=0x%x",
3104 __func__, index);
3105 return -VTD_FR_IR_INDEX_OVER;
3106 }
3107
3108 addr = iommu->intr_root + index * sizeof(*entry);
3109 if (dma_memory_read(&address_space_memory, addr, entry,
3110 sizeof(*entry))) {
3111 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64,
3112 __func__, index, addr);
3113 return -VTD_FR_IR_ROOT_INVAL;
3114 }
3115
3116 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]),
3117 le64_to_cpu(entry->data[0]));
3118
3119 if (!entry->irte.present) {
3120 error_report_once("%s: detected non-present IRTE "
3121 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
3122 __func__, index, le64_to_cpu(entry->data[1]),
3123 le64_to_cpu(entry->data[0]));
3124 return -VTD_FR_IR_ENTRY_P;
3125 }
3126
3127 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
3128 entry->irte.__reserved_2) {
3129 error_report_once("%s: detected non-zero reserved IRTE "
3130 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
3131 __func__, index, le64_to_cpu(entry->data[1]),
3132 le64_to_cpu(entry->data[0]));
3133 return -VTD_FR_IR_IRTE_RSVD;
3134 }
3135
3136 if (sid != X86_IOMMU_SID_INVALID) {
3137 /* Validate IRTE SID */
3138 source_id = le32_to_cpu(entry->irte.source_id);
3139 switch (entry->irte.sid_vtype) {
3140 case VTD_SVT_NONE:
3141 break;
3142
3143 case VTD_SVT_ALL:
3144 mask = vtd_svt_mask[entry->irte.sid_q];
3145 if ((source_id & mask) != (sid & mask)) {
3146 error_report_once("%s: invalid IRTE SID "
3147 "(index=%u, sid=%u, source_id=%u)",
3148 __func__, index, sid, source_id);
3149 return -VTD_FR_IR_SID_ERR;
3150 }
3151 break;
3152
3153 case VTD_SVT_BUS:
3154 bus_max = source_id >> 8;
3155 bus_min = source_id & 0xff;
3156 bus = sid >> 8;
3157 if (bus > bus_max || bus < bus_min) {
3158 error_report_once("%s: invalid SVT_BUS "
3159 "(index=%u, bus=%u, min=%u, max=%u)",
3160 __func__, index, bus, bus_min, bus_max);
3161 return -VTD_FR_IR_SID_ERR;
3162 }
3163 break;
3164
3165 default:
3166 error_report_once("%s: detected invalid IRTE SVT "
3167 "(index=%u, type=%d)", __func__,
3168 index, entry->irte.sid_vtype);
3169 /* Take this as verification failure. */
3170 return -VTD_FR_IR_SID_ERR;
3171 break;
3172 }
3173 }
3174
3175 return 0;
3176 }
3177
3178 /* Fetch IRQ information of specific IR index */
3179 static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
3180 X86IOMMUIrq *irq, uint16_t sid)
3181 {
3182 VTD_IR_TableEntry irte = {};
3183 int ret = 0;
3184
3185 ret = vtd_irte_get(iommu, index, &irte, sid);
3186 if (ret) {
3187 return ret;
3188 }
3189
3190 irq->trigger_mode = irte.irte.trigger_mode;
3191 irq->vector = irte.irte.vector;
3192 irq->delivery_mode = irte.irte.delivery_mode;
3193 irq->dest = le32_to_cpu(irte.irte.dest_id);
3194 if (!iommu->intr_eime) {
3195 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
3196 #define VTD_IR_APIC_DEST_SHIFT (8)
3197 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
3198 VTD_IR_APIC_DEST_SHIFT;
3199 }
3200 irq->dest_mode = irte.irte.dest_mode;
3201 irq->redir_hint = irte.irte.redir_hint;
3202
3203 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
3204 irq->delivery_mode, irq->dest, irq->dest_mode);
3205
3206 return 0;
3207 }
3208
3209 /* Interrupt remapping for MSI/MSI-X entry */
3210 static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
3211 MSIMessage *origin,
3212 MSIMessage *translated,
3213 uint16_t sid)
3214 {
3215 int ret = 0;
3216 VTD_IR_MSIAddress addr;
3217 uint16_t index;
3218 X86IOMMUIrq irq = {};
3219
3220 assert(origin && translated);
3221
3222 trace_vtd_ir_remap_msi_req(origin->address, origin->data);
3223
3224 if (!iommu || !iommu->intr_enabled) {
3225 memcpy(translated, origin, sizeof(*origin));
3226 goto out;
3227 }
3228
3229 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
3230 error_report_once("%s: MSI address high 32 bits non-zero detected: "
3231 "address=0x%" PRIx64, __func__, origin->address);
3232 return -VTD_FR_IR_REQ_RSVD;
3233 }
3234
3235 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
3236 if (addr.addr.__head != 0xfee) {
3237 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32,
3238 __func__, addr.data);
3239 return -VTD_FR_IR_REQ_RSVD;
3240 }
3241
3242 /* This is compatible mode. */
3243 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
3244 memcpy(translated, origin, sizeof(*origin));
3245 goto out;
3246 }
3247
3248 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
3249
3250 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
3251 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
3252
3253 if (addr.addr.sub_valid) {
3254 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
3255 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
3256 }
3257
3258 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
3259 if (ret) {
3260 return ret;
3261 }
3262
3263 if (addr.addr.sub_valid) {
3264 trace_vtd_ir_remap_type("MSI");
3265 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
3266 error_report_once("%s: invalid IR MSI "
3267 "(sid=%u, address=0x%" PRIx64
3268 ", data=0x%" PRIx32 ")",
3269 __func__, sid, origin->address, origin->data);
3270 return -VTD_FR_IR_REQ_RSVD;
3271 }
3272 } else {
3273 uint8_t vector = origin->data & 0xff;
3274 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
3275
3276 trace_vtd_ir_remap_type("IOAPIC");
3277 /* IOAPIC entry vector should be aligned with IRTE vector
3278 * (see vt-d spec 5.1.5.1). */
3279 if (vector != irq.vector) {
3280 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector);
3281 }
3282
3283 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
3284 * (see vt-d spec 5.1.5.1). */
3285 if (trigger_mode != irq.trigger_mode) {
3286 trace_vtd_warn_ir_trigger(sid, index, trigger_mode,
3287 irq.trigger_mode);
3288 }
3289 }
3290
3291 /*
3292 * We'd better keep the last two bits, assuming that guest OS
3293 * might modify it. Keep it does not hurt after all.
3294 */
3295 irq.msi_addr_last_bits = addr.addr.__not_care;
3296
3297 /* Translate X86IOMMUIrq to MSI message */
3298 x86_iommu_irq_to_msi_message(&irq, translated);
3299
3300 out:
3301 trace_vtd_ir_remap_msi(origin->address, origin->data,
3302 translated->address, translated->data);
3303 return 0;
3304 }
3305
3306 static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
3307 MSIMessage *dst, uint16_t sid)
3308 {
3309 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
3310 src, dst, sid);
3311 }
3312
3313 static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
3314 uint64_t *data, unsigned size,
3315 MemTxAttrs attrs)
3316 {
3317 return MEMTX_OK;
3318 }
3319
3320 static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
3321 uint64_t value, unsigned size,
3322 MemTxAttrs attrs)
3323 {
3324 int ret = 0;
3325 MSIMessage from = {}, to = {};
3326 uint16_t sid = X86_IOMMU_SID_INVALID;
3327
3328 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
3329 from.data = (uint32_t) value;
3330
3331 if (!attrs.unspecified) {
3332 /* We have explicit Source ID */
3333 sid = attrs.requester_id;
3334 }
3335
3336 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
3337 if (ret) {
3338 /* TODO: report error */
3339 /* Drop this interrupt */
3340 return MEMTX_ERROR;
3341 }
3342
3343 apic_get_class()->send_msi(&to);
3344
3345 return MEMTX_OK;
3346 }
3347
3348 static const MemoryRegionOps vtd_mem_ir_ops = {
3349 .read_with_attrs = vtd_mem_ir_read,
3350 .write_with_attrs = vtd_mem_ir_write,
3351 .endianness = DEVICE_LITTLE_ENDIAN,
3352 .impl = {
3353 .min_access_size = 4,