vga: add default display to machine class
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
29 #include "hw/ide.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/block-backend.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
61 #include "hw/mem/pc-dimm.h"
62 #include "trace.h"
63 #include "qapi/visitor.h"
64
65 /* debug PC/ISA interrupts */
66 //#define DEBUG_IRQ
67
68 #ifdef DEBUG_IRQ
69 #define DPRINTF(fmt, ...) \
70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
71 #else
72 #define DPRINTF(fmt, ...)
73 #endif
74
75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables
76 * (128K) and other BIOS datastructures (less than 4K reported to be used at
77 * the moment, 32K should be enough for a while). */
78 static unsigned acpi_data_size = 0x20000 + 0x8000;
79 void pc_set_legacy_acpi_data_size(void)
80 {
81 acpi_data_size = 0x10000;
82 }
83
84 #define BIOS_CFG_IOPORT 0x510
85 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
86 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
87 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
88 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
89 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
90
91 #define E820_NR_ENTRIES 16
92
93 struct e820_entry {
94 uint64_t address;
95 uint64_t length;
96 uint32_t type;
97 } QEMU_PACKED __attribute((__aligned__(4)));
98
99 struct e820_table {
100 uint32_t count;
101 struct e820_entry entry[E820_NR_ENTRIES];
102 } QEMU_PACKED __attribute((__aligned__(4)));
103
104 static struct e820_table e820_reserve;
105 static struct e820_entry *e820_table;
106 static unsigned e820_entries;
107 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
108
109 void gsi_handler(void *opaque, int n, int level)
110 {
111 GSIState *s = opaque;
112
113 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
114 if (n < ISA_NUM_IRQS) {
115 qemu_set_irq(s->i8259_irq[n], level);
116 }
117 qemu_set_irq(s->ioapic_irq[n], level);
118 }
119
120 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
121 unsigned size)
122 {
123 }
124
125 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
126 {
127 return 0xffffffffffffffffULL;
128 }
129
130 /* MSDOS compatibility mode FPU exception support */
131 static qemu_irq ferr_irq;
132
133 void pc_register_ferr_irq(qemu_irq irq)
134 {
135 ferr_irq = irq;
136 }
137
138 /* XXX: add IGNNE support */
139 void cpu_set_ferr(CPUX86State *s)
140 {
141 qemu_irq_raise(ferr_irq);
142 }
143
144 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
145 unsigned size)
146 {
147 qemu_irq_lower(ferr_irq);
148 }
149
150 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
151 {
152 return 0xffffffffffffffffULL;
153 }
154
155 /* TSC handling */
156 uint64_t cpu_get_tsc(CPUX86State *env)
157 {
158 return cpu_get_ticks();
159 }
160
161 /* SMM support */
162
163 static cpu_set_smm_t smm_set;
164 static void *smm_arg;
165
166 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
167 {
168 assert(smm_set == NULL);
169 assert(smm_arg == NULL);
170 smm_set = callback;
171 smm_arg = arg;
172 }
173
174 void cpu_smm_update(CPUX86State *env)
175 {
176 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
177 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
178 }
179 }
180
181
182 /* IRQ handling */
183 int cpu_get_pic_interrupt(CPUX86State *env)
184 {
185 X86CPU *cpu = x86_env_get_cpu(env);
186 int intno;
187
188 intno = apic_get_interrupt(cpu->apic_state);
189 if (intno >= 0) {
190 return intno;
191 }
192 /* read the irq from the PIC */
193 if (!apic_accept_pic_intr(cpu->apic_state)) {
194 return -1;
195 }
196
197 intno = pic_read_irq(isa_pic);
198 return intno;
199 }
200
201 static void pic_irq_request(void *opaque, int irq, int level)
202 {
203 CPUState *cs = first_cpu;
204 X86CPU *cpu = X86_CPU(cs);
205
206 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
207 if (cpu->apic_state) {
208 CPU_FOREACH(cs) {
209 cpu = X86_CPU(cs);
210 if (apic_accept_pic_intr(cpu->apic_state)) {
211 apic_deliver_pic_intr(cpu->apic_state, level);
212 }
213 }
214 } else {
215 if (level) {
216 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
217 } else {
218 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
219 }
220 }
221 }
222
223 /* PC cmos mappings */
224
225 #define REG_EQUIPMENT_BYTE 0x14
226
227 static int cmos_get_fd_drive_type(FDriveType fd0)
228 {
229 int val;
230
231 switch (fd0) {
232 case FDRIVE_DRV_144:
233 /* 1.44 Mb 3"5 drive */
234 val = 4;
235 break;
236 case FDRIVE_DRV_288:
237 /* 2.88 Mb 3"5 drive */
238 val = 5;
239 break;
240 case FDRIVE_DRV_120:
241 /* 1.2 Mb 5"5 drive */
242 val = 2;
243 break;
244 case FDRIVE_DRV_NONE:
245 default:
246 val = 0;
247 break;
248 }
249 return val;
250 }
251
252 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
253 int16_t cylinders, int8_t heads, int8_t sectors)
254 {
255 rtc_set_memory(s, type_ofs, 47);
256 rtc_set_memory(s, info_ofs, cylinders);
257 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
258 rtc_set_memory(s, info_ofs + 2, heads);
259 rtc_set_memory(s, info_ofs + 3, 0xff);
260 rtc_set_memory(s, info_ofs + 4, 0xff);
261 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
262 rtc_set_memory(s, info_ofs + 6, cylinders);
263 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
264 rtc_set_memory(s, info_ofs + 8, sectors);
265 }
266
267 /* convert boot_device letter to something recognizable by the bios */
268 static int boot_device2nibble(char boot_device)
269 {
270 switch(boot_device) {
271 case 'a':
272 case 'b':
273 return 0x01; /* floppy boot */
274 case 'c':
275 return 0x02; /* hard drive boot */
276 case 'd':
277 return 0x03; /* CD-ROM boot */
278 case 'n':
279 return 0x04; /* Network boot */
280 }
281 return 0;
282 }
283
284 static int set_boot_dev(ISADevice *s, const char *boot_device)
285 {
286 #define PC_MAX_BOOT_DEVICES 3
287 int nbds, bds[3] = { 0, };
288 int i;
289
290 nbds = strlen(boot_device);
291 if (nbds > PC_MAX_BOOT_DEVICES) {
292 error_report("Too many boot devices for PC");
293 return(1);
294 }
295 for (i = 0; i < nbds; i++) {
296 bds[i] = boot_device2nibble(boot_device[i]);
297 if (bds[i] == 0) {
298 error_report("Invalid boot device for PC: '%c'",
299 boot_device[i]);
300 return(1);
301 }
302 }
303 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
304 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
305 return(0);
306 }
307
308 static int pc_boot_set(void *opaque, const char *boot_device)
309 {
310 return set_boot_dev(opaque, boot_device);
311 }
312
313 typedef struct pc_cmos_init_late_arg {
314 ISADevice *rtc_state;
315 BusState *idebus[2];
316 } pc_cmos_init_late_arg;
317
318 static void pc_cmos_init_late(void *opaque)
319 {
320 pc_cmos_init_late_arg *arg = opaque;
321 ISADevice *s = arg->rtc_state;
322 int16_t cylinders;
323 int8_t heads, sectors;
324 int val;
325 int i, trans;
326
327 val = 0;
328 if (ide_get_geometry(arg->idebus[0], 0,
329 &cylinders, &heads, &sectors) >= 0) {
330 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
331 val |= 0xf0;
332 }
333 if (ide_get_geometry(arg->idebus[0], 1,
334 &cylinders, &heads, &sectors) >= 0) {
335 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
336 val |= 0x0f;
337 }
338 rtc_set_memory(s, 0x12, val);
339
340 val = 0;
341 for (i = 0; i < 4; i++) {
342 /* NOTE: ide_get_geometry() returns the physical
343 geometry. It is always such that: 1 <= sects <= 63, 1
344 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
345 geometry can be different if a translation is done. */
346 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
347 &cylinders, &heads, &sectors) >= 0) {
348 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
349 assert((trans & ~3) == 0);
350 val |= trans << (i * 2);
351 }
352 }
353 rtc_set_memory(s, 0x39, val);
354
355 qemu_unregister_reset(pc_cmos_init_late, opaque);
356 }
357
358 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
359 const char *boot_device, MachineState *machine,
360 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
361 ISADevice *s)
362 {
363 int val, nb, i;
364 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
365 static pc_cmos_init_late_arg arg;
366 PCMachineState *pc_machine = PC_MACHINE(machine);
367
368 /* various important CMOS locations needed by PC/Bochs bios */
369
370 /* memory size */
371 /* base memory (first MiB) */
372 val = MIN(ram_size / 1024, 640);
373 rtc_set_memory(s, 0x15, val);
374 rtc_set_memory(s, 0x16, val >> 8);
375 /* extended memory (next 64MiB) */
376 if (ram_size > 1024 * 1024) {
377 val = (ram_size - 1024 * 1024) / 1024;
378 } else {
379 val = 0;
380 }
381 if (val > 65535)
382 val = 65535;
383 rtc_set_memory(s, 0x17, val);
384 rtc_set_memory(s, 0x18, val >> 8);
385 rtc_set_memory(s, 0x30, val);
386 rtc_set_memory(s, 0x31, val >> 8);
387 /* memory between 16MiB and 4GiB */
388 if (ram_size > 16 * 1024 * 1024) {
389 val = (ram_size - 16 * 1024 * 1024) / 65536;
390 } else {
391 val = 0;
392 }
393 if (val > 65535)
394 val = 65535;
395 rtc_set_memory(s, 0x34, val);
396 rtc_set_memory(s, 0x35, val >> 8);
397 /* memory above 4GiB */
398 val = above_4g_mem_size / 65536;
399 rtc_set_memory(s, 0x5b, val);
400 rtc_set_memory(s, 0x5c, val >> 8);
401 rtc_set_memory(s, 0x5d, val >> 16);
402
403 /* set the number of CPU */
404 rtc_set_memory(s, 0x5f, smp_cpus - 1);
405
406 object_property_add_link(OBJECT(machine), "rtc_state",
407 TYPE_ISA_DEVICE,
408 (Object **)&pc_machine->rtc,
409 object_property_allow_set_link,
410 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
411 object_property_set_link(OBJECT(machine), OBJECT(s),
412 "rtc_state", &error_abort);
413
414 if (set_boot_dev(s, boot_device)) {
415 exit(1);
416 }
417
418 /* floppy type */
419 if (floppy) {
420 for (i = 0; i < 2; i++) {
421 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
422 }
423 }
424 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
425 cmos_get_fd_drive_type(fd_type[1]);
426 rtc_set_memory(s, 0x10, val);
427
428 val = 0;
429 nb = 0;
430 if (fd_type[0] < FDRIVE_DRV_NONE) {
431 nb++;
432 }
433 if (fd_type[1] < FDRIVE_DRV_NONE) {
434 nb++;
435 }
436 switch (nb) {
437 case 0:
438 break;
439 case 1:
440 val |= 0x01; /* 1 drive, ready for boot */
441 break;
442 case 2:
443 val |= 0x41; /* 2 drives, ready for boot */
444 break;
445 }
446 val |= 0x02; /* FPU is there */
447 val |= 0x04; /* PS/2 mouse installed */
448 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
449
450 /* hard drives */
451 arg.rtc_state = s;
452 arg.idebus[0] = idebus0;
453 arg.idebus[1] = idebus1;
454 qemu_register_reset(pc_cmos_init_late, &arg);
455 }
456
457 #define TYPE_PORT92 "port92"
458 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
459
460 /* port 92 stuff: could be split off */
461 typedef struct Port92State {
462 ISADevice parent_obj;
463
464 MemoryRegion io;
465 uint8_t outport;
466 qemu_irq *a20_out;
467 } Port92State;
468
469 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
470 unsigned size)
471 {
472 Port92State *s = opaque;
473 int oldval = s->outport;
474
475 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
476 s->outport = val;
477 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
478 if ((val & 1) && !(oldval & 1)) {
479 qemu_system_reset_request();
480 }
481 }
482
483 static uint64_t port92_read(void *opaque, hwaddr addr,
484 unsigned size)
485 {
486 Port92State *s = opaque;
487 uint32_t ret;
488
489 ret = s->outport;
490 DPRINTF("port92: read 0x%02x\n", ret);
491 return ret;
492 }
493
494 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
495 {
496 Port92State *s = PORT92(dev);
497
498 s->a20_out = a20_out;
499 }
500
501 static const VMStateDescription vmstate_port92_isa = {
502 .name = "port92",
503 .version_id = 1,
504 .minimum_version_id = 1,
505 .fields = (VMStateField[]) {
506 VMSTATE_UINT8(outport, Port92State),
507 VMSTATE_END_OF_LIST()
508 }
509 };
510
511 static void port92_reset(DeviceState *d)
512 {
513 Port92State *s = PORT92(d);
514
515 s->outport &= ~1;
516 }
517
518 static const MemoryRegionOps port92_ops = {
519 .read = port92_read,
520 .write = port92_write,
521 .impl = {
522 .min_access_size = 1,
523 .max_access_size = 1,
524 },
525 .endianness = DEVICE_LITTLE_ENDIAN,
526 };
527
528 static void port92_initfn(Object *obj)
529 {
530 Port92State *s = PORT92(obj);
531
532 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
533
534 s->outport = 0;
535 }
536
537 static void port92_realizefn(DeviceState *dev, Error **errp)
538 {
539 ISADevice *isadev = ISA_DEVICE(dev);
540 Port92State *s = PORT92(dev);
541
542 isa_register_ioport(isadev, &s->io, 0x92);
543 }
544
545 static void port92_class_initfn(ObjectClass *klass, void *data)
546 {
547 DeviceClass *dc = DEVICE_CLASS(klass);
548
549 dc->realize = port92_realizefn;
550 dc->reset = port92_reset;
551 dc->vmsd = &vmstate_port92_isa;
552 /*
553 * Reason: unlike ordinary ISA devices, this one needs additional
554 * wiring: its A20 output line needs to be wired up by
555 * port92_init().
556 */
557 dc->cannot_instantiate_with_device_add_yet = true;
558 }
559
560 static const TypeInfo port92_info = {
561 .name = TYPE_PORT92,
562 .parent = TYPE_ISA_DEVICE,
563 .instance_size = sizeof(Port92State),
564 .instance_init = port92_initfn,
565 .class_init = port92_class_initfn,
566 };
567
568 static void port92_register_types(void)
569 {
570 type_register_static(&port92_info);
571 }
572
573 type_init(port92_register_types)
574
575 static void handle_a20_line_change(void *opaque, int irq, int level)
576 {
577 X86CPU *cpu = opaque;
578
579 /* XXX: send to all CPUs ? */
580 /* XXX: add logic to handle multiple A20 line sources */
581 x86_cpu_set_a20(cpu, level);
582 }
583
584 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
585 {
586 int index = le32_to_cpu(e820_reserve.count);
587 struct e820_entry *entry;
588
589 if (type != E820_RAM) {
590 /* old FW_CFG_E820_TABLE entry -- reservations only */
591 if (index >= E820_NR_ENTRIES) {
592 return -EBUSY;
593 }
594 entry = &e820_reserve.entry[index++];
595
596 entry->address = cpu_to_le64(address);
597 entry->length = cpu_to_le64(length);
598 entry->type = cpu_to_le32(type);
599
600 e820_reserve.count = cpu_to_le32(index);
601 }
602
603 /* new "etc/e820" file -- include ram too */
604 e820_table = g_realloc(e820_table,
605 sizeof(struct e820_entry) * (e820_entries+1));
606 e820_table[e820_entries].address = cpu_to_le64(address);
607 e820_table[e820_entries].length = cpu_to_le64(length);
608 e820_table[e820_entries].type = cpu_to_le32(type);
609 e820_entries++;
610
611 return e820_entries;
612 }
613
614 int e820_get_num_entries(void)
615 {
616 return e820_entries;
617 }
618
619 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
620 {
621 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
622 *address = le64_to_cpu(e820_table[idx].address);
623 *length = le64_to_cpu(e820_table[idx].length);
624 return true;
625 }
626 return false;
627 }
628
629 /* Calculates the limit to CPU APIC ID values
630 *
631 * This function returns the limit for the APIC ID value, so that all
632 * CPU APIC IDs are < pc_apic_id_limit().
633 *
634 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
635 */
636 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
637 {
638 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
639 }
640
641 static FWCfgState *bochs_bios_init(void)
642 {
643 FWCfgState *fw_cfg;
644 uint8_t *smbios_tables, *smbios_anchor;
645 size_t smbios_tables_len, smbios_anchor_len;
646 uint64_t *numa_fw_cfg;
647 int i, j;
648 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
649
650 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
651 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
652 *
653 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
654 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
655 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
656 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
657 * may see".
658 *
659 * So, this means we must not use max_cpus, here, but the maximum possible
660 * APIC ID value, plus one.
661 *
662 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
663 * the APIC ID, not the "CPU index"
664 */
665 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
666 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
667 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
668 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
669 acpi_tables, acpi_tables_len);
670 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
671
672 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
673 if (smbios_tables) {
674 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
675 smbios_tables, smbios_tables_len);
676 }
677
678 smbios_get_tables(&smbios_tables, &smbios_tables_len,
679 &smbios_anchor, &smbios_anchor_len);
680 if (smbios_anchor) {
681 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
682 smbios_tables, smbios_tables_len);
683 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
684 smbios_anchor, smbios_anchor_len);
685 }
686
687 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
688 &e820_reserve, sizeof(e820_reserve));
689 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
690 sizeof(struct e820_entry) * e820_entries);
691
692 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
693 /* allocate memory for the NUMA channel: one (64bit) word for the number
694 * of nodes, one word for each VCPU->node and one word for each node to
695 * hold the amount of memory.
696 */
697 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
698 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
699 for (i = 0; i < max_cpus; i++) {
700 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
701 assert(apic_id < apic_id_limit);
702 for (j = 0; j < nb_numa_nodes; j++) {
703 if (test_bit(i, numa_info[j].node_cpu)) {
704 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
705 break;
706 }
707 }
708 }
709 for (i = 0; i < nb_numa_nodes; i++) {
710 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem);
711 }
712 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
713 (1 + apic_id_limit + nb_numa_nodes) *
714 sizeof(*numa_fw_cfg));
715
716 return fw_cfg;
717 }
718
719 static long get_file_size(FILE *f)
720 {
721 long where, size;
722
723 /* XXX: on Unix systems, using fstat() probably makes more sense */
724
725 where = ftell(f);
726 fseek(f, 0, SEEK_END);
727 size = ftell(f);
728 fseek(f, where, SEEK_SET);
729
730 return size;
731 }
732
733 static void load_linux(FWCfgState *fw_cfg,
734 const char *kernel_filename,
735 const char *initrd_filename,
736 const char *kernel_cmdline,
737 hwaddr max_ram_size)
738 {
739 uint16_t protocol;
740 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
741 uint32_t initrd_max;
742 uint8_t header[8192], *setup, *kernel, *initrd_data;
743 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
744 FILE *f;
745 char *vmode;
746
747 /* Align to 16 bytes as a paranoia measure */
748 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
749
750 /* load the kernel header */
751 f = fopen(kernel_filename, "rb");
752 if (!f || !(kernel_size = get_file_size(f)) ||
753 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
754 MIN(ARRAY_SIZE(header), kernel_size)) {
755 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
756 kernel_filename, strerror(errno));
757 exit(1);
758 }
759
760 /* kernel protocol version */
761 #if 0
762 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
763 #endif
764 if (ldl_p(header+0x202) == 0x53726448) {
765 protocol = lduw_p(header+0x206);
766 } else {
767 /* This looks like a multiboot kernel. If it is, let's stop
768 treating it like a Linux kernel. */
769 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
770 kernel_cmdline, kernel_size, header)) {
771 return;
772 }
773 protocol = 0;
774 }
775
776 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
777 /* Low kernel */
778 real_addr = 0x90000;
779 cmdline_addr = 0x9a000 - cmdline_size;
780 prot_addr = 0x10000;
781 } else if (protocol < 0x202) {
782 /* High but ancient kernel */
783 real_addr = 0x90000;
784 cmdline_addr = 0x9a000 - cmdline_size;
785 prot_addr = 0x100000;
786 } else {
787 /* High and recent kernel */
788 real_addr = 0x10000;
789 cmdline_addr = 0x20000;
790 prot_addr = 0x100000;
791 }
792
793 #if 0
794 fprintf(stderr,
795 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
796 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
797 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
798 real_addr,
799 cmdline_addr,
800 prot_addr);
801 #endif
802
803 /* highest address for loading the initrd */
804 if (protocol >= 0x203) {
805 initrd_max = ldl_p(header+0x22c);
806 } else {
807 initrd_max = 0x37ffffff;
808 }
809
810 if (initrd_max >= max_ram_size - acpi_data_size) {
811 initrd_max = max_ram_size - acpi_data_size - 1;
812 }
813
814 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
815 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
816 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
817
818 if (protocol >= 0x202) {
819 stl_p(header+0x228, cmdline_addr);
820 } else {
821 stw_p(header+0x20, 0xA33F);
822 stw_p(header+0x22, cmdline_addr-real_addr);
823 }
824
825 /* handle vga= parameter */
826 vmode = strstr(kernel_cmdline, "vga=");
827 if (vmode) {
828 unsigned int video_mode;
829 /* skip "vga=" */
830 vmode += 4;
831 if (!strncmp(vmode, "normal", 6)) {
832 video_mode = 0xffff;
833 } else if (!strncmp(vmode, "ext", 3)) {
834 video_mode = 0xfffe;
835 } else if (!strncmp(vmode, "ask", 3)) {
836 video_mode = 0xfffd;
837 } else {
838 video_mode = strtol(vmode, NULL, 0);
839 }
840 stw_p(header+0x1fa, video_mode);
841 }
842
843 /* loader type */
844 /* High nybble = B reserved for QEMU; low nybble is revision number.
845 If this code is substantially changed, you may want to consider
846 incrementing the revision. */
847 if (protocol >= 0x200) {
848 header[0x210] = 0xB0;
849 }
850 /* heap */
851 if (protocol >= 0x201) {
852 header[0x211] |= 0x80; /* CAN_USE_HEAP */
853 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
854 }
855
856 /* load initrd */
857 if (initrd_filename) {
858 if (protocol < 0x200) {
859 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
860 exit(1);
861 }
862
863 initrd_size = get_image_size(initrd_filename);
864 if (initrd_size < 0) {
865 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
866 initrd_filename, strerror(errno));
867 exit(1);
868 }
869
870 initrd_addr = (initrd_max-initrd_size) & ~4095;
871
872 initrd_data = g_malloc(initrd_size);
873 load_image(initrd_filename, initrd_data);
874
875 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
876 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
877 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
878
879 stl_p(header+0x218, initrd_addr);
880 stl_p(header+0x21c, initrd_size);
881 }
882
883 /* load kernel and setup */
884 setup_size = header[0x1f1];
885 if (setup_size == 0) {
886 setup_size = 4;
887 }
888 setup_size = (setup_size+1)*512;
889 kernel_size -= setup_size;
890
891 setup = g_malloc(setup_size);
892 kernel = g_malloc(kernel_size);
893 fseek(f, 0, SEEK_SET);
894 if (fread(setup, 1, setup_size, f) != setup_size) {
895 fprintf(stderr, "fread() failed\n");
896 exit(1);
897 }
898 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
899 fprintf(stderr, "fread() failed\n");
900 exit(1);
901 }
902 fclose(f);
903 memcpy(setup, header, MIN(sizeof(header), setup_size));
904
905 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
906 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
907 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
908
909 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
910 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
911 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
912
913 option_rom[nb_option_roms].name = "linuxboot.bin";
914 option_rom[nb_option_roms].bootindex = 0;
915 nb_option_roms++;
916 }
917
918 #define NE2000_NB_MAX 6
919
920 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
921 0x280, 0x380 };
922 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
923
924 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
925 {
926 static int nb_ne2k = 0;
927
928 if (nb_ne2k == NE2000_NB_MAX)
929 return;
930 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
931 ne2000_irq[nb_ne2k], nd);
932 nb_ne2k++;
933 }
934
935 DeviceState *cpu_get_current_apic(void)
936 {
937 if (current_cpu) {
938 X86CPU *cpu = X86_CPU(current_cpu);
939 return cpu->apic_state;
940 } else {
941 return NULL;
942 }
943 }
944
945 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
946 {
947 X86CPU *cpu = opaque;
948
949 if (level) {
950 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
951 }
952 }
953
954 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
955 DeviceState *icc_bridge, Error **errp)
956 {
957 X86CPU *cpu;
958 Error *local_err = NULL;
959
960 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
961 if (local_err != NULL) {
962 error_propagate(errp, local_err);
963 return NULL;
964 }
965
966 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
967 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
968
969 if (local_err) {
970 error_propagate(errp, local_err);
971 object_unref(OBJECT(cpu));
972 cpu = NULL;
973 }
974 return cpu;
975 }
976
977 static const char *current_cpu_model;
978
979 void pc_hot_add_cpu(const int64_t id, Error **errp)
980 {
981 DeviceState *icc_bridge;
982 int64_t apic_id = x86_cpu_apic_id_from_index(id);
983
984 if (id < 0) {
985 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
986 return;
987 }
988
989 if (cpu_exists(apic_id)) {
990 error_setg(errp, "Unable to add CPU: %" PRIi64
991 ", it already exists", id);
992 return;
993 }
994
995 if (id >= max_cpus) {
996 error_setg(errp, "Unable to add CPU: %" PRIi64
997 ", max allowed: %d", id, max_cpus - 1);
998 return;
999 }
1000
1001 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1002 error_setg(errp, "Unable to add CPU: %" PRIi64
1003 ", resulting APIC ID (%" PRIi64 ") is too large",
1004 id, apic_id);
1005 return;
1006 }
1007
1008 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
1009 TYPE_ICC_BRIDGE, NULL));
1010 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
1011 }
1012
1013 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1014 {
1015 int i;
1016 X86CPU *cpu = NULL;
1017 Error *error = NULL;
1018 unsigned long apic_id_limit;
1019
1020 /* init CPUs */
1021 if (cpu_model == NULL) {
1022 #ifdef TARGET_X86_64
1023 cpu_model = "qemu64";
1024 #else
1025 cpu_model = "qemu32";
1026 #endif
1027 }
1028 current_cpu_model = cpu_model;
1029
1030 apic_id_limit = pc_apic_id_limit(max_cpus);
1031 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1032 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1033 apic_id_limit - 1);
1034 exit(1);
1035 }
1036
1037 for (i = 0; i < smp_cpus; i++) {
1038 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1039 icc_bridge, &error);
1040 if (error) {
1041 error_report("%s", error_get_pretty(error));
1042 error_free(error);
1043 exit(1);
1044 }
1045 }
1046
1047 /* map APIC MMIO area if CPU has APIC */
1048 if (cpu && cpu->apic_state) {
1049 /* XXX: what if the base changes? */
1050 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1051 APIC_DEFAULT_ADDRESS, 0x1000);
1052 }
1053
1054 /* tell smbios about cpuid version and features */
1055 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1056 }
1057
1058 /* pci-info ROM file. Little endian format */
1059 typedef struct PcRomPciInfo {
1060 uint64_t w32_min;
1061 uint64_t w32_max;
1062 uint64_t w64_min;
1063 uint64_t w64_max;
1064 } PcRomPciInfo;
1065
1066 typedef struct PcGuestInfoState {
1067 PcGuestInfo info;
1068 Notifier machine_done;
1069 } PcGuestInfoState;
1070
1071 static
1072 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1073 {
1074 PcGuestInfoState *guest_info_state = container_of(notifier,
1075 PcGuestInfoState,
1076 machine_done);
1077 acpi_setup(&guest_info_state->info);
1078 }
1079
1080 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1081 ram_addr_t above_4g_mem_size)
1082 {
1083 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1084 PcGuestInfo *guest_info = &guest_info_state->info;
1085 int i, j;
1086
1087 guest_info->ram_size_below_4g = below_4g_mem_size;
1088 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1089 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1090 guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1091 guest_info->numa_nodes = nb_numa_nodes;
1092 guest_info->node_mem = g_malloc0(guest_info->numa_nodes *
1093 sizeof *guest_info->node_mem);
1094 for (i = 0; i < nb_numa_nodes; i++) {
1095 guest_info->node_mem[i] = numa_info[i].node_mem;
1096 }
1097
1098 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1099 sizeof *guest_info->node_cpu);
1100
1101 for (i = 0; i < max_cpus; i++) {
1102 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1103 assert(apic_id < guest_info->apic_id_limit);
1104 for (j = 0; j < nb_numa_nodes; j++) {
1105 if (test_bit(i, numa_info[j].node_cpu)) {
1106 guest_info->node_cpu[apic_id] = j;
1107 break;
1108 }
1109 }
1110 }
1111
1112 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1113 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1114 return guest_info;
1115 }
1116
1117 /* setup pci memory address space mapping into system address space */
1118 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1119 MemoryRegion *pci_address_space)
1120 {
1121 /* Set to lower priority than RAM */
1122 memory_region_add_subregion_overlap(system_memory, 0x0,
1123 pci_address_space, -1);
1124 }
1125
1126 void pc_acpi_init(const char *default_dsdt)
1127 {
1128 char *filename;
1129
1130 if (acpi_tables != NULL) {
1131 /* manually set via -acpitable, leave it alone */
1132 return;
1133 }
1134
1135 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1136 if (filename == NULL) {
1137 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1138 } else {
1139 char *arg;
1140 QemuOpts *opts;
1141 Error *err = NULL;
1142
1143 arg = g_strdup_printf("file=%s", filename);
1144
1145 /* creates a deep copy of "arg" */
1146 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1147 g_assert(opts != NULL);
1148
1149 acpi_table_add_builtin(opts, &err);
1150 if (err) {
1151 error_report("WARNING: failed to load %s: %s", filename,
1152 error_get_pretty(err));
1153 error_free(err);
1154 }
1155 g_free(arg);
1156 g_free(filename);
1157 }
1158 }
1159
1160 FWCfgState *xen_load_linux(const char *kernel_filename,
1161 const char *kernel_cmdline,
1162 const char *initrd_filename,
1163 ram_addr_t below_4g_mem_size,
1164 PcGuestInfo *guest_info)
1165 {
1166 int i;
1167 FWCfgState *fw_cfg;
1168
1169 assert(kernel_filename != NULL);
1170
1171 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
1172 rom_set_fw(fw_cfg);
1173
1174 load_linux(fw_cfg, kernel_filename, initrd_filename,
1175 kernel_cmdline, below_4g_mem_size);
1176 for (i = 0; i < nb_option_roms; i++) {
1177 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1178 !strcmp(option_rom[i].name, "multiboot.bin"));
1179 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1180 }
1181 guest_info->fw_cfg = fw_cfg;
1182 return fw_cfg;
1183 }
1184
1185 FWCfgState *pc_memory_init(MachineState *machine,
1186 MemoryRegion *system_memory,
1187 ram_addr_t below_4g_mem_size,
1188 ram_addr_t above_4g_mem_size,
1189 MemoryRegion *rom_memory,
1190 MemoryRegion **ram_memory,
1191 PcGuestInfo *guest_info)
1192 {
1193 int linux_boot, i;
1194 MemoryRegion *ram, *option_rom_mr;
1195 MemoryRegion *ram_below_4g, *ram_above_4g;
1196 FWCfgState *fw_cfg;
1197 PCMachineState *pcms = PC_MACHINE(machine);
1198
1199 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size);
1200
1201 linux_boot = (machine->kernel_filename != NULL);
1202
1203 /* Allocate RAM. We allocate it as a single memory region and use
1204 * aliases to address portions of it, mostly for backwards compatibility
1205 * with older qemus that used qemu_ram_alloc().
1206 */
1207 ram = g_malloc(sizeof(*ram));
1208 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1209 machine->ram_size);
1210 *ram_memory = ram;
1211 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1212 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1213 0, below_4g_mem_size);
1214 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1215 e820_add_entry(0, below_4g_mem_size, E820_RAM);
1216 if (above_4g_mem_size > 0) {
1217 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1218 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1219 below_4g_mem_size, above_4g_mem_size);
1220 memory_region_add_subregion(system_memory, 0x100000000ULL,
1221 ram_above_4g);
1222 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1223 }
1224
1225 if (!guest_info->has_reserved_memory &&
1226 (machine->ram_slots ||
1227 (machine->maxram_size > machine->ram_size))) {
1228 MachineClass *mc = MACHINE_GET_CLASS(machine);
1229
1230 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1231 mc->name);
1232 exit(EXIT_FAILURE);
1233 }
1234
1235 /* initialize hotplug memory address space */
1236 if (guest_info->has_reserved_memory &&
1237 (machine->ram_size < machine->maxram_size)) {
1238 ram_addr_t hotplug_mem_size =
1239 machine->maxram_size - machine->ram_size;
1240
1241 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1242 error_report("unsupported amount of memory slots: %"PRIu64,
1243 machine->ram_slots);
1244 exit(EXIT_FAILURE);
1245 }
1246
1247 pcms->hotplug_memory_base =
1248 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
1249
1250 if ((pcms->hotplug_memory_base + hotplug_mem_size) <
1251 hotplug_mem_size) {
1252 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1253 machine->maxram_size);
1254 exit(EXIT_FAILURE);
1255 }
1256
1257 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms),
1258 "hotplug-memory", hotplug_mem_size);
1259 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base,
1260 &pcms->hotplug_memory);
1261 }
1262
1263 /* Initialize PC system firmware */
1264 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1265
1266 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1267 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1268 &error_abort);
1269 vmstate_register_ram_global(option_rom_mr);
1270 memory_region_add_subregion_overlap(rom_memory,
1271 PC_ROM_MIN_VGA,
1272 option_rom_mr,
1273 1);
1274
1275 fw_cfg = bochs_bios_init();
1276 rom_set_fw(fw_cfg);
1277
1278 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) {
1279 uint64_t *val = g_malloc(sizeof(*val));
1280 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30));
1281 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1282 }
1283
1284 if (linux_boot) {
1285 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename,
1286 machine->kernel_cmdline, below_4g_mem_size);
1287 }
1288
1289 for (i = 0; i < nb_option_roms; i++) {
1290 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1291 }
1292 guest_info->fw_cfg = fw_cfg;
1293 return fw_cfg;
1294 }
1295
1296 qemu_irq *pc_allocate_cpu_irq(void)
1297 {
1298 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1299 }
1300
1301 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1302 {
1303 DeviceState *dev = NULL;
1304
1305 if (pci_bus) {
1306 PCIDevice *pcidev = pci_vga_init(pci_bus);
1307 dev = pcidev ? &pcidev->qdev : NULL;
1308 } else if (isa_bus) {
1309 ISADevice *isadev = isa_vga_init(isa_bus);
1310 dev = isadev ? DEVICE(isadev) : NULL;
1311 }
1312 return dev;
1313 }
1314
1315 static void cpu_request_exit(void *opaque, int irq, int level)
1316 {
1317 CPUState *cpu = current_cpu;
1318
1319 if (cpu && level) {
1320 cpu_exit(cpu);
1321 }
1322 }
1323
1324 static const MemoryRegionOps ioport80_io_ops = {
1325 .write = ioport80_write,
1326 .read = ioport80_read,
1327 .endianness = DEVICE_NATIVE_ENDIAN,
1328 .impl = {
1329 .min_access_size = 1,
1330 .max_access_size = 1,
1331 },
1332 };
1333
1334 static const MemoryRegionOps ioportF0_io_ops = {
1335 .write = ioportF0_write,
1336 .read = ioportF0_read,
1337 .endianness = DEVICE_NATIVE_ENDIAN,
1338 .impl = {
1339 .min_access_size = 1,
1340 .max_access_size = 1,
1341 },
1342 };
1343
1344 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1345 ISADevice **rtc_state,
1346 ISADevice **floppy,
1347 bool no_vmport,
1348 uint32 hpet_irqs)
1349 {
1350 int i;
1351 DriveInfo *fd[MAX_FD];
1352 DeviceState *hpet = NULL;
1353 int pit_isa_irq = 0;
1354 qemu_irq pit_alt_irq = NULL;
1355 qemu_irq rtc_irq = NULL;
1356 qemu_irq *a20_line;
1357 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1358 qemu_irq *cpu_exit_irq;
1359 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1360 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1361
1362 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1363 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1364
1365 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1366 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1367
1368 /*
1369 * Check if an HPET shall be created.
1370 *
1371 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1372 * when the HPET wants to take over. Thus we have to disable the latter.
1373 */
1374 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1375 /* In order to set property, here not using sysbus_try_create_simple */
1376 hpet = qdev_try_create(NULL, TYPE_HPET);
1377 if (hpet) {
1378 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1379 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1380 * IRQ8 and IRQ2.
1381 */
1382 uint8_t compat = object_property_get_int(OBJECT(hpet),
1383 HPET_INTCAP, NULL);
1384 if (!compat) {
1385 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1386 }
1387 qdev_init_nofail(hpet);
1388 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1389
1390 for (i = 0; i < GSI_NUM_PINS; i++) {
1391 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1392 }
1393 pit_isa_irq = -1;
1394 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1395 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1396 }
1397 }
1398 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1399
1400 qemu_register_boot_set(pc_boot_set, *rtc_state);
1401
1402 if (!xen_enabled()) {
1403 if (kvm_irqchip_in_kernel()) {
1404 pit = kvm_pit_init(isa_bus, 0x40);
1405 } else {
1406 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1407 }
1408 if (hpet) {
1409 /* connect PIT to output control line of the HPET */
1410 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1411 }
1412 pcspk_init(isa_bus, pit);
1413 }
1414
1415 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1416 if (serial_hds[i]) {
1417 serial_isa_init(isa_bus, i, serial_hds[i]);
1418 }
1419 }
1420
1421 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1422 if (parallel_hds[i]) {
1423 parallel_init(isa_bus, i, parallel_hds[i]);
1424 }
1425 }
1426
1427 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1428 i8042 = isa_create_simple(isa_bus, "i8042");
1429 i8042_setup_a20_line(i8042, &a20_line[0]);
1430 if (!no_vmport) {
1431 vmport_init(isa_bus);
1432 vmmouse = isa_try_create(isa_bus, "vmmouse");
1433 } else {
1434 vmmouse = NULL;
1435 }
1436 if (vmmouse) {
1437 DeviceState *dev = DEVICE(vmmouse);
1438 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1439 qdev_init_nofail(dev);
1440 }
1441 port92 = isa_create_simple(isa_bus, "port92");
1442 port92_init(port92, &a20_line[1]);
1443
1444 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1445 DMA_init(0, cpu_exit_irq);
1446
1447 for(i = 0; i < MAX_FD; i++) {
1448 fd[i] = drive_get(IF_FLOPPY, 0, i);
1449 }
1450 *floppy = fdctrl_init_isa(isa_bus, fd);
1451 }
1452
1453 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1454 {
1455 int i;
1456
1457 for (i = 0; i < nb_nics; i++) {
1458 NICInfo *nd = &nd_table[i];
1459
1460 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1461 pc_init_ne2k_isa(isa_bus, nd);
1462 } else {
1463 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1464 }
1465 }
1466 }
1467
1468 void pc_pci_device_init(PCIBus *pci_bus)
1469 {
1470 int max_bus;
1471 int bus;
1472
1473 max_bus = drive_get_max_bus(IF_SCSI);
1474 for (bus = 0; bus <= max_bus; bus++) {
1475 pci_create_simple(pci_bus, -1, "lsi53c895a");
1476 }
1477 }
1478
1479 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1480 {
1481 DeviceState *dev;
1482 SysBusDevice *d;
1483 unsigned int i;
1484
1485 if (kvm_irqchip_in_kernel()) {
1486 dev = qdev_create(NULL, "kvm-ioapic");
1487 } else {
1488 dev = qdev_create(NULL, "ioapic");
1489 }
1490 if (parent_name) {
1491 object_property_add_child(object_resolve_path(parent_name, NULL),
1492 "ioapic", OBJECT(dev), NULL);
1493 }
1494 qdev_init_nofail(dev);
1495 d = SYS_BUS_DEVICE(dev);
1496 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1497
1498 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1499 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1500 }
1501 }
1502
1503 static void pc_generic_machine_class_init(ObjectClass *oc, void *data)
1504 {
1505 MachineClass *mc = MACHINE_CLASS(oc);
1506 QEMUMachine *qm = data;
1507
1508 mc->family = qm->family;
1509 mc->name = qm->name;
1510 mc->alias = qm->alias;
1511 mc->desc = qm->desc;
1512 mc->init = qm->init;
1513 mc->reset = qm->reset;
1514 mc->hot_add_cpu = qm->hot_add_cpu;
1515 mc->kvm_type = qm->kvm_type;
1516 mc->block_default_type = qm->block_default_type;
1517 mc->units_per_default_bus = qm->units_per_default_bus;
1518 mc->max_cpus = qm->max_cpus;
1519 mc->no_serial = qm->no_serial;
1520 mc->no_parallel = qm->no_parallel;
1521 mc->use_virtcon = qm->use_virtcon;
1522 mc->use_sclp = qm->use_sclp;
1523 mc->no_floppy = qm->no_floppy;
1524 mc->no_cdrom = qm->no_cdrom;
1525 mc->no_sdcard = qm->no_sdcard;
1526 mc->is_default = qm->is_default;
1527 mc->default_machine_opts = qm->default_machine_opts;
1528 mc->default_boot_order = qm->default_boot_order;
1529 mc->default_display = qm->default_display;
1530 mc->compat_props = qm->compat_props;
1531 mc->hw_version = qm->hw_version;
1532 }
1533
1534 void qemu_register_pc_machine(QEMUMachine *m)
1535 {
1536 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL);
1537 TypeInfo ti = {
1538 .name = name,
1539 .parent = TYPE_PC_MACHINE,
1540 .class_init = pc_generic_machine_class_init,
1541 .class_data = (void *)m,
1542 };
1543
1544 type_register(&ti);
1545 g_free(name);
1546 }
1547
1548 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1549 DeviceState *dev, Error **errp)
1550 {
1551 int slot;
1552 HotplugHandlerClass *hhc;
1553 Error *local_err = NULL;
1554 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1555 MachineState *machine = MACHINE(hotplug_dev);
1556 PCDIMMDevice *dimm = PC_DIMM(dev);
1557 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1558 MemoryRegion *mr = ddc->get_memory_region(dimm);
1559 uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
1560 &local_err);
1561 if (local_err) {
1562 goto out;
1563 }
1564
1565 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base,
1566 memory_region_size(&pcms->hotplug_memory),
1567 !addr ? NULL : &addr,
1568 memory_region_size(mr), &local_err);
1569 if (local_err) {
1570 goto out;
1571 }
1572
1573 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err);
1574 if (local_err) {
1575 goto out;
1576 }
1577 trace_mhp_pc_dimm_assigned_address(addr);
1578
1579 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err);
1580 if (local_err) {
1581 goto out;
1582 }
1583
1584 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot,
1585 machine->ram_slots, &local_err);
1586 if (local_err) {
1587 goto out;
1588 }
1589 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err);
1590 if (local_err) {
1591 goto out;
1592 }
1593 trace_mhp_pc_dimm_assigned_slot(slot);
1594
1595 if (!pcms->acpi_dev) {
1596 error_setg(&local_err,
1597 "memory hotplug is not enabled: missing acpi device");
1598 goto out;
1599 }
1600
1601 memory_region_add_subregion(&pcms->hotplug_memory,
1602 addr - pcms->hotplug_memory_base, mr);
1603 vmstate_register_ram(mr, dev);
1604
1605 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1606 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1607 out:
1608 error_propagate(errp, local_err);
1609 }
1610
1611 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1612 DeviceState *dev, Error **errp)
1613 {
1614 HotplugHandlerClass *hhc;
1615 Error *local_err = NULL;
1616 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1617
1618 if (!dev->hotplugged) {
1619 goto out;
1620 }
1621
1622 if (!pcms->acpi_dev) {
1623 error_setg(&local_err,
1624 "cpu hotplug is not enabled: missing acpi device");
1625 goto out;
1626 }
1627
1628 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1629 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1630 if (local_err) {
1631 goto out;
1632 }
1633
1634 /* increment the number of CPUs */
1635 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1);
1636 out:
1637 error_propagate(errp, local_err);
1638 }
1639
1640 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1641 DeviceState *dev, Error **errp)
1642 {
1643 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1644 pc_dimm_plug(hotplug_dev, dev, errp);
1645 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1646 pc_cpu_plug(hotplug_dev, dev, errp);
1647 }
1648 }
1649
1650 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
1651 DeviceState *dev)
1652 {
1653 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1654
1655 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1656 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1657 return HOTPLUG_HANDLER(machine);
1658 }
1659
1660 return pcmc->get_hotplug_handler ?
1661 pcmc->get_hotplug_handler(machine, dev) : NULL;
1662 }
1663
1664 static void
1665 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque,
1666 const char *name, Error **errp)
1667 {
1668 PCMachineState *pcms = PC_MACHINE(obj);
1669 int64_t value = memory_region_size(&pcms->hotplug_memory);
1670
1671 visit_type_int(v, &value, name, errp);
1672 }
1673
1674 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1675 void *opaque, const char *name,
1676 Error **errp)
1677 {
1678 PCMachineState *pcms = PC_MACHINE(obj);
1679 uint64_t value = pcms->max_ram_below_4g;
1680
1681 visit_type_size(v, &value, name, errp);
1682 }
1683
1684 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1685 void *opaque, const char *name,
1686 Error **errp)
1687 {
1688 PCMachineState *pcms = PC_MACHINE(obj);
1689 Error *error = NULL;
1690 uint64_t value;
1691
1692 visit_type_size(v, &value, name, &error);
1693 if (error) {
1694 error_propagate(errp, error);
1695 return;
1696 }
1697 if (value > (1ULL << 32)) {
1698 error_set(&error, ERROR_CLASS_GENERIC_ERROR,
1699 "Machine option 'max-ram-below-4g=%"PRIu64
1700 "' expects size less than or equal to 4G", value);
1701 error_propagate(errp, error);
1702 return;
1703 }
1704
1705 if (value < (1ULL << 20)) {
1706 error_report("Warning: small max_ram_below_4g(%"PRIu64
1707 ") less than 1M. BIOS may not work..",
1708 value);
1709 }
1710
1711 pcms->max_ram_below_4g = value;
1712 }
1713
1714 static bool pc_machine_get_vmport(Object *obj, Error **errp)
1715 {
1716 PCMachineState *pcms = PC_MACHINE(obj);
1717
1718 return pcms->vmport;
1719 }
1720
1721 static void pc_machine_set_vmport(Object *obj, bool value, Error **errp)
1722 {
1723 PCMachineState *pcms = PC_MACHINE(obj);
1724
1725 pcms->vmport = value;
1726 }
1727
1728 static void pc_machine_initfn(Object *obj)
1729 {
1730 PCMachineState *pcms = PC_MACHINE(obj);
1731
1732 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int",
1733 pc_machine_get_hotplug_memory_region_size,
1734 NULL, NULL, NULL, NULL);
1735 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */
1736 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1737 pc_machine_get_max_ram_below_4g,
1738 pc_machine_set_max_ram_below_4g,
1739 NULL, NULL, NULL);
1740 pcms->vmport = !xen_enabled();
1741 object_property_add_bool(obj, PC_MACHINE_VMPORT,
1742 pc_machine_get_vmport,
1743 pc_machine_set_vmport,
1744 NULL);
1745 }
1746
1747 static void pc_machine_class_init(ObjectClass *oc, void *data)
1748 {
1749 MachineClass *mc = MACHINE_CLASS(oc);
1750 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1751 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1752
1753 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
1754 mc->get_hotplug_handler = pc_get_hotpug_handler;
1755 hc->plug = pc_machine_device_plug_cb;
1756 }
1757
1758 static const TypeInfo pc_machine_info = {
1759 .name = TYPE_PC_MACHINE,
1760 .parent = TYPE_MACHINE,
1761 .abstract = true,
1762 .instance_size = sizeof(PCMachineState),
1763 .instance_init = pc_machine_initfn,
1764 .class_size = sizeof(PCMachineClass),
1765 .class_init = pc_machine_class_init,
1766 .interfaces = (InterfaceInfo[]) {
1767 { TYPE_HOTPLUG_HANDLER },
1768 { }
1769 },
1770 };
1771
1772 static void pc_machine_register_types(void)
1773 {
1774 type_register_static(&pc_machine_info);
1775 }
1776
1777 type_init(pc_machine_register_types)