cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/pc.h"
26 #include "hw/serial.h"
27 #include "hw/apic.h"
28 #include "hw/fdc.h"
29 #include "hw/ide.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/fw_cfg.h"
33 #include "hw/hpet_emul.h"
34 #include "hw/smbios.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "hw/multiboot.h"
38 #include "hw/mc146818rtc.h"
39 #include "hw/i8254.h"
40 #include "hw/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_i386.h"
46 #include "hw/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block-common.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54
55 /* debug PC/ISA interrupts */
56 //#define DEBUG_IRQ
57
58 #ifdef DEBUG_IRQ
59 #define DPRINTF(fmt, ...) \
60 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
61 #else
62 #define DPRINTF(fmt, ...)
63 #endif
64
65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
66 #define ACPI_DATA_SIZE 0x10000
67 #define BIOS_CFG_IOPORT 0x510
68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
73
74 #define E820_NR_ENTRIES 16
75
76 struct e820_entry {
77 uint64_t address;
78 uint64_t length;
79 uint32_t type;
80 } QEMU_PACKED __attribute((__aligned__(4)));
81
82 struct e820_table {
83 uint32_t count;
84 struct e820_entry entry[E820_NR_ENTRIES];
85 } QEMU_PACKED __attribute((__aligned__(4)));
86
87 static struct e820_table e820_table;
88 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
89
90 void gsi_handler(void *opaque, int n, int level)
91 {
92 GSIState *s = opaque;
93
94 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
95 if (n < ISA_NUM_IRQS) {
96 qemu_set_irq(s->i8259_irq[n], level);
97 }
98 qemu_set_irq(s->ioapic_irq[n], level);
99 }
100
101 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
102 unsigned size)
103 {
104 }
105
106 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
107 {
108 return 0xffffffffffffffffULL;
109 }
110
111 /* MSDOS compatibility mode FPU exception support */
112 static qemu_irq ferr_irq;
113
114 void pc_register_ferr_irq(qemu_irq irq)
115 {
116 ferr_irq = irq;
117 }
118
119 /* XXX: add IGNNE support */
120 void cpu_set_ferr(CPUX86State *s)
121 {
122 qemu_irq_raise(ferr_irq);
123 }
124
125 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
126 unsigned size)
127 {
128 qemu_irq_lower(ferr_irq);
129 }
130
131 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
132 {
133 return 0xffffffffffffffffULL;
134 }
135
136 /* TSC handling */
137 uint64_t cpu_get_tsc(CPUX86State *env)
138 {
139 return cpu_get_ticks();
140 }
141
142 /* SMM support */
143
144 static cpu_set_smm_t smm_set;
145 static void *smm_arg;
146
147 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
148 {
149 assert(smm_set == NULL);
150 assert(smm_arg == NULL);
151 smm_set = callback;
152 smm_arg = arg;
153 }
154
155 void cpu_smm_update(CPUX86State *env)
156 {
157 if (smm_set && smm_arg && env == first_cpu)
158 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
159 }
160
161
162 /* IRQ handling */
163 int cpu_get_pic_interrupt(CPUX86State *env)
164 {
165 int intno;
166
167 intno = apic_get_interrupt(env->apic_state);
168 if (intno >= 0) {
169 return intno;
170 }
171 /* read the irq from the PIC */
172 if (!apic_accept_pic_intr(env->apic_state)) {
173 return -1;
174 }
175
176 intno = pic_read_irq(isa_pic);
177 return intno;
178 }
179
180 static void pic_irq_request(void *opaque, int irq, int level)
181 {
182 CPUX86State *env = first_cpu;
183
184 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
185 if (env->apic_state) {
186 while (env) {
187 if (apic_accept_pic_intr(env->apic_state)) {
188 apic_deliver_pic_intr(env->apic_state, level);
189 }
190 env = env->next_cpu;
191 }
192 } else {
193 if (level)
194 cpu_interrupt(env, CPU_INTERRUPT_HARD);
195 else
196 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
197 }
198 }
199
200 /* PC cmos mappings */
201
202 #define REG_EQUIPMENT_BYTE 0x14
203
204 static int cmos_get_fd_drive_type(FDriveType fd0)
205 {
206 int val;
207
208 switch (fd0) {
209 case FDRIVE_DRV_144:
210 /* 1.44 Mb 3"5 drive */
211 val = 4;
212 break;
213 case FDRIVE_DRV_288:
214 /* 2.88 Mb 3"5 drive */
215 val = 5;
216 break;
217 case FDRIVE_DRV_120:
218 /* 1.2 Mb 5"5 drive */
219 val = 2;
220 break;
221 case FDRIVE_DRV_NONE:
222 default:
223 val = 0;
224 break;
225 }
226 return val;
227 }
228
229 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
230 int16_t cylinders, int8_t heads, int8_t sectors)
231 {
232 rtc_set_memory(s, type_ofs, 47);
233 rtc_set_memory(s, info_ofs, cylinders);
234 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
235 rtc_set_memory(s, info_ofs + 2, heads);
236 rtc_set_memory(s, info_ofs + 3, 0xff);
237 rtc_set_memory(s, info_ofs + 4, 0xff);
238 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
239 rtc_set_memory(s, info_ofs + 6, cylinders);
240 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
241 rtc_set_memory(s, info_ofs + 8, sectors);
242 }
243
244 /* convert boot_device letter to something recognizable by the bios */
245 static int boot_device2nibble(char boot_device)
246 {
247 switch(boot_device) {
248 case 'a':
249 case 'b':
250 return 0x01; /* floppy boot */
251 case 'c':
252 return 0x02; /* hard drive boot */
253 case 'd':
254 return 0x03; /* CD-ROM boot */
255 case 'n':
256 return 0x04; /* Network boot */
257 }
258 return 0;
259 }
260
261 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
262 {
263 #define PC_MAX_BOOT_DEVICES 3
264 int nbds, bds[3] = { 0, };
265 int i;
266
267 nbds = strlen(boot_device);
268 if (nbds > PC_MAX_BOOT_DEVICES) {
269 error_report("Too many boot devices for PC");
270 return(1);
271 }
272 for (i = 0; i < nbds; i++) {
273 bds[i] = boot_device2nibble(boot_device[i]);
274 if (bds[i] == 0) {
275 error_report("Invalid boot device for PC: '%c'",
276 boot_device[i]);
277 return(1);
278 }
279 }
280 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
281 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
282 return(0);
283 }
284
285 static int pc_boot_set(void *opaque, const char *boot_device)
286 {
287 return set_boot_dev(opaque, boot_device, 0);
288 }
289
290 typedef struct pc_cmos_init_late_arg {
291 ISADevice *rtc_state;
292 BusState *idebus[2];
293 } pc_cmos_init_late_arg;
294
295 static void pc_cmos_init_late(void *opaque)
296 {
297 pc_cmos_init_late_arg *arg = opaque;
298 ISADevice *s = arg->rtc_state;
299 int16_t cylinders;
300 int8_t heads, sectors;
301 int val;
302 int i, trans;
303
304 val = 0;
305 if (ide_get_geometry(arg->idebus[0], 0,
306 &cylinders, &heads, &sectors) >= 0) {
307 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
308 val |= 0xf0;
309 }
310 if (ide_get_geometry(arg->idebus[0], 1,
311 &cylinders, &heads, &sectors) >= 0) {
312 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
313 val |= 0x0f;
314 }
315 rtc_set_memory(s, 0x12, val);
316
317 val = 0;
318 for (i = 0; i < 4; i++) {
319 /* NOTE: ide_get_geometry() returns the physical
320 geometry. It is always such that: 1 <= sects <= 63, 1
321 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
322 geometry can be different if a translation is done. */
323 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
324 &cylinders, &heads, &sectors) >= 0) {
325 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
326 assert((trans & ~3) == 0);
327 val |= trans << (i * 2);
328 }
329 }
330 rtc_set_memory(s, 0x39, val);
331
332 qemu_unregister_reset(pc_cmos_init_late, opaque);
333 }
334
335 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
336 const char *boot_device,
337 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
338 ISADevice *s)
339 {
340 int val, nb, i;
341 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
342 static pc_cmos_init_late_arg arg;
343
344 /* various important CMOS locations needed by PC/Bochs bios */
345
346 /* memory size */
347 /* base memory (first MiB) */
348 val = MIN(ram_size / 1024, 640);
349 rtc_set_memory(s, 0x15, val);
350 rtc_set_memory(s, 0x16, val >> 8);
351 /* extended memory (next 64MiB) */
352 if (ram_size > 1024 * 1024) {
353 val = (ram_size - 1024 * 1024) / 1024;
354 } else {
355 val = 0;
356 }
357 if (val > 65535)
358 val = 65535;
359 rtc_set_memory(s, 0x17, val);
360 rtc_set_memory(s, 0x18, val >> 8);
361 rtc_set_memory(s, 0x30, val);
362 rtc_set_memory(s, 0x31, val >> 8);
363 /* memory between 16MiB and 4GiB */
364 if (ram_size > 16 * 1024 * 1024) {
365 val = (ram_size - 16 * 1024 * 1024) / 65536;
366 } else {
367 val = 0;
368 }
369 if (val > 65535)
370 val = 65535;
371 rtc_set_memory(s, 0x34, val);
372 rtc_set_memory(s, 0x35, val >> 8);
373 /* memory above 4GiB */
374 val = above_4g_mem_size / 65536;
375 rtc_set_memory(s, 0x5b, val);
376 rtc_set_memory(s, 0x5c, val >> 8);
377 rtc_set_memory(s, 0x5d, val >> 16);
378
379 /* set the number of CPU */
380 rtc_set_memory(s, 0x5f, smp_cpus - 1);
381
382 /* set boot devices, and disable floppy signature check if requested */
383 if (set_boot_dev(s, boot_device, fd_bootchk)) {
384 exit(1);
385 }
386
387 /* floppy type */
388 if (floppy) {
389 for (i = 0; i < 2; i++) {
390 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
391 }
392 }
393 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
394 cmos_get_fd_drive_type(fd_type[1]);
395 rtc_set_memory(s, 0x10, val);
396
397 val = 0;
398 nb = 0;
399 if (fd_type[0] < FDRIVE_DRV_NONE) {
400 nb++;
401 }
402 if (fd_type[1] < FDRIVE_DRV_NONE) {
403 nb++;
404 }
405 switch (nb) {
406 case 0:
407 break;
408 case 1:
409 val |= 0x01; /* 1 drive, ready for boot */
410 break;
411 case 2:
412 val |= 0x41; /* 2 drives, ready for boot */
413 break;
414 }
415 val |= 0x02; /* FPU is there */
416 val |= 0x04; /* PS/2 mouse installed */
417 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
418
419 /* hard drives */
420 arg.rtc_state = s;
421 arg.idebus[0] = idebus0;
422 arg.idebus[1] = idebus1;
423 qemu_register_reset(pc_cmos_init_late, &arg);
424 }
425
426 /* port 92 stuff: could be split off */
427 typedef struct Port92State {
428 ISADevice dev;
429 MemoryRegion io;
430 uint8_t outport;
431 qemu_irq *a20_out;
432 } Port92State;
433
434 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
435 unsigned size)
436 {
437 Port92State *s = opaque;
438
439 DPRINTF("port92: write 0x%02x\n", val);
440 s->outport = val;
441 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
442 if (val & 1) {
443 qemu_system_reset_request();
444 }
445 }
446
447 static uint64_t port92_read(void *opaque, hwaddr addr,
448 unsigned size)
449 {
450 Port92State *s = opaque;
451 uint32_t ret;
452
453 ret = s->outport;
454 DPRINTF("port92: read 0x%02x\n", ret);
455 return ret;
456 }
457
458 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
459 {
460 Port92State *s = DO_UPCAST(Port92State, dev, dev);
461
462 s->a20_out = a20_out;
463 }
464
465 static const VMStateDescription vmstate_port92_isa = {
466 .name = "port92",
467 .version_id = 1,
468 .minimum_version_id = 1,
469 .minimum_version_id_old = 1,
470 .fields = (VMStateField []) {
471 VMSTATE_UINT8(outport, Port92State),
472 VMSTATE_END_OF_LIST()
473 }
474 };
475
476 static void port92_reset(DeviceState *d)
477 {
478 Port92State *s = container_of(d, Port92State, dev.qdev);
479
480 s->outport &= ~1;
481 }
482
483 static const MemoryRegionOps port92_ops = {
484 .read = port92_read,
485 .write = port92_write,
486 .impl = {
487 .min_access_size = 1,
488 .max_access_size = 1,
489 },
490 .endianness = DEVICE_LITTLE_ENDIAN,
491 };
492
493 static int port92_initfn(ISADevice *dev)
494 {
495 Port92State *s = DO_UPCAST(Port92State, dev, dev);
496
497 memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
498 isa_register_ioport(dev, &s->io, 0x92);
499
500 s->outport = 0;
501 return 0;
502 }
503
504 static void port92_class_initfn(ObjectClass *klass, void *data)
505 {
506 DeviceClass *dc = DEVICE_CLASS(klass);
507 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
508 ic->init = port92_initfn;
509 dc->no_user = 1;
510 dc->reset = port92_reset;
511 dc->vmsd = &vmstate_port92_isa;
512 }
513
514 static const TypeInfo port92_info = {
515 .name = "port92",
516 .parent = TYPE_ISA_DEVICE,
517 .instance_size = sizeof(Port92State),
518 .class_init = port92_class_initfn,
519 };
520
521 static void port92_register_types(void)
522 {
523 type_register_static(&port92_info);
524 }
525
526 type_init(port92_register_types)
527
528 static void handle_a20_line_change(void *opaque, int irq, int level)
529 {
530 X86CPU *cpu = opaque;
531
532 /* XXX: send to all CPUs ? */
533 /* XXX: add logic to handle multiple A20 line sources */
534 x86_cpu_set_a20(cpu, level);
535 }
536
537 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
538 {
539 int index = le32_to_cpu(e820_table.count);
540 struct e820_entry *entry;
541
542 if (index >= E820_NR_ENTRIES)
543 return -EBUSY;
544 entry = &e820_table.entry[index++];
545
546 entry->address = cpu_to_le64(address);
547 entry->length = cpu_to_le64(length);
548 entry->type = cpu_to_le32(type);
549
550 e820_table.count = cpu_to_le32(index);
551 return index;
552 }
553
554 /* Calculates the limit to CPU APIC ID values
555 *
556 * This function returns the limit for the APIC ID value, so that all
557 * CPU APIC IDs are < pc_apic_id_limit().
558 *
559 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
560 */
561 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
562 {
563 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
564 }
565
566 static void *bochs_bios_init(void)
567 {
568 void *fw_cfg;
569 uint8_t *smbios_table;
570 size_t smbios_len;
571 uint64_t *numa_fw_cfg;
572 int i, j;
573 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
574
575 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
576 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
577 *
578 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
579 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
580 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
581 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
582 * may see".
583 *
584 * So, this means we must not use max_cpus, here, but the maximum possible
585 * APIC ID value, plus one.
586 *
587 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
588 * the APIC ID, not the "CPU index"
589 */
590 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
591 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
592 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
593 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
594 acpi_tables, acpi_tables_len);
595 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
596
597 smbios_table = smbios_get_table(&smbios_len);
598 if (smbios_table)
599 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
600 smbios_table, smbios_len);
601 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
602 &e820_table, sizeof(e820_table));
603
604 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
605 /* allocate memory for the NUMA channel: one (64bit) word for the number
606 * of nodes, one word for each VCPU->node and one word for each node to
607 * hold the amount of memory.
608 */
609 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
610 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
611 for (i = 0; i < max_cpus; i++) {
612 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
613 assert(apic_id < apic_id_limit);
614 for (j = 0; j < nb_numa_nodes; j++) {
615 if (test_bit(i, node_cpumask[j])) {
616 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
617 break;
618 }
619 }
620 }
621 for (i = 0; i < nb_numa_nodes; i++) {
622 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
623 }
624 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
625 (1 + apic_id_limit + nb_numa_nodes) *
626 sizeof(*numa_fw_cfg));
627
628 return fw_cfg;
629 }
630
631 static long get_file_size(FILE *f)
632 {
633 long where, size;
634
635 /* XXX: on Unix systems, using fstat() probably makes more sense */
636
637 where = ftell(f);
638 fseek(f, 0, SEEK_END);
639 size = ftell(f);
640 fseek(f, where, SEEK_SET);
641
642 return size;
643 }
644
645 static void load_linux(void *fw_cfg,
646 const char *kernel_filename,
647 const char *initrd_filename,
648 const char *kernel_cmdline,
649 hwaddr max_ram_size)
650 {
651 uint16_t protocol;
652 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
653 uint32_t initrd_max;
654 uint8_t header[8192], *setup, *kernel, *initrd_data;
655 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
656 FILE *f;
657 char *vmode;
658
659 /* Align to 16 bytes as a paranoia measure */
660 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
661
662 /* load the kernel header */
663 f = fopen(kernel_filename, "rb");
664 if (!f || !(kernel_size = get_file_size(f)) ||
665 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
666 MIN(ARRAY_SIZE(header), kernel_size)) {
667 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
668 kernel_filename, strerror(errno));
669 exit(1);
670 }
671
672 /* kernel protocol version */
673 #if 0
674 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
675 #endif
676 if (ldl_p(header+0x202) == 0x53726448)
677 protocol = lduw_p(header+0x206);
678 else {
679 /* This looks like a multiboot kernel. If it is, let's stop
680 treating it like a Linux kernel. */
681 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
682 kernel_cmdline, kernel_size, header))
683 return;
684 protocol = 0;
685 }
686
687 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
688 /* Low kernel */
689 real_addr = 0x90000;
690 cmdline_addr = 0x9a000 - cmdline_size;
691 prot_addr = 0x10000;
692 } else if (protocol < 0x202) {
693 /* High but ancient kernel */
694 real_addr = 0x90000;
695 cmdline_addr = 0x9a000 - cmdline_size;
696 prot_addr = 0x100000;
697 } else {
698 /* High and recent kernel */
699 real_addr = 0x10000;
700 cmdline_addr = 0x20000;
701 prot_addr = 0x100000;
702 }
703
704 #if 0
705 fprintf(stderr,
706 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
707 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
708 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
709 real_addr,
710 cmdline_addr,
711 prot_addr);
712 #endif
713
714 /* highest address for loading the initrd */
715 if (protocol >= 0x203)
716 initrd_max = ldl_p(header+0x22c);
717 else
718 initrd_max = 0x37ffffff;
719
720 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
721 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
722
723 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
724 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
725 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
726
727 if (protocol >= 0x202) {
728 stl_p(header+0x228, cmdline_addr);
729 } else {
730 stw_p(header+0x20, 0xA33F);
731 stw_p(header+0x22, cmdline_addr-real_addr);
732 }
733
734 /* handle vga= parameter */
735 vmode = strstr(kernel_cmdline, "vga=");
736 if (vmode) {
737 unsigned int video_mode;
738 /* skip "vga=" */
739 vmode += 4;
740 if (!strncmp(vmode, "normal", 6)) {
741 video_mode = 0xffff;
742 } else if (!strncmp(vmode, "ext", 3)) {
743 video_mode = 0xfffe;
744 } else if (!strncmp(vmode, "ask", 3)) {
745 video_mode = 0xfffd;
746 } else {
747 video_mode = strtol(vmode, NULL, 0);
748 }
749 stw_p(header+0x1fa, video_mode);
750 }
751
752 /* loader type */
753 /* High nybble = B reserved for QEMU; low nybble is revision number.
754 If this code is substantially changed, you may want to consider
755 incrementing the revision. */
756 if (protocol >= 0x200)
757 header[0x210] = 0xB0;
758
759 /* heap */
760 if (protocol >= 0x201) {
761 header[0x211] |= 0x80; /* CAN_USE_HEAP */
762 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
763 }
764
765 /* load initrd */
766 if (initrd_filename) {
767 if (protocol < 0x200) {
768 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
769 exit(1);
770 }
771
772 initrd_size = get_image_size(initrd_filename);
773 if (initrd_size < 0) {
774 fprintf(stderr, "qemu: error reading initrd %s\n",
775 initrd_filename);
776 exit(1);
777 }
778
779 initrd_addr = (initrd_max-initrd_size) & ~4095;
780
781 initrd_data = g_malloc(initrd_size);
782 load_image(initrd_filename, initrd_data);
783
784 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
785 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
786 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
787
788 stl_p(header+0x218, initrd_addr);
789 stl_p(header+0x21c, initrd_size);
790 }
791
792 /* load kernel and setup */
793 setup_size = header[0x1f1];
794 if (setup_size == 0)
795 setup_size = 4;
796 setup_size = (setup_size+1)*512;
797 kernel_size -= setup_size;
798
799 setup = g_malloc(setup_size);
800 kernel = g_malloc(kernel_size);
801 fseek(f, 0, SEEK_SET);
802 if (fread(setup, 1, setup_size, f) != setup_size) {
803 fprintf(stderr, "fread() failed\n");
804 exit(1);
805 }
806 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
807 fprintf(stderr, "fread() failed\n");
808 exit(1);
809 }
810 fclose(f);
811 memcpy(setup, header, MIN(sizeof(header), setup_size));
812
813 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
814 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
815 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
816
817 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
818 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
819 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
820
821 option_rom[nb_option_roms].name = "linuxboot.bin";
822 option_rom[nb_option_roms].bootindex = 0;
823 nb_option_roms++;
824 }
825
826 #define NE2000_NB_MAX 6
827
828 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
829 0x280, 0x380 };
830 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
831
832 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
833 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
834
835 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
836 {
837 static int nb_ne2k = 0;
838
839 if (nb_ne2k == NE2000_NB_MAX)
840 return;
841 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
842 ne2000_irq[nb_ne2k], nd);
843 nb_ne2k++;
844 }
845
846 DeviceState *cpu_get_current_apic(void)
847 {
848 if (cpu_single_env) {
849 return cpu_single_env->apic_state;
850 } else {
851 return NULL;
852 }
853 }
854
855 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
856 {
857 CPUX86State *s = opaque;
858
859 if (level) {
860 cpu_interrupt(s, CPU_INTERRUPT_SMI);
861 }
862 }
863
864 void pc_cpus_init(const char *cpu_model)
865 {
866 int i;
867
868 /* init CPUs */
869 if (cpu_model == NULL) {
870 #ifdef TARGET_X86_64
871 cpu_model = "qemu64";
872 #else
873 cpu_model = "qemu32";
874 #endif
875 }
876
877 for (i = 0; i < smp_cpus; i++) {
878 if (!cpu_x86_init(cpu_model)) {
879 exit(1);
880 }
881 }
882 }
883
884 void pc_acpi_init(const char *default_dsdt)
885 {
886 char *filename = NULL, *arg = NULL;
887
888 if (acpi_tables != NULL) {
889 /* manually set via -acpitable, leave it alone */
890 return;
891 }
892
893 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
894 if (filename == NULL) {
895 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
896 return;
897 }
898
899 arg = g_strdup_printf("file=%s", filename);
900 if (acpi_table_add(arg) != 0) {
901 fprintf(stderr, "WARNING: failed to load %s\n", filename);
902 }
903 g_free(arg);
904 g_free(filename);
905 }
906
907 void *pc_memory_init(MemoryRegion *system_memory,
908 const char *kernel_filename,
909 const char *kernel_cmdline,
910 const char *initrd_filename,
911 ram_addr_t below_4g_mem_size,
912 ram_addr_t above_4g_mem_size,
913 MemoryRegion *rom_memory,
914 MemoryRegion **ram_memory)
915 {
916 int linux_boot, i;
917 MemoryRegion *ram, *option_rom_mr;
918 MemoryRegion *ram_below_4g, *ram_above_4g;
919 void *fw_cfg;
920
921 linux_boot = (kernel_filename != NULL);
922
923 /* Allocate RAM. We allocate it as a single memory region and use
924 * aliases to address portions of it, mostly for backwards compatibility
925 * with older qemus that used qemu_ram_alloc().
926 */
927 ram = g_malloc(sizeof(*ram));
928 memory_region_init_ram(ram, "pc.ram",
929 below_4g_mem_size + above_4g_mem_size);
930 vmstate_register_ram_global(ram);
931 *ram_memory = ram;
932 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
933 memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
934 0, below_4g_mem_size);
935 memory_region_add_subregion(system_memory, 0, ram_below_4g);
936 if (above_4g_mem_size > 0) {
937 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
938 memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
939 below_4g_mem_size, above_4g_mem_size);
940 memory_region_add_subregion(system_memory, 0x100000000ULL,
941 ram_above_4g);
942 }
943
944
945 /* Initialize PC system firmware */
946 pc_system_firmware_init(rom_memory);
947
948 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
949 memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
950 vmstate_register_ram_global(option_rom_mr);
951 memory_region_add_subregion_overlap(rom_memory,
952 PC_ROM_MIN_VGA,
953 option_rom_mr,
954 1);
955
956 fw_cfg = bochs_bios_init();
957 rom_set_fw(fw_cfg);
958
959 if (linux_boot) {
960 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
961 }
962
963 for (i = 0; i < nb_option_roms; i++) {
964 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
965 }
966 return fw_cfg;
967 }
968
969 qemu_irq *pc_allocate_cpu_irq(void)
970 {
971 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
972 }
973
974 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
975 {
976 DeviceState *dev = NULL;
977
978 if (pci_bus) {
979 PCIDevice *pcidev = pci_vga_init(pci_bus);
980 dev = pcidev ? &pcidev->qdev : NULL;
981 } else if (isa_bus) {
982 ISADevice *isadev = isa_vga_init(isa_bus);
983 dev = isadev ? &isadev->qdev : NULL;
984 }
985 return dev;
986 }
987
988 static void cpu_request_exit(void *opaque, int irq, int level)
989 {
990 CPUX86State *env = cpu_single_env;
991
992 if (env && level) {
993 cpu_exit(env);
994 }
995 }
996
997 static const MemoryRegionOps ioport80_io_ops = {
998 .write = ioport80_write,
999 .read = ioport80_read,
1000 .endianness = DEVICE_NATIVE_ENDIAN,
1001 .impl = {
1002 .min_access_size = 1,
1003 .max_access_size = 1,
1004 },
1005 };
1006
1007 static const MemoryRegionOps ioportF0_io_ops = {
1008 .write = ioportF0_write,
1009 .read = ioportF0_read,
1010 .endianness = DEVICE_NATIVE_ENDIAN,
1011 .impl = {
1012 .min_access_size = 1,
1013 .max_access_size = 1,
1014 },
1015 };
1016
1017 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1018 ISADevice **rtc_state,
1019 ISADevice **floppy,
1020 bool no_vmport)
1021 {
1022 int i;
1023 DriveInfo *fd[MAX_FD];
1024 DeviceState *hpet = NULL;
1025 int pit_isa_irq = 0;
1026 qemu_irq pit_alt_irq = NULL;
1027 qemu_irq rtc_irq = NULL;
1028 qemu_irq *a20_line;
1029 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1030 qemu_irq *cpu_exit_irq;
1031 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1032 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1033
1034 memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1035 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1036
1037 memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1038 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1039
1040 /*
1041 * Check if an HPET shall be created.
1042 *
1043 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1044 * when the HPET wants to take over. Thus we have to disable the latter.
1045 */
1046 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1047 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1048
1049 if (hpet) {
1050 for (i = 0; i < GSI_NUM_PINS; i++) {
1051 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1052 }
1053 pit_isa_irq = -1;
1054 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1055 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1056 }
1057 }
1058 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1059
1060 qemu_register_boot_set(pc_boot_set, *rtc_state);
1061
1062 if (!xen_enabled()) {
1063 if (kvm_irqchip_in_kernel()) {
1064 pit = kvm_pit_init(isa_bus, 0x40);
1065 } else {
1066 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1067 }
1068 if (hpet) {
1069 /* connect PIT to output control line of the HPET */
1070 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1071 }
1072 pcspk_init(isa_bus, pit);
1073 }
1074
1075 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1076 if (serial_hds[i]) {
1077 serial_isa_init(isa_bus, i, serial_hds[i]);
1078 }
1079 }
1080
1081 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1082 if (parallel_hds[i]) {
1083 parallel_init(isa_bus, i, parallel_hds[i]);
1084 }
1085 }
1086
1087 a20_line = qemu_allocate_irqs(handle_a20_line_change,
1088 x86_env_get_cpu(first_cpu), 2);
1089 i8042 = isa_create_simple(isa_bus, "i8042");
1090 i8042_setup_a20_line(i8042, &a20_line[0]);
1091 if (!no_vmport) {
1092 vmport_init(isa_bus);
1093 vmmouse = isa_try_create(isa_bus, "vmmouse");
1094 } else {
1095 vmmouse = NULL;
1096 }
1097 if (vmmouse) {
1098 qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1099 qdev_init_nofail(&vmmouse->qdev);
1100 }
1101 port92 = isa_create_simple(isa_bus, "port92");
1102 port92_init(port92, &a20_line[1]);
1103
1104 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1105 DMA_init(0, cpu_exit_irq);
1106
1107 for(i = 0; i < MAX_FD; i++) {
1108 fd[i] = drive_get(IF_FLOPPY, 0, i);
1109 }
1110 *floppy = fdctrl_init_isa(isa_bus, fd);
1111 }
1112
1113 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1114 {
1115 int i;
1116
1117 for (i = 0; i < nb_nics; i++) {
1118 NICInfo *nd = &nd_table[i];
1119
1120 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1121 pc_init_ne2k_isa(isa_bus, nd);
1122 } else {
1123 pci_nic_init_nofail(nd, "e1000", NULL);
1124 }
1125 }
1126 }
1127
1128 void pc_pci_device_init(PCIBus *pci_bus)
1129 {
1130 int max_bus;
1131 int bus;
1132
1133 max_bus = drive_get_max_bus(IF_SCSI);
1134 for (bus = 0; bus <= max_bus; bus++) {
1135 pci_create_simple(pci_bus, -1, "lsi53c895a");
1136 }
1137 }
1138
1139 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1140 {
1141 DeviceState *dev;
1142 SysBusDevice *d;
1143 unsigned int i;
1144
1145 if (kvm_irqchip_in_kernel()) {
1146 dev = qdev_create(NULL, "kvm-ioapic");
1147 } else {
1148 dev = qdev_create(NULL, "ioapic");
1149 }
1150 if (parent_name) {
1151 object_property_add_child(object_resolve_path(parent_name, NULL),
1152 "ioapic", OBJECT(dev), NULL);
1153 }
1154 qdev_init_nofail(dev);
1155 d = SYS_BUS_DEVICE(dev);
1156 sysbus_mmio_map(d, 0, 0xfec00000);
1157
1158 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1159 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1160 }
1161 }