pc: exit QEMU if number of slots more than supported 256
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
29 #include "hw/ide.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
61
62 /* debug PC/ISA interrupts */
63 //#define DEBUG_IRQ
64
65 #ifdef DEBUG_IRQ
66 #define DPRINTF(fmt, ...) \
67 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
68 #else
69 #define DPRINTF(fmt, ...)
70 #endif
71
72 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
73 #define ACPI_DATA_SIZE 0x10000
74 #define BIOS_CFG_IOPORT 0x510
75 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
76 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
77 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
78 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
79 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
80
81 #define E820_NR_ENTRIES 16
82
83 struct e820_entry {
84 uint64_t address;
85 uint64_t length;
86 uint32_t type;
87 } QEMU_PACKED __attribute((__aligned__(4)));
88
89 struct e820_table {
90 uint32_t count;
91 struct e820_entry entry[E820_NR_ENTRIES];
92 } QEMU_PACKED __attribute((__aligned__(4)));
93
94 static struct e820_table e820_reserve;
95 static struct e820_entry *e820_table;
96 static unsigned e820_entries;
97 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
98
99 void gsi_handler(void *opaque, int n, int level)
100 {
101 GSIState *s = opaque;
102
103 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
104 if (n < ISA_NUM_IRQS) {
105 qemu_set_irq(s->i8259_irq[n], level);
106 }
107 qemu_set_irq(s->ioapic_irq[n], level);
108 }
109
110 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
111 unsigned size)
112 {
113 }
114
115 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
116 {
117 return 0xffffffffffffffffULL;
118 }
119
120 /* MSDOS compatibility mode FPU exception support */
121 static qemu_irq ferr_irq;
122
123 void pc_register_ferr_irq(qemu_irq irq)
124 {
125 ferr_irq = irq;
126 }
127
128 /* XXX: add IGNNE support */
129 void cpu_set_ferr(CPUX86State *s)
130 {
131 qemu_irq_raise(ferr_irq);
132 }
133
134 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
135 unsigned size)
136 {
137 qemu_irq_lower(ferr_irq);
138 }
139
140 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
141 {
142 return 0xffffffffffffffffULL;
143 }
144
145 /* TSC handling */
146 uint64_t cpu_get_tsc(CPUX86State *env)
147 {
148 return cpu_get_ticks();
149 }
150
151 /* SMM support */
152
153 static cpu_set_smm_t smm_set;
154 static void *smm_arg;
155
156 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
157 {
158 assert(smm_set == NULL);
159 assert(smm_arg == NULL);
160 smm_set = callback;
161 smm_arg = arg;
162 }
163
164 void cpu_smm_update(CPUX86State *env)
165 {
166 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
167 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
168 }
169 }
170
171
172 /* IRQ handling */
173 int cpu_get_pic_interrupt(CPUX86State *env)
174 {
175 X86CPU *cpu = x86_env_get_cpu(env);
176 int intno;
177
178 intno = apic_get_interrupt(cpu->apic_state);
179 if (intno >= 0) {
180 return intno;
181 }
182 /* read the irq from the PIC */
183 if (!apic_accept_pic_intr(cpu->apic_state)) {
184 return -1;
185 }
186
187 intno = pic_read_irq(isa_pic);
188 return intno;
189 }
190
191 static void pic_irq_request(void *opaque, int irq, int level)
192 {
193 CPUState *cs = first_cpu;
194 X86CPU *cpu = X86_CPU(cs);
195
196 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
197 if (cpu->apic_state) {
198 CPU_FOREACH(cs) {
199 cpu = X86_CPU(cs);
200 if (apic_accept_pic_intr(cpu->apic_state)) {
201 apic_deliver_pic_intr(cpu->apic_state, level);
202 }
203 }
204 } else {
205 if (level) {
206 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
207 } else {
208 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
209 }
210 }
211 }
212
213 /* PC cmos mappings */
214
215 #define REG_EQUIPMENT_BYTE 0x14
216
217 static int cmos_get_fd_drive_type(FDriveType fd0)
218 {
219 int val;
220
221 switch (fd0) {
222 case FDRIVE_DRV_144:
223 /* 1.44 Mb 3"5 drive */
224 val = 4;
225 break;
226 case FDRIVE_DRV_288:
227 /* 2.88 Mb 3"5 drive */
228 val = 5;
229 break;
230 case FDRIVE_DRV_120:
231 /* 1.2 Mb 5"5 drive */
232 val = 2;
233 break;
234 case FDRIVE_DRV_NONE:
235 default:
236 val = 0;
237 break;
238 }
239 return val;
240 }
241
242 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
243 int16_t cylinders, int8_t heads, int8_t sectors)
244 {
245 rtc_set_memory(s, type_ofs, 47);
246 rtc_set_memory(s, info_ofs, cylinders);
247 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
248 rtc_set_memory(s, info_ofs + 2, heads);
249 rtc_set_memory(s, info_ofs + 3, 0xff);
250 rtc_set_memory(s, info_ofs + 4, 0xff);
251 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
252 rtc_set_memory(s, info_ofs + 6, cylinders);
253 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
254 rtc_set_memory(s, info_ofs + 8, sectors);
255 }
256
257 /* convert boot_device letter to something recognizable by the bios */
258 static int boot_device2nibble(char boot_device)
259 {
260 switch(boot_device) {
261 case 'a':
262 case 'b':
263 return 0x01; /* floppy boot */
264 case 'c':
265 return 0x02; /* hard drive boot */
266 case 'd':
267 return 0x03; /* CD-ROM boot */
268 case 'n':
269 return 0x04; /* Network boot */
270 }
271 return 0;
272 }
273
274 static int set_boot_dev(ISADevice *s, const char *boot_device)
275 {
276 #define PC_MAX_BOOT_DEVICES 3
277 int nbds, bds[3] = { 0, };
278 int i;
279
280 nbds = strlen(boot_device);
281 if (nbds > PC_MAX_BOOT_DEVICES) {
282 error_report("Too many boot devices for PC");
283 return(1);
284 }
285 for (i = 0; i < nbds; i++) {
286 bds[i] = boot_device2nibble(boot_device[i]);
287 if (bds[i] == 0) {
288 error_report("Invalid boot device for PC: '%c'",
289 boot_device[i]);
290 return(1);
291 }
292 }
293 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
294 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
295 return(0);
296 }
297
298 static int pc_boot_set(void *opaque, const char *boot_device)
299 {
300 return set_boot_dev(opaque, boot_device);
301 }
302
303 typedef struct pc_cmos_init_late_arg {
304 ISADevice *rtc_state;
305 BusState *idebus[2];
306 } pc_cmos_init_late_arg;
307
308 static void pc_cmos_init_late(void *opaque)
309 {
310 pc_cmos_init_late_arg *arg = opaque;
311 ISADevice *s = arg->rtc_state;
312 int16_t cylinders;
313 int8_t heads, sectors;
314 int val;
315 int i, trans;
316
317 val = 0;
318 if (ide_get_geometry(arg->idebus[0], 0,
319 &cylinders, &heads, &sectors) >= 0) {
320 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
321 val |= 0xf0;
322 }
323 if (ide_get_geometry(arg->idebus[0], 1,
324 &cylinders, &heads, &sectors) >= 0) {
325 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
326 val |= 0x0f;
327 }
328 rtc_set_memory(s, 0x12, val);
329
330 val = 0;
331 for (i = 0; i < 4; i++) {
332 /* NOTE: ide_get_geometry() returns the physical
333 geometry. It is always such that: 1 <= sects <= 63, 1
334 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
335 geometry can be different if a translation is done. */
336 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
337 &cylinders, &heads, &sectors) >= 0) {
338 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
339 assert((trans & ~3) == 0);
340 val |= trans << (i * 2);
341 }
342 }
343 rtc_set_memory(s, 0x39, val);
344
345 qemu_unregister_reset(pc_cmos_init_late, opaque);
346 }
347
348 typedef struct RTCCPUHotplugArg {
349 Notifier cpu_added_notifier;
350 ISADevice *rtc_state;
351 } RTCCPUHotplugArg;
352
353 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
354 {
355 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
356 cpu_added_notifier);
357 ISADevice *s = arg->rtc_state;
358
359 /* increment the number of CPUs */
360 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
361 }
362
363 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
364 const char *boot_device,
365 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
366 ISADevice *s)
367 {
368 int val, nb, i;
369 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
370 static pc_cmos_init_late_arg arg;
371 static RTCCPUHotplugArg cpu_hotplug_cb;
372
373 /* various important CMOS locations needed by PC/Bochs bios */
374
375 /* memory size */
376 /* base memory (first MiB) */
377 val = MIN(ram_size / 1024, 640);
378 rtc_set_memory(s, 0x15, val);
379 rtc_set_memory(s, 0x16, val >> 8);
380 /* extended memory (next 64MiB) */
381 if (ram_size > 1024 * 1024) {
382 val = (ram_size - 1024 * 1024) / 1024;
383 } else {
384 val = 0;
385 }
386 if (val > 65535)
387 val = 65535;
388 rtc_set_memory(s, 0x17, val);
389 rtc_set_memory(s, 0x18, val >> 8);
390 rtc_set_memory(s, 0x30, val);
391 rtc_set_memory(s, 0x31, val >> 8);
392 /* memory between 16MiB and 4GiB */
393 if (ram_size > 16 * 1024 * 1024) {
394 val = (ram_size - 16 * 1024 * 1024) / 65536;
395 } else {
396 val = 0;
397 }
398 if (val > 65535)
399 val = 65535;
400 rtc_set_memory(s, 0x34, val);
401 rtc_set_memory(s, 0x35, val >> 8);
402 /* memory above 4GiB */
403 val = above_4g_mem_size / 65536;
404 rtc_set_memory(s, 0x5b, val);
405 rtc_set_memory(s, 0x5c, val >> 8);
406 rtc_set_memory(s, 0x5d, val >> 16);
407
408 /* set the number of CPU */
409 rtc_set_memory(s, 0x5f, smp_cpus - 1);
410 /* init CPU hotplug notifier */
411 cpu_hotplug_cb.rtc_state = s;
412 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
413 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
414
415 if (set_boot_dev(s, boot_device)) {
416 exit(1);
417 }
418
419 /* floppy type */
420 if (floppy) {
421 for (i = 0; i < 2; i++) {
422 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
423 }
424 }
425 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
426 cmos_get_fd_drive_type(fd_type[1]);
427 rtc_set_memory(s, 0x10, val);
428
429 val = 0;
430 nb = 0;
431 if (fd_type[0] < FDRIVE_DRV_NONE) {
432 nb++;
433 }
434 if (fd_type[1] < FDRIVE_DRV_NONE) {
435 nb++;
436 }
437 switch (nb) {
438 case 0:
439 break;
440 case 1:
441 val |= 0x01; /* 1 drive, ready for boot */
442 break;
443 case 2:
444 val |= 0x41; /* 2 drives, ready for boot */
445 break;
446 }
447 val |= 0x02; /* FPU is there */
448 val |= 0x04; /* PS/2 mouse installed */
449 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
450
451 /* hard drives */
452 arg.rtc_state = s;
453 arg.idebus[0] = idebus0;
454 arg.idebus[1] = idebus1;
455 qemu_register_reset(pc_cmos_init_late, &arg);
456 }
457
458 #define TYPE_PORT92 "port92"
459 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
460
461 /* port 92 stuff: could be split off */
462 typedef struct Port92State {
463 ISADevice parent_obj;
464
465 MemoryRegion io;
466 uint8_t outport;
467 qemu_irq *a20_out;
468 } Port92State;
469
470 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
471 unsigned size)
472 {
473 Port92State *s = opaque;
474 int oldval = s->outport;
475
476 DPRINTF("port92: write 0x%02x\n", val);
477 s->outport = val;
478 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
479 if ((val & 1) && !(oldval & 1)) {
480 qemu_system_reset_request();
481 }
482 }
483
484 static uint64_t port92_read(void *opaque, hwaddr addr,
485 unsigned size)
486 {
487 Port92State *s = opaque;
488 uint32_t ret;
489
490 ret = s->outport;
491 DPRINTF("port92: read 0x%02x\n", ret);
492 return ret;
493 }
494
495 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
496 {
497 Port92State *s = PORT92(dev);
498
499 s->a20_out = a20_out;
500 }
501
502 static const VMStateDescription vmstate_port92_isa = {
503 .name = "port92",
504 .version_id = 1,
505 .minimum_version_id = 1,
506 .fields = (VMStateField[]) {
507 VMSTATE_UINT8(outport, Port92State),
508 VMSTATE_END_OF_LIST()
509 }
510 };
511
512 static void port92_reset(DeviceState *d)
513 {
514 Port92State *s = PORT92(d);
515
516 s->outport &= ~1;
517 }
518
519 static const MemoryRegionOps port92_ops = {
520 .read = port92_read,
521 .write = port92_write,
522 .impl = {
523 .min_access_size = 1,
524 .max_access_size = 1,
525 },
526 .endianness = DEVICE_LITTLE_ENDIAN,
527 };
528
529 static void port92_initfn(Object *obj)
530 {
531 Port92State *s = PORT92(obj);
532
533 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
534
535 s->outport = 0;
536 }
537
538 static void port92_realizefn(DeviceState *dev, Error **errp)
539 {
540 ISADevice *isadev = ISA_DEVICE(dev);
541 Port92State *s = PORT92(dev);
542
543 isa_register_ioport(isadev, &s->io, 0x92);
544 }
545
546 static void port92_class_initfn(ObjectClass *klass, void *data)
547 {
548 DeviceClass *dc = DEVICE_CLASS(klass);
549
550 dc->realize = port92_realizefn;
551 dc->reset = port92_reset;
552 dc->vmsd = &vmstate_port92_isa;
553 /*
554 * Reason: unlike ordinary ISA devices, this one needs additional
555 * wiring: its A20 output line needs to be wired up by
556 * port92_init().
557 */
558 dc->cannot_instantiate_with_device_add_yet = true;
559 }
560
561 static const TypeInfo port92_info = {
562 .name = TYPE_PORT92,
563 .parent = TYPE_ISA_DEVICE,
564 .instance_size = sizeof(Port92State),
565 .instance_init = port92_initfn,
566 .class_init = port92_class_initfn,
567 };
568
569 static void port92_register_types(void)
570 {
571 type_register_static(&port92_info);
572 }
573
574 type_init(port92_register_types)
575
576 static void handle_a20_line_change(void *opaque, int irq, int level)
577 {
578 X86CPU *cpu = opaque;
579
580 /* XXX: send to all CPUs ? */
581 /* XXX: add logic to handle multiple A20 line sources */
582 x86_cpu_set_a20(cpu, level);
583 }
584
585 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
586 {
587 int index = le32_to_cpu(e820_reserve.count);
588 struct e820_entry *entry;
589
590 if (type != E820_RAM) {
591 /* old FW_CFG_E820_TABLE entry -- reservations only */
592 if (index >= E820_NR_ENTRIES) {
593 return -EBUSY;
594 }
595 entry = &e820_reserve.entry[index++];
596
597 entry->address = cpu_to_le64(address);
598 entry->length = cpu_to_le64(length);
599 entry->type = cpu_to_le32(type);
600
601 e820_reserve.count = cpu_to_le32(index);
602 }
603
604 /* new "etc/e820" file -- include ram too */
605 e820_table = g_realloc(e820_table,
606 sizeof(struct e820_entry) * (e820_entries+1));
607 e820_table[e820_entries].address = cpu_to_le64(address);
608 e820_table[e820_entries].length = cpu_to_le64(length);
609 e820_table[e820_entries].type = cpu_to_le32(type);
610 e820_entries++;
611
612 return e820_entries;
613 }
614
615 int e820_get_num_entries(void)
616 {
617 return e820_entries;
618 }
619
620 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
621 {
622 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
623 *address = le64_to_cpu(e820_table[idx].address);
624 *length = le64_to_cpu(e820_table[idx].length);
625 return true;
626 }
627 return false;
628 }
629
630 /* Calculates the limit to CPU APIC ID values
631 *
632 * This function returns the limit for the APIC ID value, so that all
633 * CPU APIC IDs are < pc_apic_id_limit().
634 *
635 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
636 */
637 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
638 {
639 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
640 }
641
642 static FWCfgState *bochs_bios_init(void)
643 {
644 FWCfgState *fw_cfg;
645 uint8_t *smbios_tables, *smbios_anchor;
646 size_t smbios_tables_len, smbios_anchor_len;
647 uint64_t *numa_fw_cfg;
648 int i, j;
649 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
650
651 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
652 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
653 *
654 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
655 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
656 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
657 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
658 * may see".
659 *
660 * So, this means we must not use max_cpus, here, but the maximum possible
661 * APIC ID value, plus one.
662 *
663 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
664 * the APIC ID, not the "CPU index"
665 */
666 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
667 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
668 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
669 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
670 acpi_tables, acpi_tables_len);
671 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
672
673 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
674 if (smbios_tables) {
675 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
676 smbios_tables, smbios_tables_len);
677 }
678
679 smbios_get_tables(&smbios_tables, &smbios_tables_len,
680 &smbios_anchor, &smbios_anchor_len);
681 if (smbios_anchor) {
682 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
683 smbios_tables, smbios_tables_len);
684 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
685 smbios_anchor, smbios_anchor_len);
686 }
687
688 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
689 &e820_reserve, sizeof(e820_reserve));
690 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
691 sizeof(struct e820_entry) * e820_entries);
692
693 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
694 /* allocate memory for the NUMA channel: one (64bit) word for the number
695 * of nodes, one word for each VCPU->node and one word for each node to
696 * hold the amount of memory.
697 */
698 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
699 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
700 for (i = 0; i < max_cpus; i++) {
701 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
702 assert(apic_id < apic_id_limit);
703 for (j = 0; j < nb_numa_nodes; j++) {
704 if (test_bit(i, node_cpumask[j])) {
705 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
706 break;
707 }
708 }
709 }
710 for (i = 0; i < nb_numa_nodes; i++) {
711 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
712 }
713 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
714 (1 + apic_id_limit + nb_numa_nodes) *
715 sizeof(*numa_fw_cfg));
716
717 return fw_cfg;
718 }
719
720 static long get_file_size(FILE *f)
721 {
722 long where, size;
723
724 /* XXX: on Unix systems, using fstat() probably makes more sense */
725
726 where = ftell(f);
727 fseek(f, 0, SEEK_END);
728 size = ftell(f);
729 fseek(f, where, SEEK_SET);
730
731 return size;
732 }
733
734 static void load_linux(FWCfgState *fw_cfg,
735 const char *kernel_filename,
736 const char *initrd_filename,
737 const char *kernel_cmdline,
738 hwaddr max_ram_size)
739 {
740 uint16_t protocol;
741 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
742 uint32_t initrd_max;
743 uint8_t header[8192], *setup, *kernel, *initrd_data;
744 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
745 FILE *f;
746 char *vmode;
747
748 /* Align to 16 bytes as a paranoia measure */
749 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
750
751 /* load the kernel header */
752 f = fopen(kernel_filename, "rb");
753 if (!f || !(kernel_size = get_file_size(f)) ||
754 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
755 MIN(ARRAY_SIZE(header), kernel_size)) {
756 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
757 kernel_filename, strerror(errno));
758 exit(1);
759 }
760
761 /* kernel protocol version */
762 #if 0
763 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
764 #endif
765 if (ldl_p(header+0x202) == 0x53726448) {
766 protocol = lduw_p(header+0x206);
767 } else {
768 /* This looks like a multiboot kernel. If it is, let's stop
769 treating it like a Linux kernel. */
770 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
771 kernel_cmdline, kernel_size, header)) {
772 return;
773 }
774 protocol = 0;
775 }
776
777 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
778 /* Low kernel */
779 real_addr = 0x90000;
780 cmdline_addr = 0x9a000 - cmdline_size;
781 prot_addr = 0x10000;
782 } else if (protocol < 0x202) {
783 /* High but ancient kernel */
784 real_addr = 0x90000;
785 cmdline_addr = 0x9a000 - cmdline_size;
786 prot_addr = 0x100000;
787 } else {
788 /* High and recent kernel */
789 real_addr = 0x10000;
790 cmdline_addr = 0x20000;
791 prot_addr = 0x100000;
792 }
793
794 #if 0
795 fprintf(stderr,
796 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
797 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
798 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
799 real_addr,
800 cmdline_addr,
801 prot_addr);
802 #endif
803
804 /* highest address for loading the initrd */
805 if (protocol >= 0x203) {
806 initrd_max = ldl_p(header+0x22c);
807 } else {
808 initrd_max = 0x37ffffff;
809 }
810
811 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
812 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
813
814 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
815 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
816 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
817
818 if (protocol >= 0x202) {
819 stl_p(header+0x228, cmdline_addr);
820 } else {
821 stw_p(header+0x20, 0xA33F);
822 stw_p(header+0x22, cmdline_addr-real_addr);
823 }
824
825 /* handle vga= parameter */
826 vmode = strstr(kernel_cmdline, "vga=");
827 if (vmode) {
828 unsigned int video_mode;
829 /* skip "vga=" */
830 vmode += 4;
831 if (!strncmp(vmode, "normal", 6)) {
832 video_mode = 0xffff;
833 } else if (!strncmp(vmode, "ext", 3)) {
834 video_mode = 0xfffe;
835 } else if (!strncmp(vmode, "ask", 3)) {
836 video_mode = 0xfffd;
837 } else {
838 video_mode = strtol(vmode, NULL, 0);
839 }
840 stw_p(header+0x1fa, video_mode);
841 }
842
843 /* loader type */
844 /* High nybble = B reserved for QEMU; low nybble is revision number.
845 If this code is substantially changed, you may want to consider
846 incrementing the revision. */
847 if (protocol >= 0x200) {
848 header[0x210] = 0xB0;
849 }
850 /* heap */
851 if (protocol >= 0x201) {
852 header[0x211] |= 0x80; /* CAN_USE_HEAP */
853 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
854 }
855
856 /* load initrd */
857 if (initrd_filename) {
858 if (protocol < 0x200) {
859 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
860 exit(1);
861 }
862
863 initrd_size = get_image_size(initrd_filename);
864 if (initrd_size < 0) {
865 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
866 initrd_filename, strerror(errno));
867 exit(1);
868 }
869
870 initrd_addr = (initrd_max-initrd_size) & ~4095;
871
872 initrd_data = g_malloc(initrd_size);
873 load_image(initrd_filename, initrd_data);
874
875 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
876 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
877 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
878
879 stl_p(header+0x218, initrd_addr);
880 stl_p(header+0x21c, initrd_size);
881 }
882
883 /* load kernel and setup */
884 setup_size = header[0x1f1];
885 if (setup_size == 0) {
886 setup_size = 4;
887 }
888 setup_size = (setup_size+1)*512;
889 kernel_size -= setup_size;
890
891 setup = g_malloc(setup_size);
892 kernel = g_malloc(kernel_size);
893 fseek(f, 0, SEEK_SET);
894 if (fread(setup, 1, setup_size, f) != setup_size) {
895 fprintf(stderr, "fread() failed\n");
896 exit(1);
897 }
898 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
899 fprintf(stderr, "fread() failed\n");
900 exit(1);
901 }
902 fclose(f);
903 memcpy(setup, header, MIN(sizeof(header), setup_size));
904
905 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
906 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
907 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
908
909 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
910 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
911 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
912
913 option_rom[nb_option_roms].name = "linuxboot.bin";
914 option_rom[nb_option_roms].bootindex = 0;
915 nb_option_roms++;
916 }
917
918 #define NE2000_NB_MAX 6
919
920 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
921 0x280, 0x380 };
922 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
923
924 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
925 {
926 static int nb_ne2k = 0;
927
928 if (nb_ne2k == NE2000_NB_MAX)
929 return;
930 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
931 ne2000_irq[nb_ne2k], nd);
932 nb_ne2k++;
933 }
934
935 DeviceState *cpu_get_current_apic(void)
936 {
937 if (current_cpu) {
938 X86CPU *cpu = X86_CPU(current_cpu);
939 return cpu->apic_state;
940 } else {
941 return NULL;
942 }
943 }
944
945 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
946 {
947 X86CPU *cpu = opaque;
948
949 if (level) {
950 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
951 }
952 }
953
954 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
955 DeviceState *icc_bridge, Error **errp)
956 {
957 X86CPU *cpu;
958 Error *local_err = NULL;
959
960 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
961 if (local_err != NULL) {
962 error_propagate(errp, local_err);
963 return NULL;
964 }
965
966 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
967 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
968
969 if (local_err) {
970 error_propagate(errp, local_err);
971 object_unref(OBJECT(cpu));
972 cpu = NULL;
973 }
974 return cpu;
975 }
976
977 static const char *current_cpu_model;
978
979 void pc_hot_add_cpu(const int64_t id, Error **errp)
980 {
981 DeviceState *icc_bridge;
982 int64_t apic_id = x86_cpu_apic_id_from_index(id);
983
984 if (id < 0) {
985 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
986 return;
987 }
988
989 if (cpu_exists(apic_id)) {
990 error_setg(errp, "Unable to add CPU: %" PRIi64
991 ", it already exists", id);
992 return;
993 }
994
995 if (id >= max_cpus) {
996 error_setg(errp, "Unable to add CPU: %" PRIi64
997 ", max allowed: %d", id, max_cpus - 1);
998 return;
999 }
1000
1001 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1002 error_setg(errp, "Unable to add CPU: %" PRIi64
1003 ", resulting APIC ID (%" PRIi64 ") is too large",
1004 id, apic_id);
1005 return;
1006 }
1007
1008 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
1009 TYPE_ICC_BRIDGE, NULL));
1010 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
1011 }
1012
1013 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1014 {
1015 int i;
1016 X86CPU *cpu = NULL;
1017 Error *error = NULL;
1018 unsigned long apic_id_limit;
1019
1020 /* init CPUs */
1021 if (cpu_model == NULL) {
1022 #ifdef TARGET_X86_64
1023 cpu_model = "qemu64";
1024 #else
1025 cpu_model = "qemu32";
1026 #endif
1027 }
1028 current_cpu_model = cpu_model;
1029
1030 apic_id_limit = pc_apic_id_limit(max_cpus);
1031 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1032 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1033 apic_id_limit - 1);
1034 exit(1);
1035 }
1036
1037 for (i = 0; i < smp_cpus; i++) {
1038 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1039 icc_bridge, &error);
1040 if (error) {
1041 error_report("%s", error_get_pretty(error));
1042 error_free(error);
1043 exit(1);
1044 }
1045 }
1046
1047 /* map APIC MMIO area if CPU has APIC */
1048 if (cpu && cpu->apic_state) {
1049 /* XXX: what if the base changes? */
1050 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1051 APIC_DEFAULT_ADDRESS, 0x1000);
1052 }
1053
1054 /* tell smbios about cpuid version and features */
1055 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1056 }
1057
1058 /* pci-info ROM file. Little endian format */
1059 typedef struct PcRomPciInfo {
1060 uint64_t w32_min;
1061 uint64_t w32_max;
1062 uint64_t w64_min;
1063 uint64_t w64_max;
1064 } PcRomPciInfo;
1065
1066 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1067 {
1068 PcRomPciInfo *info;
1069 Object *pci_info;
1070 bool ambiguous = false;
1071
1072 if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1073 return;
1074 }
1075 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1076 g_assert(!ambiguous);
1077 if (!pci_info) {
1078 return;
1079 }
1080
1081 info = g_malloc(sizeof *info);
1082 info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
1083 PCI_HOST_PROP_PCI_HOLE_START, NULL));
1084 info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
1085 PCI_HOST_PROP_PCI_HOLE_END, NULL));
1086 info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
1087 PCI_HOST_PROP_PCI_HOLE64_START, NULL));
1088 info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
1089 PCI_HOST_PROP_PCI_HOLE64_END, NULL));
1090 /* Pass PCI hole info to guest via a side channel.
1091 * Required so guest PCI enumeration does the right thing. */
1092 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1093 }
1094
1095 typedef struct PcGuestInfoState {
1096 PcGuestInfo info;
1097 Notifier machine_done;
1098 } PcGuestInfoState;
1099
1100 static
1101 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1102 {
1103 PcGuestInfoState *guest_info_state = container_of(notifier,
1104 PcGuestInfoState,
1105 machine_done);
1106 pc_fw_cfg_guest_info(&guest_info_state->info);
1107 acpi_setup(&guest_info_state->info);
1108 }
1109
1110 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1111 ram_addr_t above_4g_mem_size)
1112 {
1113 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1114 PcGuestInfo *guest_info = &guest_info_state->info;
1115 int i, j;
1116
1117 guest_info->ram_size_below_4g = below_4g_mem_size;
1118 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1119 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1120 guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1121 guest_info->numa_nodes = nb_numa_nodes;
1122 guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
1123 sizeof *guest_info->node_mem);
1124 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1125 sizeof *guest_info->node_cpu);
1126
1127 for (i = 0; i < max_cpus; i++) {
1128 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1129 assert(apic_id < guest_info->apic_id_limit);
1130 for (j = 0; j < nb_numa_nodes; j++) {
1131 if (test_bit(i, node_cpumask[j])) {
1132 guest_info->node_cpu[apic_id] = j;
1133 break;
1134 }
1135 }
1136 }
1137
1138 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1139 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1140 return guest_info;
1141 }
1142
1143 /* setup pci memory address space mapping into system address space */
1144 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1145 MemoryRegion *pci_address_space)
1146 {
1147 /* Set to lower priority than RAM */
1148 memory_region_add_subregion_overlap(system_memory, 0x0,
1149 pci_address_space, -1);
1150 }
1151
1152 void pc_acpi_init(const char *default_dsdt)
1153 {
1154 char *filename;
1155
1156 if (acpi_tables != NULL) {
1157 /* manually set via -acpitable, leave it alone */
1158 return;
1159 }
1160
1161 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1162 if (filename == NULL) {
1163 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1164 } else {
1165 char *arg;
1166 QemuOpts *opts;
1167 Error *err = NULL;
1168
1169 arg = g_strdup_printf("file=%s", filename);
1170
1171 /* creates a deep copy of "arg" */
1172 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1173 g_assert(opts != NULL);
1174
1175 acpi_table_add_builtin(opts, &err);
1176 if (err) {
1177 error_report("WARNING: failed to load %s: %s", filename,
1178 error_get_pretty(err));
1179 error_free(err);
1180 }
1181 g_free(arg);
1182 g_free(filename);
1183 }
1184 }
1185
1186 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1187 const char *kernel_filename,
1188 const char *kernel_cmdline,
1189 const char *initrd_filename,
1190 ram_addr_t below_4g_mem_size,
1191 ram_addr_t above_4g_mem_size,
1192 MemoryRegion *rom_memory,
1193 MemoryRegion **ram_memory,
1194 PcGuestInfo *guest_info)
1195 {
1196 int linux_boot, i;
1197 MemoryRegion *ram, *option_rom_mr;
1198 MemoryRegion *ram_below_4g, *ram_above_4g;
1199 FWCfgState *fw_cfg;
1200 ram_addr_t ram_size = below_4g_mem_size + above_4g_mem_size;
1201 MachineState *machine = MACHINE(qdev_get_machine());
1202 PCMachineState *pcms = PC_MACHINE(machine);
1203
1204 linux_boot = (kernel_filename != NULL);
1205
1206 /* Allocate RAM. We allocate it as a single memory region and use
1207 * aliases to address portions of it, mostly for backwards compatibility
1208 * with older qemus that used qemu_ram_alloc().
1209 */
1210 ram = g_malloc(sizeof(*ram));
1211 memory_region_init_ram(ram, NULL, "pc.ram", ram_size);
1212 vmstate_register_ram_global(ram);
1213 *ram_memory = ram;
1214 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1215 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1216 0, below_4g_mem_size);
1217 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1218 e820_add_entry(0, below_4g_mem_size, E820_RAM);
1219 if (above_4g_mem_size > 0) {
1220 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1221 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1222 below_4g_mem_size, above_4g_mem_size);
1223 memory_region_add_subregion(system_memory, 0x100000000ULL,
1224 ram_above_4g);
1225 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1226 }
1227
1228 /* initialize hotplug memory address space */
1229 if (ram_size < machine->maxram_size) {
1230 ram_addr_t hotplug_mem_size =
1231 machine->maxram_size - ram_size;
1232
1233 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1234 error_report("unsupported amount of memory slots: %"PRIu64,
1235 machine->ram_slots);
1236 exit(EXIT_FAILURE);
1237 }
1238
1239 pcms->hotplug_memory_base =
1240 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
1241
1242 if ((pcms->hotplug_memory_base + hotplug_mem_size) <
1243 hotplug_mem_size) {
1244 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1245 machine->maxram_size);
1246 exit(EXIT_FAILURE);
1247 }
1248
1249 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms),
1250 "hotplug-memory", hotplug_mem_size);
1251 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base,
1252 &pcms->hotplug_memory);
1253 }
1254
1255 /* Initialize PC system firmware */
1256 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1257
1258 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1259 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1260 vmstate_register_ram_global(option_rom_mr);
1261 memory_region_add_subregion_overlap(rom_memory,
1262 PC_ROM_MIN_VGA,
1263 option_rom_mr,
1264 1);
1265
1266 fw_cfg = bochs_bios_init();
1267 rom_set_fw(fw_cfg);
1268
1269 if (linux_boot) {
1270 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1271 }
1272
1273 for (i = 0; i < nb_option_roms; i++) {
1274 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1275 }
1276 guest_info->fw_cfg = fw_cfg;
1277 return fw_cfg;
1278 }
1279
1280 qemu_irq *pc_allocate_cpu_irq(void)
1281 {
1282 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1283 }
1284
1285 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1286 {
1287 DeviceState *dev = NULL;
1288
1289 if (pci_bus) {
1290 PCIDevice *pcidev = pci_vga_init(pci_bus);
1291 dev = pcidev ? &pcidev->qdev : NULL;
1292 } else if (isa_bus) {
1293 ISADevice *isadev = isa_vga_init(isa_bus);
1294 dev = isadev ? DEVICE(isadev) : NULL;
1295 }
1296 return dev;
1297 }
1298
1299 static void cpu_request_exit(void *opaque, int irq, int level)
1300 {
1301 CPUState *cpu = current_cpu;
1302
1303 if (cpu && level) {
1304 cpu_exit(cpu);
1305 }
1306 }
1307
1308 static const MemoryRegionOps ioport80_io_ops = {
1309 .write = ioport80_write,
1310 .read = ioport80_read,
1311 .endianness = DEVICE_NATIVE_ENDIAN,
1312 .impl = {
1313 .min_access_size = 1,
1314 .max_access_size = 1,
1315 },
1316 };
1317
1318 static const MemoryRegionOps ioportF0_io_ops = {
1319 .write = ioportF0_write,
1320 .read = ioportF0_read,
1321 .endianness = DEVICE_NATIVE_ENDIAN,
1322 .impl = {
1323 .min_access_size = 1,
1324 .max_access_size = 1,
1325 },
1326 };
1327
1328 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1329 ISADevice **rtc_state,
1330 ISADevice **floppy,
1331 bool no_vmport,
1332 uint32 hpet_irqs)
1333 {
1334 int i;
1335 DriveInfo *fd[MAX_FD];
1336 DeviceState *hpet = NULL;
1337 int pit_isa_irq = 0;
1338 qemu_irq pit_alt_irq = NULL;
1339 qemu_irq rtc_irq = NULL;
1340 qemu_irq *a20_line;
1341 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1342 qemu_irq *cpu_exit_irq;
1343 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1344 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1345
1346 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1347 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1348
1349 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1350 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1351
1352 /*
1353 * Check if an HPET shall be created.
1354 *
1355 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1356 * when the HPET wants to take over. Thus we have to disable the latter.
1357 */
1358 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1359 /* In order to set property, here not using sysbus_try_create_simple */
1360 hpet = qdev_try_create(NULL, TYPE_HPET);
1361 if (hpet) {
1362 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1363 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1364 * IRQ8 and IRQ2.
1365 */
1366 uint8_t compat = object_property_get_int(OBJECT(hpet),
1367 HPET_INTCAP, NULL);
1368 if (!compat) {
1369 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1370 }
1371 qdev_init_nofail(hpet);
1372 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1373
1374 for (i = 0; i < GSI_NUM_PINS; i++) {
1375 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1376 }
1377 pit_isa_irq = -1;
1378 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1379 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1380 }
1381 }
1382 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1383
1384 qemu_register_boot_set(pc_boot_set, *rtc_state);
1385
1386 if (!xen_enabled()) {
1387 if (kvm_irqchip_in_kernel()) {
1388 pit = kvm_pit_init(isa_bus, 0x40);
1389 } else {
1390 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1391 }
1392 if (hpet) {
1393 /* connect PIT to output control line of the HPET */
1394 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1395 }
1396 pcspk_init(isa_bus, pit);
1397 }
1398
1399 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1400 if (serial_hds[i]) {
1401 serial_isa_init(isa_bus, i, serial_hds[i]);
1402 }
1403 }
1404
1405 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1406 if (parallel_hds[i]) {
1407 parallel_init(isa_bus, i, parallel_hds[i]);
1408 }
1409 }
1410
1411 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1412 i8042 = isa_create_simple(isa_bus, "i8042");
1413 i8042_setup_a20_line(i8042, &a20_line[0]);
1414 if (!no_vmport) {
1415 vmport_init(isa_bus);
1416 vmmouse = isa_try_create(isa_bus, "vmmouse");
1417 } else {
1418 vmmouse = NULL;
1419 }
1420 if (vmmouse) {
1421 DeviceState *dev = DEVICE(vmmouse);
1422 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1423 qdev_init_nofail(dev);
1424 }
1425 port92 = isa_create_simple(isa_bus, "port92");
1426 port92_init(port92, &a20_line[1]);
1427
1428 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1429 DMA_init(0, cpu_exit_irq);
1430
1431 for(i = 0; i < MAX_FD; i++) {
1432 fd[i] = drive_get(IF_FLOPPY, 0, i);
1433 }
1434 *floppy = fdctrl_init_isa(isa_bus, fd);
1435 }
1436
1437 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1438 {
1439 int i;
1440
1441 for (i = 0; i < nb_nics; i++) {
1442 NICInfo *nd = &nd_table[i];
1443
1444 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1445 pc_init_ne2k_isa(isa_bus, nd);
1446 } else {
1447 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1448 }
1449 }
1450 }
1451
1452 void pc_pci_device_init(PCIBus *pci_bus)
1453 {
1454 int max_bus;
1455 int bus;
1456
1457 max_bus = drive_get_max_bus(IF_SCSI);
1458 for (bus = 0; bus <= max_bus; bus++) {
1459 pci_create_simple(pci_bus, -1, "lsi53c895a");
1460 }
1461 }
1462
1463 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1464 {
1465 DeviceState *dev;
1466 SysBusDevice *d;
1467 unsigned int i;
1468
1469 if (kvm_irqchip_in_kernel()) {
1470 dev = qdev_create(NULL, "kvm-ioapic");
1471 } else {
1472 dev = qdev_create(NULL, "ioapic");
1473 }
1474 if (parent_name) {
1475 object_property_add_child(object_resolve_path(parent_name, NULL),
1476 "ioapic", OBJECT(dev), NULL);
1477 }
1478 qdev_init_nofail(dev);
1479 d = SYS_BUS_DEVICE(dev);
1480 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1481
1482 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1483 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1484 }
1485 }
1486
1487 static void pc_generic_machine_class_init(ObjectClass *oc, void *data)
1488 {
1489 MachineClass *mc = MACHINE_CLASS(oc);
1490 QEMUMachine *qm = data;
1491
1492 mc->name = qm->name;
1493 mc->alias = qm->alias;
1494 mc->desc = qm->desc;
1495 mc->init = qm->init;
1496 mc->reset = qm->reset;
1497 mc->hot_add_cpu = qm->hot_add_cpu;
1498 mc->kvm_type = qm->kvm_type;
1499 mc->block_default_type = qm->block_default_type;
1500 mc->max_cpus = qm->max_cpus;
1501 mc->no_serial = qm->no_serial;
1502 mc->no_parallel = qm->no_parallel;
1503 mc->use_virtcon = qm->use_virtcon;
1504 mc->use_sclp = qm->use_sclp;
1505 mc->no_floppy = qm->no_floppy;
1506 mc->no_cdrom = qm->no_cdrom;
1507 mc->no_sdcard = qm->no_sdcard;
1508 mc->is_default = qm->is_default;
1509 mc->default_machine_opts = qm->default_machine_opts;
1510 mc->default_boot_order = qm->default_boot_order;
1511 mc->compat_props = qm->compat_props;
1512 mc->hw_version = qm->hw_version;
1513 }
1514
1515 void qemu_register_pc_machine(QEMUMachine *m)
1516 {
1517 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL);
1518 TypeInfo ti = {
1519 .name = name,
1520 .parent = TYPE_PC_MACHINE,
1521 .class_init = pc_generic_machine_class_init,
1522 .class_data = (void *)m,
1523 };
1524
1525 type_register(&ti);
1526 g_free(name);
1527 }
1528
1529 static const TypeInfo pc_machine_info = {
1530 .name = TYPE_PC_MACHINE,
1531 .parent = TYPE_MACHINE,
1532 .abstract = true,
1533 .instance_size = sizeof(PCMachineState),
1534 .class_size = sizeof(PCMachineClass),
1535 };
1536
1537 static void pc_machine_register_types(void)
1538 {
1539 type_register_static(&pc_machine_info);
1540 }
1541
1542 type_init(pc_machine_register_types)