hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/qtest.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "exec/address-spaces.h"
70 #include "sysemu/arch_init.h"
71 #include "qemu/bitmap.h"
72 #include "qemu/config-file.h"
73 #include "qemu/error-report.h"
74 #include "qemu/option.h"
75 #include "qemu/cutils.h"
76 #include "hw/acpi/acpi.h"
77 #include "hw/acpi/cpu_hotplug.h"
78 #include "hw/boards.h"
79 #include "acpi-build.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "qapi/error.h"
83 #include "qapi/qapi-visit-common.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-pmem-pci.h"
91 #include "hw/virtio/virtio-mem-pci.h"
92 #include "hw/mem/memory-device.h"
93 #include "sysemu/replay.h"
94 #include "qapi/qmp/qerror.h"
95 #include "e820_memory_layout.h"
96 #include "fw_cfg.h"
97 #include "trace.h"
98 #include CONFIG_DEVICES
99
100 GlobalProperty pc_compat_5_1[] = {
101 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
102 };
103 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
104
105 GlobalProperty pc_compat_5_0[] = {
106 };
107 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
108
109 GlobalProperty pc_compat_4_2[] = {
110 { "mch", "smbase-smram", "off" },
111 };
112 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
113
114 GlobalProperty pc_compat_4_1[] = {};
115 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
116
117 GlobalProperty pc_compat_4_0[] = {};
118 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
119
120 GlobalProperty pc_compat_3_1[] = {
121 { "intel-iommu", "dma-drain", "off" },
122 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
123 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
124 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
125 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
126 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
127 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
128 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
129 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
130 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
131 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
132 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
133 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
134 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
135 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
136 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
137 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
138 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
139 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
140 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
141 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
142 };
143 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
144
145 GlobalProperty pc_compat_3_0[] = {
146 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
147 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
148 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
149 };
150 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
151
152 GlobalProperty pc_compat_2_12[] = {
153 { TYPE_X86_CPU, "legacy-cache", "on" },
154 { TYPE_X86_CPU, "topoext", "off" },
155 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
156 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
157 };
158 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
159
160 GlobalProperty pc_compat_2_11[] = {
161 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
162 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
163 };
164 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
165
166 GlobalProperty pc_compat_2_10[] = {
167 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
168 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
169 { "q35-pcihost", "x-pci-hole64-fix", "off" },
170 };
171 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
172
173 GlobalProperty pc_compat_2_9[] = {
174 { "mch", "extended-tseg-mbytes", "0" },
175 };
176 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
177
178 GlobalProperty pc_compat_2_8[] = {
179 { TYPE_X86_CPU, "tcg-cpuid", "off" },
180 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
181 { "ICH9-LPC", "x-smi-broadcast", "off" },
182 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
183 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
184 };
185 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
186
187 GlobalProperty pc_compat_2_7[] = {
188 { TYPE_X86_CPU, "l3-cache", "off" },
189 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
190 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
191 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
192 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
193 { "isa-pcspk", "migrate", "off" },
194 };
195 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
196
197 GlobalProperty pc_compat_2_6[] = {
198 { TYPE_X86_CPU, "cpuid-0xb", "off" },
199 { "vmxnet3", "romfile", "" },
200 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
201 { "apic-common", "legacy-instance-id", "on", }
202 };
203 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
204
205 GlobalProperty pc_compat_2_5[] = {};
206 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
207
208 GlobalProperty pc_compat_2_4[] = {
209 PC_CPU_MODEL_IDS("2.4.0")
210 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
211 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
212 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
213 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
214 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
215 { TYPE_X86_CPU, "check", "off" },
216 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
217 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
218 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
219 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
220 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
221 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
222 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
223 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
224 };
225 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
226
227 GlobalProperty pc_compat_2_3[] = {
228 PC_CPU_MODEL_IDS("2.3.0")
229 { TYPE_X86_CPU, "arat", "off" },
230 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
231 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
232 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
233 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
234 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
235 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
236 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
237 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
242 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
243 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
244 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
245 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
247 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
249 };
250 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
251
252 GlobalProperty pc_compat_2_2[] = {
253 PC_CPU_MODEL_IDS("2.2.0")
254 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
255 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
260 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
262 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
263 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
265 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
268 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
269 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
270 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
271 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
272 };
273 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
274
275 GlobalProperty pc_compat_2_1[] = {
276 PC_CPU_MODEL_IDS("2.1.0")
277 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
278 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
279 };
280 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
281
282 GlobalProperty pc_compat_2_0[] = {
283 PC_CPU_MODEL_IDS("2.0.0")
284 { "virtio-scsi-pci", "any_layout", "off" },
285 { "PIIX4_PM", "memory-hotplug-support", "off" },
286 { "apic", "version", "0x11" },
287 { "nec-usb-xhci", "superspeed-ports-first", "off" },
288 { "nec-usb-xhci", "force-pcie-endcap", "on" },
289 { "pci-serial", "prog_if", "0" },
290 { "pci-serial-2x", "prog_if", "0" },
291 { "pci-serial-4x", "prog_if", "0" },
292 { "virtio-net-pci", "guest_announce", "off" },
293 { "ICH9-LPC", "memory-hotplug-support", "off" },
294 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
295 { "ioh3420", COMPAT_PROP_PCP, "off" },
296 };
297 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
298
299 GlobalProperty pc_compat_1_7[] = {
300 PC_CPU_MODEL_IDS("1.7.0")
301 { TYPE_USB_DEVICE, "msos-desc", "no" },
302 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
303 { "hpet", HPET_INTCAP, "4" },
304 };
305 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
306
307 GlobalProperty pc_compat_1_6[] = {
308 PC_CPU_MODEL_IDS("1.6.0")
309 { "e1000", "mitigation", "off" },
310 { "qemu64-" TYPE_X86_CPU, "model", "2" },
311 { "qemu32-" TYPE_X86_CPU, "model", "3" },
312 { "i440FX-pcihost", "short_root_bus", "1" },
313 { "q35-pcihost", "short_root_bus", "1" },
314 };
315 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
316
317 GlobalProperty pc_compat_1_5[] = {
318 PC_CPU_MODEL_IDS("1.5.0")
319 { "Conroe-" TYPE_X86_CPU, "model", "2" },
320 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
321 { "Penryn-" TYPE_X86_CPU, "model", "2" },
322 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
323 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
324 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
325 { "virtio-net-pci", "any_layout", "off" },
326 { TYPE_X86_CPU, "pmu", "on" },
327 { "i440FX-pcihost", "short_root_bus", "0" },
328 { "q35-pcihost", "short_root_bus", "0" },
329 };
330 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
331
332 GlobalProperty pc_compat_1_4[] = {
333 PC_CPU_MODEL_IDS("1.4.0")
334 { "scsi-hd", "discard_granularity", "0" },
335 { "scsi-cd", "discard_granularity", "0" },
336 { "scsi-disk", "discard_granularity", "0" },
337 { "ide-hd", "discard_granularity", "0" },
338 { "ide-cd", "discard_granularity", "0" },
339 { "ide-drive", "discard_granularity", "0" },
340 { "virtio-blk-pci", "discard_granularity", "0" },
341 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
342 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
343 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
344 { "e1000", "romfile", "pxe-e1000.rom" },
345 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
346 { "pcnet", "romfile", "pxe-pcnet.rom" },
347 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
348 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
349 { "486-" TYPE_X86_CPU, "model", "0" },
350 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
351 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
352 };
353 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
354
355 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
356 {
357 GSIState *s;
358
359 s = g_new0(GSIState, 1);
360 if (kvm_ioapic_in_kernel()) {
361 kvm_pc_setup_irq_routing(pci_enabled);
362 }
363 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
364
365 return s;
366 }
367
368 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
369 unsigned size)
370 {
371 }
372
373 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
374 {
375 return 0xffffffffffffffffULL;
376 }
377
378 /* MSDOS compatibility mode FPU exception support */
379 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
380 unsigned size)
381 {
382 if (tcg_enabled()) {
383 cpu_set_ignne();
384 }
385 }
386
387 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
388 {
389 return 0xffffffffffffffffULL;
390 }
391
392 /* PC cmos mappings */
393
394 #define REG_EQUIPMENT_BYTE 0x14
395
396 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
397 int16_t cylinders, int8_t heads, int8_t sectors)
398 {
399 rtc_set_memory(s, type_ofs, 47);
400 rtc_set_memory(s, info_ofs, cylinders);
401 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
402 rtc_set_memory(s, info_ofs + 2, heads);
403 rtc_set_memory(s, info_ofs + 3, 0xff);
404 rtc_set_memory(s, info_ofs + 4, 0xff);
405 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
406 rtc_set_memory(s, info_ofs + 6, cylinders);
407 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
408 rtc_set_memory(s, info_ofs + 8, sectors);
409 }
410
411 /* convert boot_device letter to something recognizable by the bios */
412 static int boot_device2nibble(char boot_device)
413 {
414 switch(boot_device) {
415 case 'a':
416 case 'b':
417 return 0x01; /* floppy boot */
418 case 'c':
419 return 0x02; /* hard drive boot */
420 case 'd':
421 return 0x03; /* CD-ROM boot */
422 case 'n':
423 return 0x04; /* Network boot */
424 }
425 return 0;
426 }
427
428 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
429 {
430 #define PC_MAX_BOOT_DEVICES 3
431 int nbds, bds[3] = { 0, };
432 int i;
433
434 nbds = strlen(boot_device);
435 if (nbds > PC_MAX_BOOT_DEVICES) {
436 error_setg(errp, "Too many boot devices for PC");
437 return;
438 }
439 for (i = 0; i < nbds; i++) {
440 bds[i] = boot_device2nibble(boot_device[i]);
441 if (bds[i] == 0) {
442 error_setg(errp, "Invalid boot device for PC: '%c'",
443 boot_device[i]);
444 return;
445 }
446 }
447 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
448 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
449 }
450
451 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
452 {
453 set_boot_dev(opaque, boot_device, errp);
454 }
455
456 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
457 {
458 int val, nb, i;
459 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
460 FLOPPY_DRIVE_TYPE_NONE };
461
462 /* floppy type */
463 if (floppy) {
464 for (i = 0; i < 2; i++) {
465 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
466 }
467 }
468 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
469 cmos_get_fd_drive_type(fd_type[1]);
470 rtc_set_memory(rtc_state, 0x10, val);
471
472 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
473 nb = 0;
474 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
475 nb++;
476 }
477 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
478 nb++;
479 }
480 switch (nb) {
481 case 0:
482 break;
483 case 1:
484 val |= 0x01; /* 1 drive, ready for boot */
485 break;
486 case 2:
487 val |= 0x41; /* 2 drives, ready for boot */
488 break;
489 }
490 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
491 }
492
493 typedef struct pc_cmos_init_late_arg {
494 ISADevice *rtc_state;
495 BusState *idebus[2];
496 } pc_cmos_init_late_arg;
497
498 typedef struct check_fdc_state {
499 ISADevice *floppy;
500 bool multiple;
501 } CheckFdcState;
502
503 static int check_fdc(Object *obj, void *opaque)
504 {
505 CheckFdcState *state = opaque;
506 Object *fdc;
507 uint32_t iobase;
508 Error *local_err = NULL;
509
510 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
511 if (!fdc) {
512 return 0;
513 }
514
515 iobase = object_property_get_uint(obj, "iobase", &local_err);
516 if (local_err || iobase != 0x3f0) {
517 error_free(local_err);
518 return 0;
519 }
520
521 if (state->floppy) {
522 state->multiple = true;
523 } else {
524 state->floppy = ISA_DEVICE(obj);
525 }
526 return 0;
527 }
528
529 static const char * const fdc_container_path[] = {
530 "/unattached", "/peripheral", "/peripheral-anon"
531 };
532
533 /*
534 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
535 * and ACPI objects.
536 */
537 ISADevice *pc_find_fdc0(void)
538 {
539 int i;
540 Object *container;
541 CheckFdcState state = { 0 };
542
543 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
544 container = container_get(qdev_get_machine(), fdc_container_path[i]);
545 object_child_foreach(container, check_fdc, &state);
546 }
547
548 if (state.multiple) {
549 warn_report("multiple floppy disk controllers with "
550 "iobase=0x3f0 have been found");
551 error_printf("the one being picked for CMOS setup might not reflect "
552 "your intent");
553 }
554
555 return state.floppy;
556 }
557
558 static void pc_cmos_init_late(void *opaque)
559 {
560 pc_cmos_init_late_arg *arg = opaque;
561 ISADevice *s = arg->rtc_state;
562 int16_t cylinders;
563 int8_t heads, sectors;
564 int val;
565 int i, trans;
566
567 val = 0;
568 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
569 &cylinders, &heads, &sectors) >= 0) {
570 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
571 val |= 0xf0;
572 }
573 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
574 &cylinders, &heads, &sectors) >= 0) {
575 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
576 val |= 0x0f;
577 }
578 rtc_set_memory(s, 0x12, val);
579
580 val = 0;
581 for (i = 0; i < 4; i++) {
582 /* NOTE: ide_get_geometry() returns the physical
583 geometry. It is always such that: 1 <= sects <= 63, 1
584 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
585 geometry can be different if a translation is done. */
586 if (arg->idebus[i / 2] &&
587 ide_get_geometry(arg->idebus[i / 2], i % 2,
588 &cylinders, &heads, &sectors) >= 0) {
589 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
590 assert((trans & ~3) == 0);
591 val |= trans << (i * 2);
592 }
593 }
594 rtc_set_memory(s, 0x39, val);
595
596 pc_cmos_init_floppy(s, pc_find_fdc0());
597
598 qemu_unregister_reset(pc_cmos_init_late, opaque);
599 }
600
601 void pc_cmos_init(PCMachineState *pcms,
602 BusState *idebus0, BusState *idebus1,
603 ISADevice *s)
604 {
605 int val;
606 static pc_cmos_init_late_arg arg;
607 X86MachineState *x86ms = X86_MACHINE(pcms);
608
609 /* various important CMOS locations needed by PC/Bochs bios */
610
611 /* memory size */
612 /* base memory (first MiB) */
613 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
614 rtc_set_memory(s, 0x15, val);
615 rtc_set_memory(s, 0x16, val >> 8);
616 /* extended memory (next 64MiB) */
617 if (x86ms->below_4g_mem_size > 1 * MiB) {
618 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
619 } else {
620 val = 0;
621 }
622 if (val > 65535)
623 val = 65535;
624 rtc_set_memory(s, 0x17, val);
625 rtc_set_memory(s, 0x18, val >> 8);
626 rtc_set_memory(s, 0x30, val);
627 rtc_set_memory(s, 0x31, val >> 8);
628 /* memory between 16MiB and 4GiB */
629 if (x86ms->below_4g_mem_size > 16 * MiB) {
630 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
631 } else {
632 val = 0;
633 }
634 if (val > 65535)
635 val = 65535;
636 rtc_set_memory(s, 0x34, val);
637 rtc_set_memory(s, 0x35, val >> 8);
638 /* memory above 4GiB */
639 val = x86ms->above_4g_mem_size / 65536;
640 rtc_set_memory(s, 0x5b, val);
641 rtc_set_memory(s, 0x5c, val >> 8);
642 rtc_set_memory(s, 0x5d, val >> 16);
643
644 object_property_add_link(OBJECT(pcms), "rtc_state",
645 TYPE_ISA_DEVICE,
646 (Object **)&x86ms->rtc,
647 object_property_allow_set_link,
648 OBJ_PROP_LINK_STRONG);
649 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
650 &error_abort);
651
652 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
653
654 val = 0;
655 val |= 0x02; /* FPU is there */
656 val |= 0x04; /* PS/2 mouse installed */
657 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
658
659 /* hard drives and FDC */
660 arg.rtc_state = s;
661 arg.idebus[0] = idebus0;
662 arg.idebus[1] = idebus1;
663 qemu_register_reset(pc_cmos_init_late, &arg);
664 }
665
666 static void handle_a20_line_change(void *opaque, int irq, int level)
667 {
668 X86CPU *cpu = opaque;
669
670 /* XXX: send to all CPUs ? */
671 /* XXX: add logic to handle multiple A20 line sources */
672 x86_cpu_set_a20(cpu, level);
673 }
674
675 #define NE2000_NB_MAX 6
676
677 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
678 0x280, 0x380 };
679 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
680
681 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
682 {
683 static int nb_ne2k = 0;
684
685 if (nb_ne2k == NE2000_NB_MAX)
686 return;
687 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
688 ne2000_irq[nb_ne2k], nd);
689 nb_ne2k++;
690 }
691
692 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
693 {
694 X86CPU *cpu = opaque;
695
696 if (level) {
697 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
698 }
699 }
700
701 /*
702 * This function is very similar to smp_parse()
703 * in hw/core/machine.c but includes CPU die support.
704 */
705 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
706 {
707 X86MachineState *x86ms = X86_MACHINE(ms);
708
709 if (opts) {
710 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
711 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
712 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
713 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
714 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
715
716 /* compute missing values, prefer sockets over cores over threads */
717 if (cpus == 0 || sockets == 0) {
718 cores = cores > 0 ? cores : 1;
719 threads = threads > 0 ? threads : 1;
720 if (cpus == 0) {
721 sockets = sockets > 0 ? sockets : 1;
722 cpus = cores * threads * dies * sockets;
723 } else {
724 ms->smp.max_cpus =
725 qemu_opt_get_number(opts, "maxcpus", cpus);
726 sockets = ms->smp.max_cpus / (cores * threads * dies);
727 }
728 } else if (cores == 0) {
729 threads = threads > 0 ? threads : 1;
730 cores = cpus / (sockets * dies * threads);
731 cores = cores > 0 ? cores : 1;
732 } else if (threads == 0) {
733 threads = cpus / (cores * dies * sockets);
734 threads = threads > 0 ? threads : 1;
735 } else if (sockets * dies * cores * threads < cpus) {
736 error_report("cpu topology: "
737 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
738 "smp_cpus (%u)",
739 sockets, dies, cores, threads, cpus);
740 exit(1);
741 }
742
743 ms->smp.max_cpus =
744 qemu_opt_get_number(opts, "maxcpus", cpus);
745
746 if (ms->smp.max_cpus < cpus) {
747 error_report("maxcpus must be equal to or greater than smp");
748 exit(1);
749 }
750
751 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
752 error_report("Invalid CPU topology deprecated: "
753 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
754 "!= maxcpus (%u)",
755 sockets, dies, cores, threads,
756 ms->smp.max_cpus);
757 exit(1);
758 }
759
760 ms->smp.cpus = cpus;
761 ms->smp.cores = cores;
762 ms->smp.threads = threads;
763 ms->smp.sockets = sockets;
764 x86ms->smp_dies = dies;
765 }
766
767 if (ms->smp.cpus > 1) {
768 Error *blocker = NULL;
769 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
770 replay_add_blocker(blocker);
771 }
772 }
773
774 static
775 void pc_machine_done(Notifier *notifier, void *data)
776 {
777 PCMachineState *pcms = container_of(notifier,
778 PCMachineState, machine_done);
779 X86MachineState *x86ms = X86_MACHINE(pcms);
780 PCIBus *bus = pcms->bus;
781
782 /* set the number of CPUs */
783 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
784
785 if (bus) {
786 int extra_hosts = 0;
787
788 QLIST_FOREACH(bus, &bus->child, sibling) {
789 /* look for expander root buses */
790 if (pci_bus_is_root(bus)) {
791 extra_hosts++;
792 }
793 }
794 if (extra_hosts && x86ms->fw_cfg) {
795 uint64_t *val = g_malloc(sizeof(*val));
796 *val = cpu_to_le64(extra_hosts);
797 fw_cfg_add_file(x86ms->fw_cfg,
798 "etc/extra-pci-roots", val, sizeof(*val));
799 }
800 }
801
802 acpi_setup();
803 if (x86ms->fw_cfg) {
804 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
805 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
806 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
807 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
808 }
809
810 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
811 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
812
813 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
814 iommu->intr_eim != ON_OFF_AUTO_ON) {
815 error_report("current -smp configuration requires "
816 "Extended Interrupt Mode enabled. "
817 "You can add an IOMMU using: "
818 "-device intel-iommu,intremap=on,eim=on");
819 exit(EXIT_FAILURE);
820 }
821 }
822 }
823
824 void pc_guest_info_init(PCMachineState *pcms)
825 {
826 int i;
827 MachineState *ms = MACHINE(pcms);
828 X86MachineState *x86ms = X86_MACHINE(pcms);
829
830 x86ms->apic_xrupt_override = true;
831 pcms->numa_nodes = ms->numa_state->num_nodes;
832 pcms->node_mem = g_malloc0(pcms->numa_nodes *
833 sizeof *pcms->node_mem);
834 for (i = 0; i < ms->numa_state->num_nodes; i++) {
835 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
836 }
837
838 pcms->machine_done.notify = pc_machine_done;
839 qemu_add_machine_init_done_notifier(&pcms->machine_done);
840 }
841
842 /* setup pci memory address space mapping into system address space */
843 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
844 MemoryRegion *pci_address_space)
845 {
846 /* Set to lower priority than RAM */
847 memory_region_add_subregion_overlap(system_memory, 0x0,
848 pci_address_space, -1);
849 }
850
851 void xen_load_linux(PCMachineState *pcms)
852 {
853 int i;
854 FWCfgState *fw_cfg;
855 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
856 X86MachineState *x86ms = X86_MACHINE(pcms);
857
858 assert(MACHINE(pcms)->kernel_filename != NULL);
859
860 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
861 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
862 rom_set_fw(fw_cfg);
863
864 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
865 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
866 for (i = 0; i < nb_option_roms; i++) {
867 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
868 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
869 !strcmp(option_rom[i].name, "pvh.bin") ||
870 !strcmp(option_rom[i].name, "multiboot.bin"));
871 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
872 }
873 x86ms->fw_cfg = fw_cfg;
874 }
875
876 void pc_memory_init(PCMachineState *pcms,
877 MemoryRegion *system_memory,
878 MemoryRegion *rom_memory,
879 MemoryRegion **ram_memory)
880 {
881 int linux_boot, i;
882 MemoryRegion *option_rom_mr;
883 MemoryRegion *ram_below_4g, *ram_above_4g;
884 FWCfgState *fw_cfg;
885 MachineState *machine = MACHINE(pcms);
886 MachineClass *mc = MACHINE_GET_CLASS(machine);
887 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
888 X86MachineState *x86ms = X86_MACHINE(pcms);
889
890 assert(machine->ram_size == x86ms->below_4g_mem_size +
891 x86ms->above_4g_mem_size);
892
893 linux_boot = (machine->kernel_filename != NULL);
894
895 /*
896 * Split single memory region and use aliases to address portions of it,
897 * done for backwards compatibility with older qemus.
898 */
899 *ram_memory = machine->ram;
900 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
901 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
902 0, x86ms->below_4g_mem_size);
903 memory_region_add_subregion(system_memory, 0, ram_below_4g);
904 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
905 if (x86ms->above_4g_mem_size > 0) {
906 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
907 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
908 machine->ram,
909 x86ms->below_4g_mem_size,
910 x86ms->above_4g_mem_size);
911 memory_region_add_subregion(system_memory, 0x100000000ULL,
912 ram_above_4g);
913 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
914 }
915
916 if (!pcmc->has_reserved_memory &&
917 (machine->ram_slots ||
918 (machine->maxram_size > machine->ram_size))) {
919
920 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
921 mc->name);
922 exit(EXIT_FAILURE);
923 }
924
925 /* always allocate the device memory information */
926 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
927
928 /* initialize device memory address space */
929 if (pcmc->has_reserved_memory &&
930 (machine->ram_size < machine->maxram_size)) {
931 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
932
933 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
934 error_report("unsupported amount of memory slots: %"PRIu64,
935 machine->ram_slots);
936 exit(EXIT_FAILURE);
937 }
938
939 if (QEMU_ALIGN_UP(machine->maxram_size,
940 TARGET_PAGE_SIZE) != machine->maxram_size) {
941 error_report("maximum memory size must by aligned to multiple of "
942 "%d bytes", TARGET_PAGE_SIZE);
943 exit(EXIT_FAILURE);
944 }
945
946 machine->device_memory->base =
947 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
948
949 if (pcmc->enforce_aligned_dimm) {
950 /* size device region assuming 1G page max alignment per slot */
951 device_mem_size += (1 * GiB) * machine->ram_slots;
952 }
953
954 if ((machine->device_memory->base + device_mem_size) <
955 device_mem_size) {
956 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
957 machine->maxram_size);
958 exit(EXIT_FAILURE);
959 }
960
961 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
962 "device-memory", device_mem_size);
963 memory_region_add_subregion(system_memory, machine->device_memory->base,
964 &machine->device_memory->mr);
965 }
966
967 /* Initialize PC system firmware */
968 pc_system_firmware_init(pcms, rom_memory);
969
970 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
971 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
972 &error_fatal);
973 if (pcmc->pci_enabled) {
974 memory_region_set_readonly(option_rom_mr, true);
975 }
976 memory_region_add_subregion_overlap(rom_memory,
977 PC_ROM_MIN_VGA,
978 option_rom_mr,
979 1);
980
981 fw_cfg = fw_cfg_arch_create(machine,
982 x86ms->boot_cpus, x86ms->apic_id_limit);
983
984 rom_set_fw(fw_cfg);
985
986 if (pcmc->has_reserved_memory && machine->device_memory->base) {
987 uint64_t *val = g_malloc(sizeof(*val));
988 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
989 uint64_t res_mem_end = machine->device_memory->base;
990
991 if (!pcmc->broken_reserved_end) {
992 res_mem_end += memory_region_size(&machine->device_memory->mr);
993 }
994 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
995 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
996 }
997
998 if (linux_boot) {
999 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1000 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1001 }
1002
1003 for (i = 0; i < nb_option_roms; i++) {
1004 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1005 }
1006 x86ms->fw_cfg = fw_cfg;
1007
1008 /* Init default IOAPIC address space */
1009 x86ms->ioapic_as = &address_space_memory;
1010
1011 /* Init ACPI memory hotplug IO base address */
1012 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1013 }
1014
1015 /*
1016 * The 64bit pci hole starts after "above 4G RAM" and
1017 * potentially the space reserved for memory hotplug.
1018 */
1019 uint64_t pc_pci_hole64_start(void)
1020 {
1021 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1022 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1023 MachineState *ms = MACHINE(pcms);
1024 X86MachineState *x86ms = X86_MACHINE(pcms);
1025 uint64_t hole64_start = 0;
1026
1027 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1028 hole64_start = ms->device_memory->base;
1029 if (!pcmc->broken_reserved_end) {
1030 hole64_start += memory_region_size(&ms->device_memory->mr);
1031 }
1032 } else {
1033 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1034 }
1035
1036 return ROUND_UP(hole64_start, 1 * GiB);
1037 }
1038
1039 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1040 {
1041 DeviceState *dev = NULL;
1042
1043 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1044 if (pci_bus) {
1045 PCIDevice *pcidev = pci_vga_init(pci_bus);
1046 dev = pcidev ? &pcidev->qdev : NULL;
1047 } else if (isa_bus) {
1048 ISADevice *isadev = isa_vga_init(isa_bus);
1049 dev = isadev ? DEVICE(isadev) : NULL;
1050 }
1051 rom_reset_order_override();
1052 return dev;
1053 }
1054
1055 static const MemoryRegionOps ioport80_io_ops = {
1056 .write = ioport80_write,
1057 .read = ioport80_read,
1058 .endianness = DEVICE_NATIVE_ENDIAN,
1059 .impl = {
1060 .min_access_size = 1,
1061 .max_access_size = 1,
1062 },
1063 };
1064
1065 static const MemoryRegionOps ioportF0_io_ops = {
1066 .write = ioportF0_write,
1067 .read = ioportF0_read,
1068 .endianness = DEVICE_NATIVE_ENDIAN,
1069 .impl = {
1070 .min_access_size = 1,
1071 .max_access_size = 1,
1072 },
1073 };
1074
1075 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1076 {
1077 int i;
1078 DriveInfo *fd[MAX_FD];
1079 qemu_irq *a20_line;
1080 ISADevice *fdc, *i8042, *port92, *vmmouse;
1081
1082 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1083 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1084
1085 for (i = 0; i < MAX_FD; i++) {
1086 fd[i] = drive_get(IF_FLOPPY, 0, i);
1087 create_fdctrl |= !!fd[i];
1088 }
1089 if (create_fdctrl) {
1090 fdc = isa_new(TYPE_ISA_FDC);
1091 if (fdc) {
1092 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1093 isa_fdc_init_drives(fdc, fd);
1094 }
1095 }
1096
1097 i8042 = isa_create_simple(isa_bus, "i8042");
1098 if (!no_vmport) {
1099 isa_create_simple(isa_bus, TYPE_VMPORT);
1100 vmmouse = isa_try_new("vmmouse");
1101 } else {
1102 vmmouse = NULL;
1103 }
1104 if (vmmouse) {
1105 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1106 &error_abort);
1107 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1108 }
1109 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1110
1111 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1112 i8042_setup_a20_line(i8042, a20_line[0]);
1113 qdev_connect_gpio_out_named(DEVICE(port92),
1114 PORT92_A20_LINE, 0, a20_line[1]);
1115 g_free(a20_line);
1116 }
1117
1118 void pc_basic_device_init(struct PCMachineState *pcms,
1119 ISABus *isa_bus, qemu_irq *gsi,
1120 ISADevice **rtc_state,
1121 bool create_fdctrl,
1122 uint32_t hpet_irqs)
1123 {
1124 int i;
1125 DeviceState *hpet = NULL;
1126 int pit_isa_irq = 0;
1127 qemu_irq pit_alt_irq = NULL;
1128 qemu_irq rtc_irq = NULL;
1129 ISADevice *pit = NULL;
1130 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1131 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1132
1133 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1134 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1135
1136 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1137 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1138
1139 /*
1140 * Check if an HPET shall be created.
1141 *
1142 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1143 * when the HPET wants to take over. Thus we have to disable the latter.
1144 */
1145 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1146 hpet = qdev_try_new(TYPE_HPET);
1147 if (hpet) {
1148 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1149 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1150 * IRQ8 and IRQ2.
1151 */
1152 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1153 HPET_INTCAP, NULL);
1154 if (!compat) {
1155 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1156 }
1157 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1158 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1159
1160 for (i = 0; i < GSI_NUM_PINS; i++) {
1161 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1162 }
1163 pit_isa_irq = -1;
1164 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1165 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1166 }
1167 }
1168 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1169
1170 qemu_register_boot_set(pc_boot_set, *rtc_state);
1171
1172 if (!xen_enabled() && pcms->pit_enabled) {
1173 if (kvm_pit_in_kernel()) {
1174 pit = kvm_pit_init(isa_bus, 0x40);
1175 } else {
1176 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1177 }
1178 if (hpet) {
1179 /* connect PIT to output control line of the HPET */
1180 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1181 }
1182 pcspk_init(pcms->pcspk, isa_bus, pit);
1183 }
1184
1185 i8257_dma_init(isa_bus, 0);
1186
1187 /* Super I/O */
1188 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
1189 }
1190
1191 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1192 {
1193 int i;
1194
1195 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1196 for (i = 0; i < nb_nics; i++) {
1197 NICInfo *nd = &nd_table[i];
1198 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1199
1200 if (g_str_equal(model, "ne2k_isa")) {
1201 pc_init_ne2k_isa(isa_bus, nd);
1202 } else {
1203 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1204 }
1205 }
1206 rom_reset_order_override();
1207 }
1208
1209 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1210 {
1211 qemu_irq *i8259;
1212
1213 if (kvm_pic_in_kernel()) {
1214 i8259 = kvm_i8259_init(isa_bus);
1215 } else if (xen_enabled()) {
1216 i8259 = xen_interrupt_controller_init();
1217 } else {
1218 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1219 }
1220
1221 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1222 i8259_irqs[i] = i8259[i];
1223 }
1224
1225 g_free(i8259);
1226 }
1227
1228 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1229 Error **errp)
1230 {
1231 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1232 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1233 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1234 const MachineState *ms = MACHINE(hotplug_dev);
1235 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1236 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1237 Error *local_err = NULL;
1238
1239 /*
1240 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1241 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1242 * addition to cover this case.
1243 */
1244 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1245 error_setg(errp,
1246 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1247 return;
1248 }
1249
1250 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1251 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1252 return;
1253 }
1254
1255 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1256 if (local_err) {
1257 error_propagate(errp, local_err);
1258 return;
1259 }
1260
1261 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1262 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1263 }
1264
1265 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1266 DeviceState *dev, Error **errp)
1267 {
1268 Error *local_err = NULL;
1269 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1270 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1271 MachineState *ms = MACHINE(hotplug_dev);
1272 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1273
1274 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1275 if (local_err) {
1276 goto out;
1277 }
1278
1279 if (is_nvdimm) {
1280 nvdimm_plug(ms->nvdimms_state);
1281 }
1282
1283 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1284 out:
1285 error_propagate(errp, local_err);
1286 }
1287
1288 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1289 DeviceState *dev, Error **errp)
1290 {
1291 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1292
1293 /*
1294 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1295 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1296 * addition to cover this case.
1297 */
1298 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1299 error_setg(errp,
1300 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1301 return;
1302 }
1303
1304 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1305 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1306 return;
1307 }
1308
1309 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1310 errp);
1311 }
1312
1313 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1314 DeviceState *dev, Error **errp)
1315 {
1316 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1317 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1318 Error *local_err = NULL;
1319
1320 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1321 if (local_err) {
1322 goto out;
1323 }
1324
1325 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1326 qdev_unrealize(dev);
1327 out:
1328 error_propagate(errp, local_err);
1329 }
1330
1331 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1332 DeviceState *dev, Error **errp)
1333 {
1334 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1335 Error *local_err = NULL;
1336
1337 if (!hotplug_dev2 && dev->hotplugged) {
1338 /*
1339 * Without a bus hotplug handler, we cannot control the plug/unplug
1340 * order. We should never reach this point when hotplugging on x86,
1341 * however, better add a safety net.
1342 */
1343 error_setg(errp, "hotplug of virtio based memory devices not supported"
1344 " on this bus.");
1345 return;
1346 }
1347 /*
1348 * First, see if we can plug this memory device at all. If that
1349 * succeeds, branch of to the actual hotplug handler.
1350 */
1351 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1352 &local_err);
1353 if (!local_err && hotplug_dev2) {
1354 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1355 }
1356 error_propagate(errp, local_err);
1357 }
1358
1359 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1360 DeviceState *dev, Error **errp)
1361 {
1362 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1363 Error *local_err = NULL;
1364
1365 /*
1366 * Plug the memory device first and then branch off to the actual
1367 * hotplug handler. If that one fails, we can easily undo the memory
1368 * device bits.
1369 */
1370 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1371 if (hotplug_dev2) {
1372 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1373 if (local_err) {
1374 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1375 }
1376 }
1377 error_propagate(errp, local_err);
1378 }
1379
1380 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1381 DeviceState *dev, Error **errp)
1382 {
1383 /* We don't support hot unplug of virtio based memory devices */
1384 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1385 }
1386
1387 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1388 DeviceState *dev, Error **errp)
1389 {
1390 /* We don't support hot unplug of virtio based memory devices */
1391 }
1392
1393 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1394 DeviceState *dev, Error **errp)
1395 {
1396 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1397 pc_memory_pre_plug(hotplug_dev, dev, errp);
1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1399 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1400 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1401 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1402 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1403 }
1404 }
1405
1406 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1407 DeviceState *dev, Error **errp)
1408 {
1409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1410 pc_memory_plug(hotplug_dev, dev, errp);
1411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1412 x86_cpu_plug(hotplug_dev, dev, errp);
1413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1414 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1415 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1416 }
1417 }
1418
1419 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1420 DeviceState *dev, Error **errp)
1421 {
1422 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1423 pc_memory_unplug_request(hotplug_dev, dev, errp);
1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1425 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1426 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1427 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1428 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1429 } else {
1430 error_setg(errp, "acpi: device unplug request for not supported device"
1431 " type: %s", object_get_typename(OBJECT(dev)));
1432 }
1433 }
1434
1435 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1436 DeviceState *dev, Error **errp)
1437 {
1438 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1439 pc_memory_unplug(hotplug_dev, dev, errp);
1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1441 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1443 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1444 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1445 } else {
1446 error_setg(errp, "acpi: device unplug for not supported device"
1447 " type: %s", object_get_typename(OBJECT(dev)));
1448 }
1449 }
1450
1451 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1452 DeviceState *dev)
1453 {
1454 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1455 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1456 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1457 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1458 return HOTPLUG_HANDLER(machine);
1459 }
1460
1461 return NULL;
1462 }
1463
1464 static void
1465 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1466 const char *name, void *opaque,
1467 Error **errp)
1468 {
1469 MachineState *ms = MACHINE(obj);
1470 int64_t value = 0;
1471
1472 if (ms->device_memory) {
1473 value = memory_region_size(&ms->device_memory->mr);
1474 }
1475
1476 visit_type_int(v, name, &value, errp);
1477 }
1478
1479 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1480 void *opaque, Error **errp)
1481 {
1482 PCMachineState *pcms = PC_MACHINE(obj);
1483 OnOffAuto vmport = pcms->vmport;
1484
1485 visit_type_OnOffAuto(v, name, &vmport, errp);
1486 }
1487
1488 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1489 void *opaque, Error **errp)
1490 {
1491 PCMachineState *pcms = PC_MACHINE(obj);
1492
1493 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1494 }
1495
1496 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1497 {
1498 PCMachineState *pcms = PC_MACHINE(obj);
1499
1500 return pcms->smbus_enabled;
1501 }
1502
1503 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1504 {
1505 PCMachineState *pcms = PC_MACHINE(obj);
1506
1507 pcms->smbus_enabled = value;
1508 }
1509
1510 static bool pc_machine_get_sata(Object *obj, Error **errp)
1511 {
1512 PCMachineState *pcms = PC_MACHINE(obj);
1513
1514 return pcms->sata_enabled;
1515 }
1516
1517 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1518 {
1519 PCMachineState *pcms = PC_MACHINE(obj);
1520
1521 pcms->sata_enabled = value;
1522 }
1523
1524 static bool pc_machine_get_pit(Object *obj, Error **errp)
1525 {
1526 PCMachineState *pcms = PC_MACHINE(obj);
1527
1528 return pcms->pit_enabled;
1529 }
1530
1531 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1532 {
1533 PCMachineState *pcms = PC_MACHINE(obj);
1534
1535 pcms->pit_enabled = value;
1536 }
1537
1538 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1539 const char *name, void *opaque,
1540 Error **errp)
1541 {
1542 PCMachineState *pcms = PC_MACHINE(obj);
1543 uint64_t value = pcms->max_ram_below_4g;
1544
1545 visit_type_size(v, name, &value, errp);
1546 }
1547
1548 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1549 const char *name, void *opaque,
1550 Error **errp)
1551 {
1552 PCMachineState *pcms = PC_MACHINE(obj);
1553 uint64_t value;
1554
1555 if (!visit_type_size(v, name, &value, errp)) {
1556 return;
1557 }
1558 if (value > 4 * GiB) {
1559 error_setg(errp,
1560 "Machine option 'max-ram-below-4g=%"PRIu64
1561 "' expects size less than or equal to 4G", value);
1562 return;
1563 }
1564
1565 if (value < 1 * MiB) {
1566 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1567 "BIOS may not work with less than 1MiB", value);
1568 }
1569
1570 pcms->max_ram_below_4g = value;
1571 }
1572
1573 static void pc_machine_initfn(Object *obj)
1574 {
1575 PCMachineState *pcms = PC_MACHINE(obj);
1576
1577 #ifdef CONFIG_VMPORT
1578 pcms->vmport = ON_OFF_AUTO_AUTO;
1579 #else
1580 pcms->vmport = ON_OFF_AUTO_OFF;
1581 #endif /* CONFIG_VMPORT */
1582 pcms->max_ram_below_4g = 0; /* use default */
1583 /* acpi build is enabled by default if machine supports it */
1584 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1585 pcms->smbus_enabled = true;
1586 pcms->sata_enabled = true;
1587 pcms->pit_enabled = true;
1588
1589 pc_system_flash_create(pcms);
1590 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1591 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1592 OBJECT(pcms->pcspk), "audiodev");
1593 }
1594
1595 static void pc_machine_reset(MachineState *machine)
1596 {
1597 CPUState *cs;
1598 X86CPU *cpu;
1599
1600 qemu_devices_reset();
1601
1602 /* Reset APIC after devices have been reset to cancel
1603 * any changes that qemu_devices_reset() might have done.
1604 */
1605 CPU_FOREACH(cs) {
1606 cpu = X86_CPU(cs);
1607
1608 if (cpu->apic_state) {
1609 device_legacy_reset(cpu->apic_state);
1610 }
1611 }
1612 }
1613
1614 static void pc_machine_wakeup(MachineState *machine)
1615 {
1616 cpu_synchronize_all_states();
1617 pc_machine_reset(machine);
1618 cpu_synchronize_all_post_reset();
1619 }
1620
1621 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1622 {
1623 X86IOMMUState *iommu = x86_iommu_get_default();
1624 IntelIOMMUState *intel_iommu;
1625
1626 if (iommu &&
1627 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1628 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1629 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1630 if (!intel_iommu->caching_mode) {
1631 error_setg(errp, "Device assignment is not allowed without "
1632 "enabling caching-mode=on for Intel IOMMU.");
1633 return false;
1634 }
1635 }
1636
1637 return true;
1638 }
1639
1640 static void pc_machine_class_init(ObjectClass *oc, void *data)
1641 {
1642 MachineClass *mc = MACHINE_CLASS(oc);
1643 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1644 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1645
1646 pcmc->pci_enabled = true;
1647 pcmc->has_acpi_build = true;
1648 pcmc->rsdp_in_ram = true;
1649 pcmc->smbios_defaults = true;
1650 pcmc->smbios_uuid_encoded = true;
1651 pcmc->gigabyte_align = true;
1652 pcmc->has_reserved_memory = true;
1653 pcmc->kvmclock_enabled = true;
1654 pcmc->enforce_aligned_dimm = true;
1655 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1656 * to be used at the moment, 32K should be enough for a while. */
1657 pcmc->acpi_data_size = 0x20000 + 0x8000;
1658 pcmc->linuxboot_dma_enabled = true;
1659 pcmc->pvh_enabled = true;
1660 pcmc->kvmclock_create_always = true;
1661 assert(!mc->get_hotplug_handler);
1662 mc->get_hotplug_handler = pc_get_hotplug_handler;
1663 mc->hotplug_allowed = pc_hotplug_allowed;
1664 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1665 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1666 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1667 mc->auto_enable_numa_with_memhp = true;
1668 mc->auto_enable_numa_with_memdev = true;
1669 mc->has_hotpluggable_cpus = true;
1670 mc->default_boot_order = "cad";
1671 mc->smp_parse = pc_smp_parse;
1672 mc->block_default_type = IF_IDE;
1673 mc->max_cpus = 255;
1674 mc->reset = pc_machine_reset;
1675 mc->wakeup = pc_machine_wakeup;
1676 hc->pre_plug = pc_machine_device_pre_plug_cb;
1677 hc->plug = pc_machine_device_plug_cb;
1678 hc->unplug_request = pc_machine_device_unplug_request_cb;
1679 hc->unplug = pc_machine_device_unplug_cb;
1680 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1681 mc->nvdimm_supported = true;
1682 mc->default_ram_id = "pc.ram";
1683
1684 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1685 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1686 NULL, NULL);
1687 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1688 "Maximum ram below the 4G boundary (32bit boundary)");
1689
1690 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1691 pc_machine_get_device_memory_region_size, NULL,
1692 NULL, NULL);
1693
1694 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1695 pc_machine_get_vmport, pc_machine_set_vmport,
1696 NULL, NULL);
1697 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1698 "Enable vmport (pc & q35)");
1699
1700 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1701 pc_machine_get_smbus, pc_machine_set_smbus);
1702
1703 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1704 pc_machine_get_sata, pc_machine_set_sata);
1705
1706 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1707 pc_machine_get_pit, pc_machine_set_pit);
1708 }
1709
1710 static const TypeInfo pc_machine_info = {
1711 .name = TYPE_PC_MACHINE,
1712 .parent = TYPE_X86_MACHINE,
1713 .abstract = true,
1714 .instance_size = sizeof(PCMachineState),
1715 .instance_init = pc_machine_initfn,
1716 .class_size = sizeof(PCMachineClass),
1717 .class_init = pc_machine_class_init,
1718 .interfaces = (InterfaceInfo[]) {
1719 { TYPE_HOTPLUG_HANDLER },
1720 { }
1721 },
1722 };
1723
1724 static void pc_machine_register_types(void)
1725 {
1726 type_register_static(&pc_machine_info);
1727 }
1728
1729 type_init(pc_machine_register_types)