i386: Fix pkg_id offset for EPYC cpu models
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "hw/mem/nvdimm.h"
80 #include "qapi/error.h"
81 #include "qapi/qapi-visit-common.h"
82 #include "qapi/visitor.h"
83 #include "hw/core/cpu.h"
84 #include "hw/usb.h"
85 #include "hw/i386/intel_iommu.h"
86 #include "hw/net/ne2000-isa.h"
87 #include "standard-headers/asm-x86/bootparam.h"
88 #include "hw/virtio/virtio-pmem-pci.h"
89 #include "hw/mem/memory-device.h"
90 #include "sysemu/replay.h"
91 #include "qapi/qmp/qerror.h"
92 #include "config-devices.h"
93 #include "e820_memory_layout.h"
94 #include "fw_cfg.h"
95 #include "trace.h"
96
97 GlobalProperty pc_compat_4_2[] = {
98 { "mch", "smbase-smram", "off" },
99 };
100 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
101
102 GlobalProperty pc_compat_4_1[] = {};
103 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
104
105 GlobalProperty pc_compat_4_0[] = {};
106 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
107
108 GlobalProperty pc_compat_3_1[] = {
109 { "intel-iommu", "dma-drain", "off" },
110 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
111 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
112 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
113 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
114 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
115 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
116 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
117 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
118 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
119 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
120 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
121 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
122 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
123 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
124 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
125 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
126 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
129 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
130 };
131 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
132
133 GlobalProperty pc_compat_3_0[] = {
134 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
135 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
136 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
137 };
138 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
139
140 GlobalProperty pc_compat_2_12[] = {
141 { TYPE_X86_CPU, "legacy-cache", "on" },
142 { TYPE_X86_CPU, "topoext", "off" },
143 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
144 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
145 };
146 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
147
148 GlobalProperty pc_compat_2_11[] = {
149 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
150 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
151 };
152 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
153
154 GlobalProperty pc_compat_2_10[] = {
155 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
156 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
157 { "q35-pcihost", "x-pci-hole64-fix", "off" },
158 };
159 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
160
161 GlobalProperty pc_compat_2_9[] = {
162 { "mch", "extended-tseg-mbytes", "0" },
163 };
164 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
165
166 GlobalProperty pc_compat_2_8[] = {
167 { TYPE_X86_CPU, "tcg-cpuid", "off" },
168 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
169 { "ICH9-LPC", "x-smi-broadcast", "off" },
170 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
171 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
172 };
173 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
174
175 GlobalProperty pc_compat_2_7[] = {
176 { TYPE_X86_CPU, "l3-cache", "off" },
177 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
178 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
179 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
180 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
181 { "isa-pcspk", "migrate", "off" },
182 };
183 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
184
185 GlobalProperty pc_compat_2_6[] = {
186 { TYPE_X86_CPU, "cpuid-0xb", "off" },
187 { "vmxnet3", "romfile", "" },
188 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
189 { "apic-common", "legacy-instance-id", "on", }
190 };
191 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
192
193 GlobalProperty pc_compat_2_5[] = {};
194 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
195
196 GlobalProperty pc_compat_2_4[] = {
197 PC_CPU_MODEL_IDS("2.4.0")
198 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
199 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
200 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
201 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
202 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
203 { TYPE_X86_CPU, "check", "off" },
204 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
205 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
206 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
207 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
208 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
209 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
210 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
211 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
212 };
213 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
214
215 GlobalProperty pc_compat_2_3[] = {
216 PC_CPU_MODEL_IDS("2.3.0")
217 { TYPE_X86_CPU, "arat", "off" },
218 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
219 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
220 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
221 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
222 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
223 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
224 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
225 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
226 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
227 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
228 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
229 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
237 };
238 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
239
240 GlobalProperty pc_compat_2_2[] = {
241 PC_CPU_MODEL_IDS("2.2.0")
242 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
243 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
244 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
245 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
246 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
247 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
248 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
257 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
258 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
259 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
260 };
261 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
262
263 GlobalProperty pc_compat_2_1[] = {
264 PC_CPU_MODEL_IDS("2.1.0")
265 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
266 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
267 };
268 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
269
270 GlobalProperty pc_compat_2_0[] = {
271 PC_CPU_MODEL_IDS("2.0.0")
272 { "virtio-scsi-pci", "any_layout", "off" },
273 { "PIIX4_PM", "memory-hotplug-support", "off" },
274 { "apic", "version", "0x11" },
275 { "nec-usb-xhci", "superspeed-ports-first", "off" },
276 { "nec-usb-xhci", "force-pcie-endcap", "on" },
277 { "pci-serial", "prog_if", "0" },
278 { "pci-serial-2x", "prog_if", "0" },
279 { "pci-serial-4x", "prog_if", "0" },
280 { "virtio-net-pci", "guest_announce", "off" },
281 { "ICH9-LPC", "memory-hotplug-support", "off" },
282 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
283 { "ioh3420", COMPAT_PROP_PCP, "off" },
284 };
285 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
286
287 GlobalProperty pc_compat_1_7[] = {
288 PC_CPU_MODEL_IDS("1.7.0")
289 { TYPE_USB_DEVICE, "msos-desc", "no" },
290 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
291 { "hpet", HPET_INTCAP, "4" },
292 };
293 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
294
295 GlobalProperty pc_compat_1_6[] = {
296 PC_CPU_MODEL_IDS("1.6.0")
297 { "e1000", "mitigation", "off" },
298 { "qemu64-" TYPE_X86_CPU, "model", "2" },
299 { "qemu32-" TYPE_X86_CPU, "model", "3" },
300 { "i440FX-pcihost", "short_root_bus", "1" },
301 { "q35-pcihost", "short_root_bus", "1" },
302 };
303 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
304
305 GlobalProperty pc_compat_1_5[] = {
306 PC_CPU_MODEL_IDS("1.5.0")
307 { "Conroe-" TYPE_X86_CPU, "model", "2" },
308 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
309 { "Penryn-" TYPE_X86_CPU, "model", "2" },
310 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
311 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
312 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
313 { "virtio-net-pci", "any_layout", "off" },
314 { TYPE_X86_CPU, "pmu", "on" },
315 { "i440FX-pcihost", "short_root_bus", "0" },
316 { "q35-pcihost", "short_root_bus", "0" },
317 };
318 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
319
320 GlobalProperty pc_compat_1_4[] = {
321 PC_CPU_MODEL_IDS("1.4.0")
322 { "scsi-hd", "discard_granularity", "0" },
323 { "scsi-cd", "discard_granularity", "0" },
324 { "scsi-disk", "discard_granularity", "0" },
325 { "ide-hd", "discard_granularity", "0" },
326 { "ide-cd", "discard_granularity", "0" },
327 { "ide-drive", "discard_granularity", "0" },
328 { "virtio-blk-pci", "discard_granularity", "0" },
329 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
330 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
331 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
332 { "e1000", "romfile", "pxe-e1000.rom" },
333 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
334 { "pcnet", "romfile", "pxe-pcnet.rom" },
335 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
336 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
337 { "486-" TYPE_X86_CPU, "model", "0" },
338 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
339 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
340 };
341 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
342
343 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
344 {
345 GSIState *s;
346
347 s = g_new0(GSIState, 1);
348 if (kvm_ioapic_in_kernel()) {
349 kvm_pc_setup_irq_routing(pci_enabled);
350 }
351 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
352
353 return s;
354 }
355
356 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
357 unsigned size)
358 {
359 }
360
361 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
362 {
363 return 0xffffffffffffffffULL;
364 }
365
366 /* MSDOS compatibility mode FPU exception support */
367 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
368 unsigned size)
369 {
370 if (tcg_enabled()) {
371 cpu_set_ignne();
372 }
373 }
374
375 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
376 {
377 return 0xffffffffffffffffULL;
378 }
379
380 /* PC cmos mappings */
381
382 #define REG_EQUIPMENT_BYTE 0x14
383
384 int cmos_get_fd_drive_type(FloppyDriveType fd0)
385 {
386 int val;
387
388 switch (fd0) {
389 case FLOPPY_DRIVE_TYPE_144:
390 /* 1.44 Mb 3"5 drive */
391 val = 4;
392 break;
393 case FLOPPY_DRIVE_TYPE_288:
394 /* 2.88 Mb 3"5 drive */
395 val = 5;
396 break;
397 case FLOPPY_DRIVE_TYPE_120:
398 /* 1.2 Mb 5"5 drive */
399 val = 2;
400 break;
401 case FLOPPY_DRIVE_TYPE_NONE:
402 default:
403 val = 0;
404 break;
405 }
406 return val;
407 }
408
409 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
410 int16_t cylinders, int8_t heads, int8_t sectors)
411 {
412 rtc_set_memory(s, type_ofs, 47);
413 rtc_set_memory(s, info_ofs, cylinders);
414 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
415 rtc_set_memory(s, info_ofs + 2, heads);
416 rtc_set_memory(s, info_ofs + 3, 0xff);
417 rtc_set_memory(s, info_ofs + 4, 0xff);
418 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
419 rtc_set_memory(s, info_ofs + 6, cylinders);
420 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
421 rtc_set_memory(s, info_ofs + 8, sectors);
422 }
423
424 /* convert boot_device letter to something recognizable by the bios */
425 static int boot_device2nibble(char boot_device)
426 {
427 switch(boot_device) {
428 case 'a':
429 case 'b':
430 return 0x01; /* floppy boot */
431 case 'c':
432 return 0x02; /* hard drive boot */
433 case 'd':
434 return 0x03; /* CD-ROM boot */
435 case 'n':
436 return 0x04; /* Network boot */
437 }
438 return 0;
439 }
440
441 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
442 {
443 #define PC_MAX_BOOT_DEVICES 3
444 int nbds, bds[3] = { 0, };
445 int i;
446
447 nbds = strlen(boot_device);
448 if (nbds > PC_MAX_BOOT_DEVICES) {
449 error_setg(errp, "Too many boot devices for PC");
450 return;
451 }
452 for (i = 0; i < nbds; i++) {
453 bds[i] = boot_device2nibble(boot_device[i]);
454 if (bds[i] == 0) {
455 error_setg(errp, "Invalid boot device for PC: '%c'",
456 boot_device[i]);
457 return;
458 }
459 }
460 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
461 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
462 }
463
464 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
465 {
466 set_boot_dev(opaque, boot_device, errp);
467 }
468
469 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
470 {
471 int val, nb, i;
472 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
473 FLOPPY_DRIVE_TYPE_NONE };
474
475 /* floppy type */
476 if (floppy) {
477 for (i = 0; i < 2; i++) {
478 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
479 }
480 }
481 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
482 cmos_get_fd_drive_type(fd_type[1]);
483 rtc_set_memory(rtc_state, 0x10, val);
484
485 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
486 nb = 0;
487 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
488 nb++;
489 }
490 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
491 nb++;
492 }
493 switch (nb) {
494 case 0:
495 break;
496 case 1:
497 val |= 0x01; /* 1 drive, ready for boot */
498 break;
499 case 2:
500 val |= 0x41; /* 2 drives, ready for boot */
501 break;
502 }
503 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
504 }
505
506 typedef struct pc_cmos_init_late_arg {
507 ISADevice *rtc_state;
508 BusState *idebus[2];
509 } pc_cmos_init_late_arg;
510
511 typedef struct check_fdc_state {
512 ISADevice *floppy;
513 bool multiple;
514 } CheckFdcState;
515
516 static int check_fdc(Object *obj, void *opaque)
517 {
518 CheckFdcState *state = opaque;
519 Object *fdc;
520 uint32_t iobase;
521 Error *local_err = NULL;
522
523 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
524 if (!fdc) {
525 return 0;
526 }
527
528 iobase = object_property_get_uint(obj, "iobase", &local_err);
529 if (local_err || iobase != 0x3f0) {
530 error_free(local_err);
531 return 0;
532 }
533
534 if (state->floppy) {
535 state->multiple = true;
536 } else {
537 state->floppy = ISA_DEVICE(obj);
538 }
539 return 0;
540 }
541
542 static const char * const fdc_container_path[] = {
543 "/unattached", "/peripheral", "/peripheral-anon"
544 };
545
546 /*
547 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
548 * and ACPI objects.
549 */
550 ISADevice *pc_find_fdc0(void)
551 {
552 int i;
553 Object *container;
554 CheckFdcState state = { 0 };
555
556 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
557 container = container_get(qdev_get_machine(), fdc_container_path[i]);
558 object_child_foreach(container, check_fdc, &state);
559 }
560
561 if (state.multiple) {
562 warn_report("multiple floppy disk controllers with "
563 "iobase=0x3f0 have been found");
564 error_printf("the one being picked for CMOS setup might not reflect "
565 "your intent");
566 }
567
568 return state.floppy;
569 }
570
571 static void pc_cmos_init_late(void *opaque)
572 {
573 pc_cmos_init_late_arg *arg = opaque;
574 ISADevice *s = arg->rtc_state;
575 int16_t cylinders;
576 int8_t heads, sectors;
577 int val;
578 int i, trans;
579
580 val = 0;
581 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
582 &cylinders, &heads, &sectors) >= 0) {
583 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
584 val |= 0xf0;
585 }
586 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
587 &cylinders, &heads, &sectors) >= 0) {
588 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
589 val |= 0x0f;
590 }
591 rtc_set_memory(s, 0x12, val);
592
593 val = 0;
594 for (i = 0; i < 4; i++) {
595 /* NOTE: ide_get_geometry() returns the physical
596 geometry. It is always such that: 1 <= sects <= 63, 1
597 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
598 geometry can be different if a translation is done. */
599 if (arg->idebus[i / 2] &&
600 ide_get_geometry(arg->idebus[i / 2], i % 2,
601 &cylinders, &heads, &sectors) >= 0) {
602 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
603 assert((trans & ~3) == 0);
604 val |= trans << (i * 2);
605 }
606 }
607 rtc_set_memory(s, 0x39, val);
608
609 pc_cmos_init_floppy(s, pc_find_fdc0());
610
611 qemu_unregister_reset(pc_cmos_init_late, opaque);
612 }
613
614 void pc_cmos_init(PCMachineState *pcms,
615 BusState *idebus0, BusState *idebus1,
616 ISADevice *s)
617 {
618 int val;
619 static pc_cmos_init_late_arg arg;
620 X86MachineState *x86ms = X86_MACHINE(pcms);
621
622 /* various important CMOS locations needed by PC/Bochs bios */
623
624 /* memory size */
625 /* base memory (first MiB) */
626 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
627 rtc_set_memory(s, 0x15, val);
628 rtc_set_memory(s, 0x16, val >> 8);
629 /* extended memory (next 64MiB) */
630 if (x86ms->below_4g_mem_size > 1 * MiB) {
631 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
632 } else {
633 val = 0;
634 }
635 if (val > 65535)
636 val = 65535;
637 rtc_set_memory(s, 0x17, val);
638 rtc_set_memory(s, 0x18, val >> 8);
639 rtc_set_memory(s, 0x30, val);
640 rtc_set_memory(s, 0x31, val >> 8);
641 /* memory between 16MiB and 4GiB */
642 if (x86ms->below_4g_mem_size > 16 * MiB) {
643 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
644 } else {
645 val = 0;
646 }
647 if (val > 65535)
648 val = 65535;
649 rtc_set_memory(s, 0x34, val);
650 rtc_set_memory(s, 0x35, val >> 8);
651 /* memory above 4GiB */
652 val = x86ms->above_4g_mem_size / 65536;
653 rtc_set_memory(s, 0x5b, val);
654 rtc_set_memory(s, 0x5c, val >> 8);
655 rtc_set_memory(s, 0x5d, val >> 16);
656
657 object_property_add_link(OBJECT(pcms), "rtc_state",
658 TYPE_ISA_DEVICE,
659 (Object **)&x86ms->rtc,
660 object_property_allow_set_link,
661 OBJ_PROP_LINK_STRONG, &error_abort);
662 object_property_set_link(OBJECT(pcms), OBJECT(s),
663 "rtc_state", &error_abort);
664
665 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
666
667 val = 0;
668 val |= 0x02; /* FPU is there */
669 val |= 0x04; /* PS/2 mouse installed */
670 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
671
672 /* hard drives and FDC */
673 arg.rtc_state = s;
674 arg.idebus[0] = idebus0;
675 arg.idebus[1] = idebus1;
676 qemu_register_reset(pc_cmos_init_late, &arg);
677 }
678
679 static void handle_a20_line_change(void *opaque, int irq, int level)
680 {
681 X86CPU *cpu = opaque;
682
683 /* XXX: send to all CPUs ? */
684 /* XXX: add logic to handle multiple A20 line sources */
685 x86_cpu_set_a20(cpu, level);
686 }
687
688 #define NE2000_NB_MAX 6
689
690 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
691 0x280, 0x380 };
692 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
693
694 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
695 {
696 static int nb_ne2k = 0;
697
698 if (nb_ne2k == NE2000_NB_MAX)
699 return;
700 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
701 ne2000_irq[nb_ne2k], nd);
702 nb_ne2k++;
703 }
704
705 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
706 {
707 X86CPU *cpu = opaque;
708
709 if (level) {
710 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
711 }
712 }
713
714 /*
715 * This function is very similar to smp_parse()
716 * in hw/core/machine.c but includes CPU die support.
717 */
718 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
719 {
720 X86MachineState *x86ms = X86_MACHINE(ms);
721
722 if (opts) {
723 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
724 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
725 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
726 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
727 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
728
729 /* compute missing values, prefer sockets over cores over threads */
730 if (cpus == 0 || sockets == 0) {
731 cores = cores > 0 ? cores : 1;
732 threads = threads > 0 ? threads : 1;
733 if (cpus == 0) {
734 sockets = sockets > 0 ? sockets : 1;
735 cpus = cores * threads * dies * sockets;
736 } else {
737 ms->smp.max_cpus =
738 qemu_opt_get_number(opts, "maxcpus", cpus);
739 sockets = ms->smp.max_cpus / (cores * threads * dies);
740 }
741 } else if (cores == 0) {
742 threads = threads > 0 ? threads : 1;
743 cores = cpus / (sockets * dies * threads);
744 cores = cores > 0 ? cores : 1;
745 } else if (threads == 0) {
746 threads = cpus / (cores * dies * sockets);
747 threads = threads > 0 ? threads : 1;
748 } else if (sockets * dies * cores * threads < cpus) {
749 error_report("cpu topology: "
750 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
751 "smp_cpus (%u)",
752 sockets, dies, cores, threads, cpus);
753 exit(1);
754 }
755
756 ms->smp.max_cpus =
757 qemu_opt_get_number(opts, "maxcpus", cpus);
758
759 if (ms->smp.max_cpus < cpus) {
760 error_report("maxcpus must be equal to or greater than smp");
761 exit(1);
762 }
763
764 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
765 error_report("cpu topology: "
766 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
767 "maxcpus (%u)",
768 sockets, dies, cores, threads,
769 ms->smp.max_cpus);
770 exit(1);
771 }
772
773 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
774 warn_report("Invalid CPU topology deprecated: "
775 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
776 "!= maxcpus (%u)",
777 sockets, dies, cores, threads,
778 ms->smp.max_cpus);
779 }
780
781 ms->smp.cpus = cpus;
782 ms->smp.cores = cores;
783 ms->smp.threads = threads;
784 ms->smp.sockets = sockets;
785 x86ms->smp_dies = dies;
786 }
787
788 if (ms->smp.cpus > 1) {
789 Error *blocker = NULL;
790 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
791 replay_add_blocker(blocker);
792 }
793 }
794
795 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
796 {
797 X86MachineState *x86ms = X86_MACHINE(ms);
798 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
799 Error *local_err = NULL;
800
801 if (id < 0) {
802 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
803 return;
804 }
805
806 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
807 error_setg(errp, "Unable to add CPU: %" PRIi64
808 ", resulting APIC ID (%" PRIi64 ") is too large",
809 id, apic_id);
810 return;
811 }
812
813
814 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
815 if (local_err) {
816 error_propagate(errp, local_err);
817 return;
818 }
819 }
820
821 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
822 {
823 if (cpus_count > 0xff) {
824 /* If the number of CPUs can't be represented in 8 bits, the
825 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
826 * to make old BIOSes fail more predictably.
827 */
828 rtc_set_memory(rtc, 0x5f, 0);
829 } else {
830 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
831 }
832 }
833
834 static
835 void pc_machine_done(Notifier *notifier, void *data)
836 {
837 PCMachineState *pcms = container_of(notifier,
838 PCMachineState, machine_done);
839 X86MachineState *x86ms = X86_MACHINE(pcms);
840 PCIBus *bus = pcms->bus;
841
842 /* set the number of CPUs */
843 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
844
845 if (bus) {
846 int extra_hosts = 0;
847
848 QLIST_FOREACH(bus, &bus->child, sibling) {
849 /* look for expander root buses */
850 if (pci_bus_is_root(bus)) {
851 extra_hosts++;
852 }
853 }
854 if (extra_hosts && x86ms->fw_cfg) {
855 uint64_t *val = g_malloc(sizeof(*val));
856 *val = cpu_to_le64(extra_hosts);
857 fw_cfg_add_file(x86ms->fw_cfg,
858 "etc/extra-pci-roots", val, sizeof(*val));
859 }
860 }
861
862 acpi_setup();
863 if (x86ms->fw_cfg) {
864 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
865 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
866 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
867 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
868 }
869
870 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
871 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
872
873 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
874 iommu->intr_eim != ON_OFF_AUTO_ON) {
875 error_report("current -smp configuration requires "
876 "Extended Interrupt Mode enabled. "
877 "You can add an IOMMU using: "
878 "-device intel-iommu,intremap=on,eim=on");
879 exit(EXIT_FAILURE);
880 }
881 }
882 }
883
884 void pc_guest_info_init(PCMachineState *pcms)
885 {
886 int i;
887 MachineState *ms = MACHINE(pcms);
888 X86MachineState *x86ms = X86_MACHINE(pcms);
889
890 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
891 pcms->numa_nodes = ms->numa_state->num_nodes;
892 pcms->node_mem = g_malloc0(pcms->numa_nodes *
893 sizeof *pcms->node_mem);
894 for (i = 0; i < ms->numa_state->num_nodes; i++) {
895 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
896 }
897
898 pcms->machine_done.notify = pc_machine_done;
899 qemu_add_machine_init_done_notifier(&pcms->machine_done);
900 }
901
902 /* setup pci memory address space mapping into system address space */
903 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
904 MemoryRegion *pci_address_space)
905 {
906 /* Set to lower priority than RAM */
907 memory_region_add_subregion_overlap(system_memory, 0x0,
908 pci_address_space, -1);
909 }
910
911 void xen_load_linux(PCMachineState *pcms)
912 {
913 int i;
914 FWCfgState *fw_cfg;
915 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
916 X86MachineState *x86ms = X86_MACHINE(pcms);
917
918 assert(MACHINE(pcms)->kernel_filename != NULL);
919
920 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
921 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
922 rom_set_fw(fw_cfg);
923
924 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
925 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
926 for (i = 0; i < nb_option_roms; i++) {
927 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
928 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
929 !strcmp(option_rom[i].name, "pvh.bin") ||
930 !strcmp(option_rom[i].name, "multiboot.bin"));
931 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
932 }
933 x86ms->fw_cfg = fw_cfg;
934 }
935
936 void pc_memory_init(PCMachineState *pcms,
937 MemoryRegion *system_memory,
938 MemoryRegion *rom_memory,
939 MemoryRegion **ram_memory)
940 {
941 int linux_boot, i;
942 MemoryRegion *option_rom_mr;
943 MemoryRegion *ram_below_4g, *ram_above_4g;
944 FWCfgState *fw_cfg;
945 MachineState *machine = MACHINE(pcms);
946 MachineClass *mc = MACHINE_GET_CLASS(machine);
947 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
948 X86MachineState *x86ms = X86_MACHINE(pcms);
949
950 assert(machine->ram_size == x86ms->below_4g_mem_size +
951 x86ms->above_4g_mem_size);
952
953 linux_boot = (machine->kernel_filename != NULL);
954
955 /*
956 * Split single memory region and use aliases to address portions of it,
957 * done for backwards compatibility with older qemus.
958 */
959 *ram_memory = machine->ram;
960 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
961 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
962 0, x86ms->below_4g_mem_size);
963 memory_region_add_subregion(system_memory, 0, ram_below_4g);
964 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
965 if (x86ms->above_4g_mem_size > 0) {
966 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
967 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
968 machine->ram,
969 x86ms->below_4g_mem_size,
970 x86ms->above_4g_mem_size);
971 memory_region_add_subregion(system_memory, 0x100000000ULL,
972 ram_above_4g);
973 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
974 }
975
976 if (!pcmc->has_reserved_memory &&
977 (machine->ram_slots ||
978 (machine->maxram_size > machine->ram_size))) {
979
980 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
981 mc->name);
982 exit(EXIT_FAILURE);
983 }
984
985 /* always allocate the device memory information */
986 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
987
988 /* initialize device memory address space */
989 if (pcmc->has_reserved_memory &&
990 (machine->ram_size < machine->maxram_size)) {
991 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
992
993 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
994 error_report("unsupported amount of memory slots: %"PRIu64,
995 machine->ram_slots);
996 exit(EXIT_FAILURE);
997 }
998
999 if (QEMU_ALIGN_UP(machine->maxram_size,
1000 TARGET_PAGE_SIZE) != machine->maxram_size) {
1001 error_report("maximum memory size must by aligned to multiple of "
1002 "%d bytes", TARGET_PAGE_SIZE);
1003 exit(EXIT_FAILURE);
1004 }
1005
1006 machine->device_memory->base =
1007 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1008
1009 if (pcmc->enforce_aligned_dimm) {
1010 /* size device region assuming 1G page max alignment per slot */
1011 device_mem_size += (1 * GiB) * machine->ram_slots;
1012 }
1013
1014 if ((machine->device_memory->base + device_mem_size) <
1015 device_mem_size) {
1016 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1017 machine->maxram_size);
1018 exit(EXIT_FAILURE);
1019 }
1020
1021 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1022 "device-memory", device_mem_size);
1023 memory_region_add_subregion(system_memory, machine->device_memory->base,
1024 &machine->device_memory->mr);
1025 }
1026
1027 /* Initialize PC system firmware */
1028 pc_system_firmware_init(pcms, rom_memory);
1029
1030 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1031 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1032 &error_fatal);
1033 if (pcmc->pci_enabled) {
1034 memory_region_set_readonly(option_rom_mr, true);
1035 }
1036 memory_region_add_subregion_overlap(rom_memory,
1037 PC_ROM_MIN_VGA,
1038 option_rom_mr,
1039 1);
1040
1041 fw_cfg = fw_cfg_arch_create(machine,
1042 x86ms->boot_cpus, x86ms->apic_id_limit);
1043
1044 rom_set_fw(fw_cfg);
1045
1046 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1047 uint64_t *val = g_malloc(sizeof(*val));
1048 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1049 uint64_t res_mem_end = machine->device_memory->base;
1050
1051 if (!pcmc->broken_reserved_end) {
1052 res_mem_end += memory_region_size(&machine->device_memory->mr);
1053 }
1054 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1055 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1056 }
1057
1058 if (linux_boot) {
1059 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1060 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1061 }
1062
1063 for (i = 0; i < nb_option_roms; i++) {
1064 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1065 }
1066 x86ms->fw_cfg = fw_cfg;
1067
1068 /* Init default IOAPIC address space */
1069 x86ms->ioapic_as = &address_space_memory;
1070
1071 /* Init ACPI memory hotplug IO base address */
1072 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1073 }
1074
1075 /*
1076 * The 64bit pci hole starts after "above 4G RAM" and
1077 * potentially the space reserved for memory hotplug.
1078 */
1079 uint64_t pc_pci_hole64_start(void)
1080 {
1081 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1082 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1083 MachineState *ms = MACHINE(pcms);
1084 X86MachineState *x86ms = X86_MACHINE(pcms);
1085 uint64_t hole64_start = 0;
1086
1087 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1088 hole64_start = ms->device_memory->base;
1089 if (!pcmc->broken_reserved_end) {
1090 hole64_start += memory_region_size(&ms->device_memory->mr);
1091 }
1092 } else {
1093 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1094 }
1095
1096 return ROUND_UP(hole64_start, 1 * GiB);
1097 }
1098
1099 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1100 {
1101 DeviceState *dev = NULL;
1102
1103 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1104 if (pci_bus) {
1105 PCIDevice *pcidev = pci_vga_init(pci_bus);
1106 dev = pcidev ? &pcidev->qdev : NULL;
1107 } else if (isa_bus) {
1108 ISADevice *isadev = isa_vga_init(isa_bus);
1109 dev = isadev ? DEVICE(isadev) : NULL;
1110 }
1111 rom_reset_order_override();
1112 return dev;
1113 }
1114
1115 static const MemoryRegionOps ioport80_io_ops = {
1116 .write = ioport80_write,
1117 .read = ioport80_read,
1118 .endianness = DEVICE_NATIVE_ENDIAN,
1119 .impl = {
1120 .min_access_size = 1,
1121 .max_access_size = 1,
1122 },
1123 };
1124
1125 static const MemoryRegionOps ioportF0_io_ops = {
1126 .write = ioportF0_write,
1127 .read = ioportF0_read,
1128 .endianness = DEVICE_NATIVE_ENDIAN,
1129 .impl = {
1130 .min_access_size = 1,
1131 .max_access_size = 1,
1132 },
1133 };
1134
1135 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1136 {
1137 int i;
1138 DriveInfo *fd[MAX_FD];
1139 qemu_irq *a20_line;
1140 ISADevice *i8042, *port92, *vmmouse;
1141
1142 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1143 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1144
1145 for (i = 0; i < MAX_FD; i++) {
1146 fd[i] = drive_get(IF_FLOPPY, 0, i);
1147 create_fdctrl |= !!fd[i];
1148 }
1149 if (create_fdctrl) {
1150 fdctrl_init_isa(isa_bus, fd);
1151 }
1152
1153 i8042 = isa_create_simple(isa_bus, "i8042");
1154 if (!no_vmport) {
1155 vmport_init(isa_bus);
1156 vmmouse = isa_try_create(isa_bus, "vmmouse");
1157 } else {
1158 vmmouse = NULL;
1159 }
1160 if (vmmouse) {
1161 object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
1162 "i8042", &error_abort);
1163 qdev_init_nofail(DEVICE(vmmouse));
1164 }
1165 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1166
1167 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1168 i8042_setup_a20_line(i8042, a20_line[0]);
1169 qdev_connect_gpio_out_named(DEVICE(port92),
1170 PORT92_A20_LINE, 0, a20_line[1]);
1171 g_free(a20_line);
1172 }
1173
1174 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1175 ISADevice **rtc_state,
1176 bool create_fdctrl,
1177 bool no_vmport,
1178 bool has_pit,
1179 uint32_t hpet_irqs)
1180 {
1181 int i;
1182 DeviceState *hpet = NULL;
1183 int pit_isa_irq = 0;
1184 qemu_irq pit_alt_irq = NULL;
1185 qemu_irq rtc_irq = NULL;
1186 ISADevice *pit = NULL;
1187 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1188 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1189
1190 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1191 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1192
1193 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1194 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1195
1196 /*
1197 * Check if an HPET shall be created.
1198 *
1199 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1200 * when the HPET wants to take over. Thus we have to disable the latter.
1201 */
1202 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1203 hpet = qdev_try_create(NULL, TYPE_HPET);
1204 if (hpet) {
1205 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1206 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1207 * IRQ8 and IRQ2.
1208 */
1209 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1210 HPET_INTCAP, NULL);
1211 if (!compat) {
1212 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1213 }
1214 qdev_init_nofail(hpet);
1215 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1216
1217 for (i = 0; i < GSI_NUM_PINS; i++) {
1218 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1219 }
1220 pit_isa_irq = -1;
1221 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1222 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1223 }
1224 }
1225 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1226
1227 qemu_register_boot_set(pc_boot_set, *rtc_state);
1228
1229 if (!xen_enabled() && has_pit) {
1230 if (kvm_pit_in_kernel()) {
1231 pit = kvm_pit_init(isa_bus, 0x40);
1232 } else {
1233 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1234 }
1235 if (hpet) {
1236 /* connect PIT to output control line of the HPET */
1237 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1238 }
1239 pcspk_init(isa_bus, pit);
1240 }
1241
1242 i8257_dma_init(isa_bus, 0);
1243
1244 /* Super I/O */
1245 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1246 }
1247
1248 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1249 {
1250 int i;
1251
1252 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1253 for (i = 0; i < nb_nics; i++) {
1254 NICInfo *nd = &nd_table[i];
1255 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1256
1257 if (g_str_equal(model, "ne2k_isa")) {
1258 pc_init_ne2k_isa(isa_bus, nd);
1259 } else {
1260 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1261 }
1262 }
1263 rom_reset_order_override();
1264 }
1265
1266 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1267 {
1268 qemu_irq *i8259;
1269
1270 if (kvm_pic_in_kernel()) {
1271 i8259 = kvm_i8259_init(isa_bus);
1272 } else if (xen_enabled()) {
1273 i8259 = xen_interrupt_controller_init();
1274 } else {
1275 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1276 }
1277
1278 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1279 i8259_irqs[i] = i8259[i];
1280 }
1281
1282 g_free(i8259);
1283 }
1284
1285 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1286 Error **errp)
1287 {
1288 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1289 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1290 const MachineState *ms = MACHINE(hotplug_dev);
1291 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1292 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1293 Error *local_err = NULL;
1294
1295 /*
1296 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1297 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1298 * addition to cover this case.
1299 */
1300 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1301 error_setg(errp,
1302 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1303 return;
1304 }
1305
1306 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1307 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1308 return;
1309 }
1310
1311 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1312 if (local_err) {
1313 error_propagate(errp, local_err);
1314 return;
1315 }
1316
1317 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1318 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1319 }
1320
1321 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1322 DeviceState *dev, Error **errp)
1323 {
1324 Error *local_err = NULL;
1325 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1326 MachineState *ms = MACHINE(hotplug_dev);
1327 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1328
1329 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1330 if (local_err) {
1331 goto out;
1332 }
1333
1334 if (is_nvdimm) {
1335 nvdimm_plug(ms->nvdimms_state);
1336 }
1337
1338 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1339 out:
1340 error_propagate(errp, local_err);
1341 }
1342
1343 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1344 DeviceState *dev, Error **errp)
1345 {
1346 Error *local_err = NULL;
1347 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1348
1349 /*
1350 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1351 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1352 * addition to cover this case.
1353 */
1354 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1355 error_setg(&local_err,
1356 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1357 goto out;
1358 }
1359
1360 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1361 error_setg(&local_err,
1362 "nvdimm device hot unplug is not supported yet.");
1363 goto out;
1364 }
1365
1366 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1367 &local_err);
1368 out:
1369 error_propagate(errp, local_err);
1370 }
1371
1372 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1373 DeviceState *dev, Error **errp)
1374 {
1375 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1376 Error *local_err = NULL;
1377
1378 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1379 if (local_err) {
1380 goto out;
1381 }
1382
1383 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1384 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1385 out:
1386 error_propagate(errp, local_err);
1387 }
1388
1389 static int pc_apic_cmp(const void *a, const void *b)
1390 {
1391 CPUArchId *apic_a = (CPUArchId *)a;
1392 CPUArchId *apic_b = (CPUArchId *)b;
1393
1394 return apic_a->arch_id - apic_b->arch_id;
1395 }
1396
1397 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1398 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1399 * entry corresponding to CPU's apic_id returns NULL.
1400 */
1401 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1402 {
1403 CPUArchId apic_id, *found_cpu;
1404
1405 apic_id.arch_id = id;
1406 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1407 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1408 pc_apic_cmp);
1409 if (found_cpu && idx) {
1410 *idx = found_cpu - ms->possible_cpus->cpus;
1411 }
1412 return found_cpu;
1413 }
1414
1415 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1416 DeviceState *dev, Error **errp)
1417 {
1418 CPUArchId *found_cpu;
1419 Error *local_err = NULL;
1420 X86CPU *cpu = X86_CPU(dev);
1421 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1422 X86MachineState *x86ms = X86_MACHINE(pcms);
1423
1424 if (pcms->acpi_dev) {
1425 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1426 if (local_err) {
1427 goto out;
1428 }
1429 }
1430
1431 /* increment the number of CPUs */
1432 x86ms->boot_cpus++;
1433 if (x86ms->rtc) {
1434 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1435 }
1436 if (x86ms->fw_cfg) {
1437 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1438 }
1439
1440 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1441 found_cpu->cpu = OBJECT(dev);
1442 out:
1443 error_propagate(errp, local_err);
1444 }
1445 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1446 DeviceState *dev, Error **errp)
1447 {
1448 int idx = -1;
1449 Error *local_err = NULL;
1450 X86CPU *cpu = X86_CPU(dev);
1451 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1452
1453 if (!pcms->acpi_dev) {
1454 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1455 goto out;
1456 }
1457
1458 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1459 assert(idx != -1);
1460 if (idx == 0) {
1461 error_setg(&local_err, "Boot CPU is unpluggable");
1462 goto out;
1463 }
1464
1465 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1466 &local_err);
1467 if (local_err) {
1468 goto out;
1469 }
1470
1471 out:
1472 error_propagate(errp, local_err);
1473
1474 }
1475
1476 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1477 DeviceState *dev, Error **errp)
1478 {
1479 CPUArchId *found_cpu;
1480 Error *local_err = NULL;
1481 X86CPU *cpu = X86_CPU(dev);
1482 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1483 X86MachineState *x86ms = X86_MACHINE(pcms);
1484
1485 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1486 if (local_err) {
1487 goto out;
1488 }
1489
1490 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1491 found_cpu->cpu = NULL;
1492 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
1493
1494 /* decrement the number of CPUs */
1495 x86ms->boot_cpus--;
1496 /* Update the number of CPUs in CMOS */
1497 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1498 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1499 out:
1500 error_propagate(errp, local_err);
1501 }
1502
1503 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1504 DeviceState *dev, Error **errp)
1505 {
1506 int idx;
1507 CPUState *cs;
1508 CPUArchId *cpu_slot;
1509 X86CPUTopoIDs topo_ids;
1510 X86CPU *cpu = X86_CPU(dev);
1511 CPUX86State *env = &cpu->env;
1512 MachineState *ms = MACHINE(hotplug_dev);
1513 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1514 X86MachineState *x86ms = X86_MACHINE(pcms);
1515 unsigned int smp_cores = ms->smp.cores;
1516 unsigned int smp_threads = ms->smp.threads;
1517 X86CPUTopoInfo topo_info;
1518
1519 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1520 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1521 ms->cpu_type);
1522 return;
1523 }
1524
1525 init_topo_info(&topo_info, x86ms);
1526
1527 env->nr_dies = x86ms->smp_dies;
1528 env->nr_nodes = topo_info.nodes_per_pkg;
1529 env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info);
1530
1531 /*
1532 * If APIC ID is not set,
1533 * set it based on socket/die/core/thread properties.
1534 */
1535 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1536 int max_socket = (ms->smp.max_cpus - 1) /
1537 smp_threads / smp_cores / x86ms->smp_dies;
1538
1539 /*
1540 * die-id was optional in QEMU 4.0 and older, so keep it optional
1541 * if there's only one die per socket.
1542 */
1543 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1544 cpu->die_id = 0;
1545 }
1546
1547 if (cpu->socket_id < 0) {
1548 error_setg(errp, "CPU socket-id is not set");
1549 return;
1550 } else if (cpu->socket_id > max_socket) {
1551 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1552 cpu->socket_id, max_socket);
1553 return;
1554 }
1555 if (cpu->die_id < 0) {
1556 error_setg(errp, "CPU die-id is not set");
1557 return;
1558 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1559 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1560 cpu->die_id, x86ms->smp_dies - 1);
1561 return;
1562 }
1563 if (cpu->core_id < 0) {
1564 error_setg(errp, "CPU core-id is not set");
1565 return;
1566 } else if (cpu->core_id > (smp_cores - 1)) {
1567 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1568 cpu->core_id, smp_cores - 1);
1569 return;
1570 }
1571 if (cpu->thread_id < 0) {
1572 error_setg(errp, "CPU thread-id is not set");
1573 return;
1574 } else if (cpu->thread_id > (smp_threads - 1)) {
1575 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1576 cpu->thread_id, smp_threads - 1);
1577 return;
1578 }
1579
1580 topo_ids.pkg_id = cpu->socket_id;
1581 topo_ids.die_id = cpu->die_id;
1582 topo_ids.core_id = cpu->core_id;
1583 topo_ids.smt_id = cpu->thread_id;
1584 cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
1585 }
1586
1587 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1588 if (!cpu_slot) {
1589 MachineState *ms = MACHINE(pcms);
1590
1591 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1592 error_setg(errp,
1593 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1594 " APIC ID %" PRIu32 ", valid index range 0:%d",
1595 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,
1596 cpu->apic_id, ms->possible_cpus->len - 1);
1597 return;
1598 }
1599
1600 if (cpu_slot->cpu) {
1601 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1602 idx, cpu->apic_id);
1603 return;
1604 }
1605
1606 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1607 * so that machine_query_hotpluggable_cpus would show correct values
1608 */
1609 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1610 * once -smp refactoring is complete and there will be CPU private
1611 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1612 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1613 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
1614 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1615 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
1616 topo_ids.pkg_id);
1617 return;
1618 }
1619 cpu->socket_id = topo_ids.pkg_id;
1620
1621 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
1622 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1623 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
1624 return;
1625 }
1626 cpu->die_id = topo_ids.die_id;
1627
1628 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
1629 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1630 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
1631 topo_ids.core_id);
1632 return;
1633 }
1634 cpu->core_id = topo_ids.core_id;
1635
1636 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
1637 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1638 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
1639 topo_ids.smt_id);
1640 return;
1641 }
1642 cpu->thread_id = topo_ids.smt_id;
1643
1644 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1645 !kvm_hv_vpindex_settable()) {
1646 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1647 return;
1648 }
1649
1650 cs = CPU(cpu);
1651 cs->cpu_index = idx;
1652
1653 numa_cpu_pre_plug(cpu_slot, dev, errp);
1654 }
1655
1656 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1657 DeviceState *dev, Error **errp)
1658 {
1659 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1660 Error *local_err = NULL;
1661
1662 if (!hotplug_dev2) {
1663 /*
1664 * Without a bus hotplug handler, we cannot control the plug/unplug
1665 * order. This should never be the case on x86, however better add
1666 * a safety net.
1667 */
1668 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1669 return;
1670 }
1671 /*
1672 * First, see if we can plug this memory device at all. If that
1673 * succeeds, branch of to the actual hotplug handler.
1674 */
1675 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1676 &local_err);
1677 if (!local_err) {
1678 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1679 }
1680 error_propagate(errp, local_err);
1681 }
1682
1683 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1684 DeviceState *dev, Error **errp)
1685 {
1686 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1687 Error *local_err = NULL;
1688
1689 /*
1690 * Plug the memory device first and then branch off to the actual
1691 * hotplug handler. If that one fails, we can easily undo the memory
1692 * device bits.
1693 */
1694 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1695 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1696 if (local_err) {
1697 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1698 }
1699 error_propagate(errp, local_err);
1700 }
1701
1702 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1703 DeviceState *dev, Error **errp)
1704 {
1705 /* We don't support virtio pmem hot unplug */
1706 error_setg(errp, "virtio pmem device unplug not supported.");
1707 }
1708
1709 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1710 DeviceState *dev, Error **errp)
1711 {
1712 /* We don't support virtio pmem hot unplug */
1713 }
1714
1715 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1716 DeviceState *dev, Error **errp)
1717 {
1718 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1719 pc_memory_pre_plug(hotplug_dev, dev, errp);
1720 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1721 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1722 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1723 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1724 }
1725 }
1726
1727 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1728 DeviceState *dev, Error **errp)
1729 {
1730 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1731 pc_memory_plug(hotplug_dev, dev, errp);
1732 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1733 pc_cpu_plug(hotplug_dev, dev, errp);
1734 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1735 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1736 }
1737 }
1738
1739 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1740 DeviceState *dev, Error **errp)
1741 {
1742 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1743 pc_memory_unplug_request(hotplug_dev, dev, errp);
1744 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1745 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1746 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1747 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1748 } else {
1749 error_setg(errp, "acpi: device unplug request for not supported device"
1750 " type: %s", object_get_typename(OBJECT(dev)));
1751 }
1752 }
1753
1754 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1755 DeviceState *dev, Error **errp)
1756 {
1757 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1758 pc_memory_unplug(hotplug_dev, dev, errp);
1759 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1760 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1761 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1762 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1763 } else {
1764 error_setg(errp, "acpi: device unplug for not supported device"
1765 " type: %s", object_get_typename(OBJECT(dev)));
1766 }
1767 }
1768
1769 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1770 DeviceState *dev)
1771 {
1772 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1773 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1774 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1775 return HOTPLUG_HANDLER(machine);
1776 }
1777
1778 return NULL;
1779 }
1780
1781 static void
1782 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1783 const char *name, void *opaque,
1784 Error **errp)
1785 {
1786 MachineState *ms = MACHINE(obj);
1787 int64_t value = 0;
1788
1789 if (ms->device_memory) {
1790 value = memory_region_size(&ms->device_memory->mr);
1791 }
1792
1793 visit_type_int(v, name, &value, errp);
1794 }
1795
1796 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1797 void *opaque, Error **errp)
1798 {
1799 PCMachineState *pcms = PC_MACHINE(obj);
1800 OnOffAuto vmport = pcms->vmport;
1801
1802 visit_type_OnOffAuto(v, name, &vmport, errp);
1803 }
1804
1805 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1806 void *opaque, Error **errp)
1807 {
1808 PCMachineState *pcms = PC_MACHINE(obj);
1809
1810 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1811 }
1812
1813 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1814 {
1815 PCMachineState *pcms = PC_MACHINE(obj);
1816
1817 return pcms->smbus_enabled;
1818 }
1819
1820 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1821 {
1822 PCMachineState *pcms = PC_MACHINE(obj);
1823
1824 pcms->smbus_enabled = value;
1825 }
1826
1827 static bool pc_machine_get_sata(Object *obj, Error **errp)
1828 {
1829 PCMachineState *pcms = PC_MACHINE(obj);
1830
1831 return pcms->sata_enabled;
1832 }
1833
1834 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1835 {
1836 PCMachineState *pcms = PC_MACHINE(obj);
1837
1838 pcms->sata_enabled = value;
1839 }
1840
1841 static bool pc_machine_get_pit(Object *obj, Error **errp)
1842 {
1843 PCMachineState *pcms = PC_MACHINE(obj);
1844
1845 return pcms->pit_enabled;
1846 }
1847
1848 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1849 {
1850 PCMachineState *pcms = PC_MACHINE(obj);
1851
1852 pcms->pit_enabled = value;
1853 }
1854
1855 static void pc_machine_initfn(Object *obj)
1856 {
1857 PCMachineState *pcms = PC_MACHINE(obj);
1858
1859 #ifdef CONFIG_VMPORT
1860 pcms->vmport = ON_OFF_AUTO_AUTO;
1861 #else
1862 pcms->vmport = ON_OFF_AUTO_OFF;
1863 #endif /* CONFIG_VMPORT */
1864 /* acpi build is enabled by default if machine supports it */
1865 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1866 pcms->smbus_enabled = true;
1867 pcms->sata_enabled = true;
1868 pcms->pit_enabled = true;
1869
1870 pc_system_flash_create(pcms);
1871 }
1872
1873 static void pc_machine_reset(MachineState *machine)
1874 {
1875 CPUState *cs;
1876 X86CPU *cpu;
1877
1878 qemu_devices_reset();
1879
1880 /* Reset APIC after devices have been reset to cancel
1881 * any changes that qemu_devices_reset() might have done.
1882 */
1883 CPU_FOREACH(cs) {
1884 cpu = X86_CPU(cs);
1885
1886 if (cpu->apic_state) {
1887 device_legacy_reset(cpu->apic_state);
1888 }
1889 }
1890 }
1891
1892 static void pc_machine_wakeup(MachineState *machine)
1893 {
1894 cpu_synchronize_all_states();
1895 pc_machine_reset(machine);
1896 cpu_synchronize_all_post_reset();
1897 }
1898
1899 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1900 {
1901 X86IOMMUState *iommu = x86_iommu_get_default();
1902 IntelIOMMUState *intel_iommu;
1903
1904 if (iommu &&
1905 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1906 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1907 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1908 if (!intel_iommu->caching_mode) {
1909 error_setg(errp, "Device assignment is not allowed without "
1910 "enabling caching-mode=on for Intel IOMMU.");
1911 return false;
1912 }
1913 }
1914
1915 return true;
1916 }
1917
1918 static void pc_machine_class_init(ObjectClass *oc, void *data)
1919 {
1920 MachineClass *mc = MACHINE_CLASS(oc);
1921 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1922 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1923
1924 pcmc->pci_enabled = true;
1925 pcmc->has_acpi_build = true;
1926 pcmc->rsdp_in_ram = true;
1927 pcmc->smbios_defaults = true;
1928 pcmc->smbios_uuid_encoded = true;
1929 pcmc->gigabyte_align = true;
1930 pcmc->has_reserved_memory = true;
1931 pcmc->kvmclock_enabled = true;
1932 pcmc->enforce_aligned_dimm = true;
1933 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1934 * to be used at the moment, 32K should be enough for a while. */
1935 pcmc->acpi_data_size = 0x20000 + 0x8000;
1936 pcmc->linuxboot_dma_enabled = true;
1937 pcmc->pvh_enabled = true;
1938 assert(!mc->get_hotplug_handler);
1939 mc->get_hotplug_handler = pc_get_hotplug_handler;
1940 mc->hotplug_allowed = pc_hotplug_allowed;
1941 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1942 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1943 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1944 mc->auto_enable_numa_with_memhp = true;
1945 mc->has_hotpluggable_cpus = true;
1946 mc->default_boot_order = "cad";
1947 mc->hot_add_cpu = pc_hot_add_cpu;
1948 mc->smp_parse = pc_smp_parse;
1949 mc->block_default_type = IF_IDE;
1950 mc->max_cpus = 255;
1951 mc->reset = pc_machine_reset;
1952 mc->wakeup = pc_machine_wakeup;
1953 hc->pre_plug = pc_machine_device_pre_plug_cb;
1954 hc->plug = pc_machine_device_plug_cb;
1955 hc->unplug_request = pc_machine_device_unplug_request_cb;
1956 hc->unplug = pc_machine_device_unplug_cb;
1957 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1958 mc->nvdimm_supported = true;
1959 mc->numa_mem_supported = true;
1960 mc->default_ram_id = "pc.ram";
1961
1962 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1963 pc_machine_get_device_memory_region_size, NULL,
1964 NULL, NULL, &error_abort);
1965
1966 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1967 pc_machine_get_vmport, pc_machine_set_vmport,
1968 NULL, NULL, &error_abort);
1969 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1970 "Enable vmport (pc & q35)", &error_abort);
1971
1972 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1973 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
1974
1975 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1976 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
1977
1978 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1979 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
1980 }
1981
1982 static const TypeInfo pc_machine_info = {
1983 .name = TYPE_PC_MACHINE,
1984 .parent = TYPE_X86_MACHINE,
1985 .abstract = true,
1986 .instance_size = sizeof(PCMachineState),
1987 .instance_init = pc_machine_initfn,
1988 .class_size = sizeof(PCMachineClass),
1989 .class_init = pc_machine_class_init,
1990 .interfaces = (InterfaceInfo[]) {
1991 { TYPE_HOTPLUG_HANDLER },
1992 { }
1993 },
1994 };
1995
1996 static void pc_machine_register_types(void)
1997 {
1998 type_register_static(&pc_machine_info);
1999 }
2000
2001 type_init(pc_machine_register_types)