pc: pass MachineState to pc_memory_init
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
29 #include "hw/ide.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
61 #include "hw/mem/pc-dimm.h"
62 #include "trace.h"
63 #include "qapi/visitor.h"
64
65 /* debug PC/ISA interrupts */
66 //#define DEBUG_IRQ
67
68 #ifdef DEBUG_IRQ
69 #define DPRINTF(fmt, ...) \
70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
71 #else
72 #define DPRINTF(fmt, ...)
73 #endif
74
75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
76 #define ACPI_DATA_SIZE 0x10000
77 #define BIOS_CFG_IOPORT 0x510
78 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
79 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
80 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
81 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
82 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
83
84 #define E820_NR_ENTRIES 16
85
86 struct e820_entry {
87 uint64_t address;
88 uint64_t length;
89 uint32_t type;
90 } QEMU_PACKED __attribute((__aligned__(4)));
91
92 struct e820_table {
93 uint32_t count;
94 struct e820_entry entry[E820_NR_ENTRIES];
95 } QEMU_PACKED __attribute((__aligned__(4)));
96
97 static struct e820_table e820_reserve;
98 static struct e820_entry *e820_table;
99 static unsigned e820_entries;
100 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
101
102 void gsi_handler(void *opaque, int n, int level)
103 {
104 GSIState *s = opaque;
105
106 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
107 if (n < ISA_NUM_IRQS) {
108 qemu_set_irq(s->i8259_irq[n], level);
109 }
110 qemu_set_irq(s->ioapic_irq[n], level);
111 }
112
113 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
114 unsigned size)
115 {
116 }
117
118 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
119 {
120 return 0xffffffffffffffffULL;
121 }
122
123 /* MSDOS compatibility mode FPU exception support */
124 static qemu_irq ferr_irq;
125
126 void pc_register_ferr_irq(qemu_irq irq)
127 {
128 ferr_irq = irq;
129 }
130
131 /* XXX: add IGNNE support */
132 void cpu_set_ferr(CPUX86State *s)
133 {
134 qemu_irq_raise(ferr_irq);
135 }
136
137 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
138 unsigned size)
139 {
140 qemu_irq_lower(ferr_irq);
141 }
142
143 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
144 {
145 return 0xffffffffffffffffULL;
146 }
147
148 /* TSC handling */
149 uint64_t cpu_get_tsc(CPUX86State *env)
150 {
151 return cpu_get_ticks();
152 }
153
154 /* SMM support */
155
156 static cpu_set_smm_t smm_set;
157 static void *smm_arg;
158
159 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
160 {
161 assert(smm_set == NULL);
162 assert(smm_arg == NULL);
163 smm_set = callback;
164 smm_arg = arg;
165 }
166
167 void cpu_smm_update(CPUX86State *env)
168 {
169 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
170 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
171 }
172 }
173
174
175 /* IRQ handling */
176 int cpu_get_pic_interrupt(CPUX86State *env)
177 {
178 X86CPU *cpu = x86_env_get_cpu(env);
179 int intno;
180
181 intno = apic_get_interrupt(cpu->apic_state);
182 if (intno >= 0) {
183 return intno;
184 }
185 /* read the irq from the PIC */
186 if (!apic_accept_pic_intr(cpu->apic_state)) {
187 return -1;
188 }
189
190 intno = pic_read_irq(isa_pic);
191 return intno;
192 }
193
194 static void pic_irq_request(void *opaque, int irq, int level)
195 {
196 CPUState *cs = first_cpu;
197 X86CPU *cpu = X86_CPU(cs);
198
199 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
200 if (cpu->apic_state) {
201 CPU_FOREACH(cs) {
202 cpu = X86_CPU(cs);
203 if (apic_accept_pic_intr(cpu->apic_state)) {
204 apic_deliver_pic_intr(cpu->apic_state, level);
205 }
206 }
207 } else {
208 if (level) {
209 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
210 } else {
211 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
212 }
213 }
214 }
215
216 /* PC cmos mappings */
217
218 #define REG_EQUIPMENT_BYTE 0x14
219
220 static int cmos_get_fd_drive_type(FDriveType fd0)
221 {
222 int val;
223
224 switch (fd0) {
225 case FDRIVE_DRV_144:
226 /* 1.44 Mb 3"5 drive */
227 val = 4;
228 break;
229 case FDRIVE_DRV_288:
230 /* 2.88 Mb 3"5 drive */
231 val = 5;
232 break;
233 case FDRIVE_DRV_120:
234 /* 1.2 Mb 5"5 drive */
235 val = 2;
236 break;
237 case FDRIVE_DRV_NONE:
238 default:
239 val = 0;
240 break;
241 }
242 return val;
243 }
244
245 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
246 int16_t cylinders, int8_t heads, int8_t sectors)
247 {
248 rtc_set_memory(s, type_ofs, 47);
249 rtc_set_memory(s, info_ofs, cylinders);
250 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
251 rtc_set_memory(s, info_ofs + 2, heads);
252 rtc_set_memory(s, info_ofs + 3, 0xff);
253 rtc_set_memory(s, info_ofs + 4, 0xff);
254 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
255 rtc_set_memory(s, info_ofs + 6, cylinders);
256 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
257 rtc_set_memory(s, info_ofs + 8, sectors);
258 }
259
260 /* convert boot_device letter to something recognizable by the bios */
261 static int boot_device2nibble(char boot_device)
262 {
263 switch(boot_device) {
264 case 'a':
265 case 'b':
266 return 0x01; /* floppy boot */
267 case 'c':
268 return 0x02; /* hard drive boot */
269 case 'd':
270 return 0x03; /* CD-ROM boot */
271 case 'n':
272 return 0x04; /* Network boot */
273 }
274 return 0;
275 }
276
277 static int set_boot_dev(ISADevice *s, const char *boot_device)
278 {
279 #define PC_MAX_BOOT_DEVICES 3
280 int nbds, bds[3] = { 0, };
281 int i;
282
283 nbds = strlen(boot_device);
284 if (nbds > PC_MAX_BOOT_DEVICES) {
285 error_report("Too many boot devices for PC");
286 return(1);
287 }
288 for (i = 0; i < nbds; i++) {
289 bds[i] = boot_device2nibble(boot_device[i]);
290 if (bds[i] == 0) {
291 error_report("Invalid boot device for PC: '%c'",
292 boot_device[i]);
293 return(1);
294 }
295 }
296 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
297 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
298 return(0);
299 }
300
301 static int pc_boot_set(void *opaque, const char *boot_device)
302 {
303 return set_boot_dev(opaque, boot_device);
304 }
305
306 typedef struct pc_cmos_init_late_arg {
307 ISADevice *rtc_state;
308 BusState *idebus[2];
309 } pc_cmos_init_late_arg;
310
311 static void pc_cmos_init_late(void *opaque)
312 {
313 pc_cmos_init_late_arg *arg = opaque;
314 ISADevice *s = arg->rtc_state;
315 int16_t cylinders;
316 int8_t heads, sectors;
317 int val;
318 int i, trans;
319
320 val = 0;
321 if (ide_get_geometry(arg->idebus[0], 0,
322 &cylinders, &heads, &sectors) >= 0) {
323 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
324 val |= 0xf0;
325 }
326 if (ide_get_geometry(arg->idebus[0], 1,
327 &cylinders, &heads, &sectors) >= 0) {
328 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
329 val |= 0x0f;
330 }
331 rtc_set_memory(s, 0x12, val);
332
333 val = 0;
334 for (i = 0; i < 4; i++) {
335 /* NOTE: ide_get_geometry() returns the physical
336 geometry. It is always such that: 1 <= sects <= 63, 1
337 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
338 geometry can be different if a translation is done. */
339 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
340 &cylinders, &heads, &sectors) >= 0) {
341 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
342 assert((trans & ~3) == 0);
343 val |= trans << (i * 2);
344 }
345 }
346 rtc_set_memory(s, 0x39, val);
347
348 qemu_unregister_reset(pc_cmos_init_late, opaque);
349 }
350
351 typedef struct RTCCPUHotplugArg {
352 Notifier cpu_added_notifier;
353 ISADevice *rtc_state;
354 } RTCCPUHotplugArg;
355
356 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
357 {
358 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
359 cpu_added_notifier);
360 ISADevice *s = arg->rtc_state;
361
362 /* increment the number of CPUs */
363 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
364 }
365
366 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
367 const char *boot_device,
368 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
369 ISADevice *s)
370 {
371 int val, nb, i;
372 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
373 static pc_cmos_init_late_arg arg;
374 static RTCCPUHotplugArg cpu_hotplug_cb;
375
376 /* various important CMOS locations needed by PC/Bochs bios */
377
378 /* memory size */
379 /* base memory (first MiB) */
380 val = MIN(ram_size / 1024, 640);
381 rtc_set_memory(s, 0x15, val);
382 rtc_set_memory(s, 0x16, val >> 8);
383 /* extended memory (next 64MiB) */
384 if (ram_size > 1024 * 1024) {
385 val = (ram_size - 1024 * 1024) / 1024;
386 } else {
387 val = 0;
388 }
389 if (val > 65535)
390 val = 65535;
391 rtc_set_memory(s, 0x17, val);
392 rtc_set_memory(s, 0x18, val >> 8);
393 rtc_set_memory(s, 0x30, val);
394 rtc_set_memory(s, 0x31, val >> 8);
395 /* memory between 16MiB and 4GiB */
396 if (ram_size > 16 * 1024 * 1024) {
397 val = (ram_size - 16 * 1024 * 1024) / 65536;
398 } else {
399 val = 0;
400 }
401 if (val > 65535)
402 val = 65535;
403 rtc_set_memory(s, 0x34, val);
404 rtc_set_memory(s, 0x35, val >> 8);
405 /* memory above 4GiB */
406 val = above_4g_mem_size / 65536;
407 rtc_set_memory(s, 0x5b, val);
408 rtc_set_memory(s, 0x5c, val >> 8);
409 rtc_set_memory(s, 0x5d, val >> 16);
410
411 /* set the number of CPU */
412 rtc_set_memory(s, 0x5f, smp_cpus - 1);
413 /* init CPU hotplug notifier */
414 cpu_hotplug_cb.rtc_state = s;
415 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
416 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
417
418 if (set_boot_dev(s, boot_device)) {
419 exit(1);
420 }
421
422 /* floppy type */
423 if (floppy) {
424 for (i = 0; i < 2; i++) {
425 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
426 }
427 }
428 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
429 cmos_get_fd_drive_type(fd_type[1]);
430 rtc_set_memory(s, 0x10, val);
431
432 val = 0;
433 nb = 0;
434 if (fd_type[0] < FDRIVE_DRV_NONE) {
435 nb++;
436 }
437 if (fd_type[1] < FDRIVE_DRV_NONE) {
438 nb++;
439 }
440 switch (nb) {
441 case 0:
442 break;
443 case 1:
444 val |= 0x01; /* 1 drive, ready for boot */
445 break;
446 case 2:
447 val |= 0x41; /* 2 drives, ready for boot */
448 break;
449 }
450 val |= 0x02; /* FPU is there */
451 val |= 0x04; /* PS/2 mouse installed */
452 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
453
454 /* hard drives */
455 arg.rtc_state = s;
456 arg.idebus[0] = idebus0;
457 arg.idebus[1] = idebus1;
458 qemu_register_reset(pc_cmos_init_late, &arg);
459 }
460
461 #define TYPE_PORT92 "port92"
462 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
463
464 /* port 92 stuff: could be split off */
465 typedef struct Port92State {
466 ISADevice parent_obj;
467
468 MemoryRegion io;
469 uint8_t outport;
470 qemu_irq *a20_out;
471 } Port92State;
472
473 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
474 unsigned size)
475 {
476 Port92State *s = opaque;
477 int oldval = s->outport;
478
479 DPRINTF("port92: write 0x%02x\n", val);
480 s->outport = val;
481 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
482 if ((val & 1) && !(oldval & 1)) {
483 qemu_system_reset_request();
484 }
485 }
486
487 static uint64_t port92_read(void *opaque, hwaddr addr,
488 unsigned size)
489 {
490 Port92State *s = opaque;
491 uint32_t ret;
492
493 ret = s->outport;
494 DPRINTF("port92: read 0x%02x\n", ret);
495 return ret;
496 }
497
498 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
499 {
500 Port92State *s = PORT92(dev);
501
502 s->a20_out = a20_out;
503 }
504
505 static const VMStateDescription vmstate_port92_isa = {
506 .name = "port92",
507 .version_id = 1,
508 .minimum_version_id = 1,
509 .fields = (VMStateField[]) {
510 VMSTATE_UINT8(outport, Port92State),
511 VMSTATE_END_OF_LIST()
512 }
513 };
514
515 static void port92_reset(DeviceState *d)
516 {
517 Port92State *s = PORT92(d);
518
519 s->outport &= ~1;
520 }
521
522 static const MemoryRegionOps port92_ops = {
523 .read = port92_read,
524 .write = port92_write,
525 .impl = {
526 .min_access_size = 1,
527 .max_access_size = 1,
528 },
529 .endianness = DEVICE_LITTLE_ENDIAN,
530 };
531
532 static void port92_initfn(Object *obj)
533 {
534 Port92State *s = PORT92(obj);
535
536 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
537
538 s->outport = 0;
539 }
540
541 static void port92_realizefn(DeviceState *dev, Error **errp)
542 {
543 ISADevice *isadev = ISA_DEVICE(dev);
544 Port92State *s = PORT92(dev);
545
546 isa_register_ioport(isadev, &s->io, 0x92);
547 }
548
549 static void port92_class_initfn(ObjectClass *klass, void *data)
550 {
551 DeviceClass *dc = DEVICE_CLASS(klass);
552
553 dc->realize = port92_realizefn;
554 dc->reset = port92_reset;
555 dc->vmsd = &vmstate_port92_isa;
556 /*
557 * Reason: unlike ordinary ISA devices, this one needs additional
558 * wiring: its A20 output line needs to be wired up by
559 * port92_init().
560 */
561 dc->cannot_instantiate_with_device_add_yet = true;
562 }
563
564 static const TypeInfo port92_info = {
565 .name = TYPE_PORT92,
566 .parent = TYPE_ISA_DEVICE,
567 .instance_size = sizeof(Port92State),
568 .instance_init = port92_initfn,
569 .class_init = port92_class_initfn,
570 };
571
572 static void port92_register_types(void)
573 {
574 type_register_static(&port92_info);
575 }
576
577 type_init(port92_register_types)
578
579 static void handle_a20_line_change(void *opaque, int irq, int level)
580 {
581 X86CPU *cpu = opaque;
582
583 /* XXX: send to all CPUs ? */
584 /* XXX: add logic to handle multiple A20 line sources */
585 x86_cpu_set_a20(cpu, level);
586 }
587
588 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
589 {
590 int index = le32_to_cpu(e820_reserve.count);
591 struct e820_entry *entry;
592
593 if (type != E820_RAM) {
594 /* old FW_CFG_E820_TABLE entry -- reservations only */
595 if (index >= E820_NR_ENTRIES) {
596 return -EBUSY;
597 }
598 entry = &e820_reserve.entry[index++];
599
600 entry->address = cpu_to_le64(address);
601 entry->length = cpu_to_le64(length);
602 entry->type = cpu_to_le32(type);
603
604 e820_reserve.count = cpu_to_le32(index);
605 }
606
607 /* new "etc/e820" file -- include ram too */
608 e820_table = g_realloc(e820_table,
609 sizeof(struct e820_entry) * (e820_entries+1));
610 e820_table[e820_entries].address = cpu_to_le64(address);
611 e820_table[e820_entries].length = cpu_to_le64(length);
612 e820_table[e820_entries].type = cpu_to_le32(type);
613 e820_entries++;
614
615 return e820_entries;
616 }
617
618 int e820_get_num_entries(void)
619 {
620 return e820_entries;
621 }
622
623 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
624 {
625 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
626 *address = le64_to_cpu(e820_table[idx].address);
627 *length = le64_to_cpu(e820_table[idx].length);
628 return true;
629 }
630 return false;
631 }
632
633 /* Calculates the limit to CPU APIC ID values
634 *
635 * This function returns the limit for the APIC ID value, so that all
636 * CPU APIC IDs are < pc_apic_id_limit().
637 *
638 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
639 */
640 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
641 {
642 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
643 }
644
645 static FWCfgState *bochs_bios_init(void)
646 {
647 FWCfgState *fw_cfg;
648 uint8_t *smbios_tables, *smbios_anchor;
649 size_t smbios_tables_len, smbios_anchor_len;
650 uint64_t *numa_fw_cfg;
651 int i, j;
652 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
653
654 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
655 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
656 *
657 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
658 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
659 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
660 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
661 * may see".
662 *
663 * So, this means we must not use max_cpus, here, but the maximum possible
664 * APIC ID value, plus one.
665 *
666 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
667 * the APIC ID, not the "CPU index"
668 */
669 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
670 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
671 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
672 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
673 acpi_tables, acpi_tables_len);
674 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
675
676 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
677 if (smbios_tables) {
678 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
679 smbios_tables, smbios_tables_len);
680 }
681
682 smbios_get_tables(&smbios_tables, &smbios_tables_len,
683 &smbios_anchor, &smbios_anchor_len);
684 if (smbios_anchor) {
685 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
686 smbios_tables, smbios_tables_len);
687 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
688 smbios_anchor, smbios_anchor_len);
689 }
690
691 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
692 &e820_reserve, sizeof(e820_reserve));
693 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
694 sizeof(struct e820_entry) * e820_entries);
695
696 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
697 /* allocate memory for the NUMA channel: one (64bit) word for the number
698 * of nodes, one word for each VCPU->node and one word for each node to
699 * hold the amount of memory.
700 */
701 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
702 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
703 for (i = 0; i < max_cpus; i++) {
704 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
705 assert(apic_id < apic_id_limit);
706 for (j = 0; j < nb_numa_nodes; j++) {
707 if (test_bit(i, numa_info[j].node_cpu)) {
708 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
709 break;
710 }
711 }
712 }
713 for (i = 0; i < nb_numa_nodes; i++) {
714 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem);
715 }
716 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
717 (1 + apic_id_limit + nb_numa_nodes) *
718 sizeof(*numa_fw_cfg));
719
720 return fw_cfg;
721 }
722
723 static long get_file_size(FILE *f)
724 {
725 long where, size;
726
727 /* XXX: on Unix systems, using fstat() probably makes more sense */
728
729 where = ftell(f);
730 fseek(f, 0, SEEK_END);
731 size = ftell(f);
732 fseek(f, where, SEEK_SET);
733
734 return size;
735 }
736
737 static void load_linux(FWCfgState *fw_cfg,
738 const char *kernel_filename,
739 const char *initrd_filename,
740 const char *kernel_cmdline,
741 hwaddr max_ram_size)
742 {
743 uint16_t protocol;
744 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
745 uint32_t initrd_max;
746 uint8_t header[8192], *setup, *kernel, *initrd_data;
747 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
748 FILE *f;
749 char *vmode;
750
751 /* Align to 16 bytes as a paranoia measure */
752 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
753
754 /* load the kernel header */
755 f = fopen(kernel_filename, "rb");
756 if (!f || !(kernel_size = get_file_size(f)) ||
757 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
758 MIN(ARRAY_SIZE(header), kernel_size)) {
759 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
760 kernel_filename, strerror(errno));
761 exit(1);
762 }
763
764 /* kernel protocol version */
765 #if 0
766 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
767 #endif
768 if (ldl_p(header+0x202) == 0x53726448) {
769 protocol = lduw_p(header+0x206);
770 } else {
771 /* This looks like a multiboot kernel. If it is, let's stop
772 treating it like a Linux kernel. */
773 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
774 kernel_cmdline, kernel_size, header)) {
775 return;
776 }
777 protocol = 0;
778 }
779
780 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
781 /* Low kernel */
782 real_addr = 0x90000;
783 cmdline_addr = 0x9a000 - cmdline_size;
784 prot_addr = 0x10000;
785 } else if (protocol < 0x202) {
786 /* High but ancient kernel */
787 real_addr = 0x90000;
788 cmdline_addr = 0x9a000 - cmdline_size;
789 prot_addr = 0x100000;
790 } else {
791 /* High and recent kernel */
792 real_addr = 0x10000;
793 cmdline_addr = 0x20000;
794 prot_addr = 0x100000;
795 }
796
797 #if 0
798 fprintf(stderr,
799 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
800 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
801 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
802 real_addr,
803 cmdline_addr,
804 prot_addr);
805 #endif
806
807 /* highest address for loading the initrd */
808 if (protocol >= 0x203) {
809 initrd_max = ldl_p(header+0x22c);
810 } else {
811 initrd_max = 0x37ffffff;
812 }
813
814 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
815 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
816
817 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
818 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
819 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
820
821 if (protocol >= 0x202) {
822 stl_p(header+0x228, cmdline_addr);
823 } else {
824 stw_p(header+0x20, 0xA33F);
825 stw_p(header+0x22, cmdline_addr-real_addr);
826 }
827
828 /* handle vga= parameter */
829 vmode = strstr(kernel_cmdline, "vga=");
830 if (vmode) {
831 unsigned int video_mode;
832 /* skip "vga=" */
833 vmode += 4;
834 if (!strncmp(vmode, "normal", 6)) {
835 video_mode = 0xffff;
836 } else if (!strncmp(vmode, "ext", 3)) {
837 video_mode = 0xfffe;
838 } else if (!strncmp(vmode, "ask", 3)) {
839 video_mode = 0xfffd;
840 } else {
841 video_mode = strtol(vmode, NULL, 0);
842 }
843 stw_p(header+0x1fa, video_mode);
844 }
845
846 /* loader type */
847 /* High nybble = B reserved for QEMU; low nybble is revision number.
848 If this code is substantially changed, you may want to consider
849 incrementing the revision. */
850 if (protocol >= 0x200) {
851 header[0x210] = 0xB0;
852 }
853 /* heap */
854 if (protocol >= 0x201) {
855 header[0x211] |= 0x80; /* CAN_USE_HEAP */
856 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
857 }
858
859 /* load initrd */
860 if (initrd_filename) {
861 if (protocol < 0x200) {
862 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
863 exit(1);
864 }
865
866 initrd_size = get_image_size(initrd_filename);
867 if (initrd_size < 0) {
868 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
869 initrd_filename, strerror(errno));
870 exit(1);
871 }
872
873 initrd_addr = (initrd_max-initrd_size) & ~4095;
874
875 initrd_data = g_malloc(initrd_size);
876 load_image(initrd_filename, initrd_data);
877
878 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
879 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
880 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
881
882 stl_p(header+0x218, initrd_addr);
883 stl_p(header+0x21c, initrd_size);
884 }
885
886 /* load kernel and setup */
887 setup_size = header[0x1f1];
888 if (setup_size == 0) {
889 setup_size = 4;
890 }
891 setup_size = (setup_size+1)*512;
892 kernel_size -= setup_size;
893
894 setup = g_malloc(setup_size);
895 kernel = g_malloc(kernel_size);
896 fseek(f, 0, SEEK_SET);
897 if (fread(setup, 1, setup_size, f) != setup_size) {
898 fprintf(stderr, "fread() failed\n");
899 exit(1);
900 }
901 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
902 fprintf(stderr, "fread() failed\n");
903 exit(1);
904 }
905 fclose(f);
906 memcpy(setup, header, MIN(sizeof(header), setup_size));
907
908 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
909 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
910 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
911
912 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
913 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
914 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
915
916 option_rom[nb_option_roms].name = "linuxboot.bin";
917 option_rom[nb_option_roms].bootindex = 0;
918 nb_option_roms++;
919 }
920
921 #define NE2000_NB_MAX 6
922
923 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
924 0x280, 0x380 };
925 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
926
927 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
928 {
929 static int nb_ne2k = 0;
930
931 if (nb_ne2k == NE2000_NB_MAX)
932 return;
933 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
934 ne2000_irq[nb_ne2k], nd);
935 nb_ne2k++;
936 }
937
938 DeviceState *cpu_get_current_apic(void)
939 {
940 if (current_cpu) {
941 X86CPU *cpu = X86_CPU(current_cpu);
942 return cpu->apic_state;
943 } else {
944 return NULL;
945 }
946 }
947
948 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
949 {
950 X86CPU *cpu = opaque;
951
952 if (level) {
953 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
954 }
955 }
956
957 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
958 DeviceState *icc_bridge, Error **errp)
959 {
960 X86CPU *cpu;
961 Error *local_err = NULL;
962
963 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
964 if (local_err != NULL) {
965 error_propagate(errp, local_err);
966 return NULL;
967 }
968
969 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
970 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
971
972 if (local_err) {
973 error_propagate(errp, local_err);
974 object_unref(OBJECT(cpu));
975 cpu = NULL;
976 }
977 return cpu;
978 }
979
980 static const char *current_cpu_model;
981
982 void pc_hot_add_cpu(const int64_t id, Error **errp)
983 {
984 DeviceState *icc_bridge;
985 int64_t apic_id = x86_cpu_apic_id_from_index(id);
986
987 if (id < 0) {
988 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
989 return;
990 }
991
992 if (cpu_exists(apic_id)) {
993 error_setg(errp, "Unable to add CPU: %" PRIi64
994 ", it already exists", id);
995 return;
996 }
997
998 if (id >= max_cpus) {
999 error_setg(errp, "Unable to add CPU: %" PRIi64
1000 ", max allowed: %d", id, max_cpus - 1);
1001 return;
1002 }
1003
1004 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1005 error_setg(errp, "Unable to add CPU: %" PRIi64
1006 ", resulting APIC ID (%" PRIi64 ") is too large",
1007 id, apic_id);
1008 return;
1009 }
1010
1011 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
1012 TYPE_ICC_BRIDGE, NULL));
1013 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
1014 }
1015
1016 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1017 {
1018 int i;
1019 X86CPU *cpu = NULL;
1020 Error *error = NULL;
1021 unsigned long apic_id_limit;
1022
1023 /* init CPUs */
1024 if (cpu_model == NULL) {
1025 #ifdef TARGET_X86_64
1026 cpu_model = "qemu64";
1027 #else
1028 cpu_model = "qemu32";
1029 #endif
1030 }
1031 current_cpu_model = cpu_model;
1032
1033 apic_id_limit = pc_apic_id_limit(max_cpus);
1034 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1035 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1036 apic_id_limit - 1);
1037 exit(1);
1038 }
1039
1040 for (i = 0; i < smp_cpus; i++) {
1041 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1042 icc_bridge, &error);
1043 if (error) {
1044 error_report("%s", error_get_pretty(error));
1045 error_free(error);
1046 exit(1);
1047 }
1048 }
1049
1050 /* map APIC MMIO area if CPU has APIC */
1051 if (cpu && cpu->apic_state) {
1052 /* XXX: what if the base changes? */
1053 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1054 APIC_DEFAULT_ADDRESS, 0x1000);
1055 }
1056
1057 /* tell smbios about cpuid version and features */
1058 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1059 }
1060
1061 /* pci-info ROM file. Little endian format */
1062 typedef struct PcRomPciInfo {
1063 uint64_t w32_min;
1064 uint64_t w32_max;
1065 uint64_t w64_min;
1066 uint64_t w64_max;
1067 } PcRomPciInfo;
1068
1069 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1070 {
1071 PcRomPciInfo *info;
1072 Object *pci_info;
1073 bool ambiguous = false;
1074
1075 if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1076 return;
1077 }
1078 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1079 g_assert(!ambiguous);
1080 if (!pci_info) {
1081 return;
1082 }
1083
1084 info = g_malloc(sizeof *info);
1085 info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
1086 PCI_HOST_PROP_PCI_HOLE_START, NULL));
1087 info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
1088 PCI_HOST_PROP_PCI_HOLE_END, NULL));
1089 info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
1090 PCI_HOST_PROP_PCI_HOLE64_START, NULL));
1091 info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
1092 PCI_HOST_PROP_PCI_HOLE64_END, NULL));
1093 /* Pass PCI hole info to guest via a side channel.
1094 * Required so guest PCI enumeration does the right thing. */
1095 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1096 }
1097
1098 typedef struct PcGuestInfoState {
1099 PcGuestInfo info;
1100 Notifier machine_done;
1101 } PcGuestInfoState;
1102
1103 static
1104 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1105 {
1106 PcGuestInfoState *guest_info_state = container_of(notifier,
1107 PcGuestInfoState,
1108 machine_done);
1109 pc_fw_cfg_guest_info(&guest_info_state->info);
1110 acpi_setup(&guest_info_state->info);
1111 }
1112
1113 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1114 ram_addr_t above_4g_mem_size)
1115 {
1116 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1117 PcGuestInfo *guest_info = &guest_info_state->info;
1118 int i, j;
1119
1120 guest_info->ram_size_below_4g = below_4g_mem_size;
1121 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1122 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1123 guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1124 guest_info->numa_nodes = nb_numa_nodes;
1125 guest_info->node_mem = g_malloc0(guest_info->numa_nodes *
1126 sizeof *guest_info->node_mem);
1127 for (i = 0; i < nb_numa_nodes; i++) {
1128 guest_info->node_mem[i] = numa_info[i].node_mem;
1129 }
1130
1131 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1132 sizeof *guest_info->node_cpu);
1133
1134 for (i = 0; i < max_cpus; i++) {
1135 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1136 assert(apic_id < guest_info->apic_id_limit);
1137 for (j = 0; j < nb_numa_nodes; j++) {
1138 if (test_bit(i, numa_info[j].node_cpu)) {
1139 guest_info->node_cpu[apic_id] = j;
1140 break;
1141 }
1142 }
1143 }
1144
1145 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1146 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1147 return guest_info;
1148 }
1149
1150 /* setup pci memory address space mapping into system address space */
1151 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1152 MemoryRegion *pci_address_space)
1153 {
1154 /* Set to lower priority than RAM */
1155 memory_region_add_subregion_overlap(system_memory, 0x0,
1156 pci_address_space, -1);
1157 }
1158
1159 void pc_acpi_init(const char *default_dsdt)
1160 {
1161 char *filename;
1162
1163 if (acpi_tables != NULL) {
1164 /* manually set via -acpitable, leave it alone */
1165 return;
1166 }
1167
1168 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1169 if (filename == NULL) {
1170 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1171 } else {
1172 char *arg;
1173 QemuOpts *opts;
1174 Error *err = NULL;
1175
1176 arg = g_strdup_printf("file=%s", filename);
1177
1178 /* creates a deep copy of "arg" */
1179 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1180 g_assert(opts != NULL);
1181
1182 acpi_table_add_builtin(opts, &err);
1183 if (err) {
1184 error_report("WARNING: failed to load %s: %s", filename,
1185 error_get_pretty(err));
1186 error_free(err);
1187 }
1188 g_free(arg);
1189 g_free(filename);
1190 }
1191 }
1192
1193 FWCfgState *pc_memory_init(MachineState *machine,
1194 MemoryRegion *system_memory,
1195 ram_addr_t below_4g_mem_size,
1196 ram_addr_t above_4g_mem_size,
1197 MemoryRegion *rom_memory,
1198 MemoryRegion **ram_memory,
1199 PcGuestInfo *guest_info)
1200 {
1201 int linux_boot, i;
1202 MemoryRegion *ram, *option_rom_mr;
1203 MemoryRegion *ram_below_4g, *ram_above_4g;
1204 FWCfgState *fw_cfg;
1205 PCMachineState *pcms = PC_MACHINE(machine);
1206
1207 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size);
1208
1209 linux_boot = (machine->kernel_filename != NULL);
1210
1211 /* Allocate RAM. We allocate it as a single memory region and use
1212 * aliases to address portions of it, mostly for backwards compatibility
1213 * with older qemus that used qemu_ram_alloc().
1214 */
1215 ram = g_malloc(sizeof(*ram));
1216 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1217 machine->ram_size);
1218 *ram_memory = ram;
1219 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1220 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1221 0, below_4g_mem_size);
1222 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1223 e820_add_entry(0, below_4g_mem_size, E820_RAM);
1224 if (above_4g_mem_size > 0) {
1225 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1226 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1227 below_4g_mem_size, above_4g_mem_size);
1228 memory_region_add_subregion(system_memory, 0x100000000ULL,
1229 ram_above_4g);
1230 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1231 }
1232
1233 if (!guest_info->has_reserved_memory &&
1234 (machine->ram_slots ||
1235 (machine->maxram_size > machine->ram_size))) {
1236 MachineClass *mc = MACHINE_GET_CLASS(machine);
1237
1238 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1239 mc->name);
1240 exit(EXIT_FAILURE);
1241 }
1242
1243 /* initialize hotplug memory address space */
1244 if (guest_info->has_reserved_memory &&
1245 (machine->ram_size < machine->maxram_size)) {
1246 ram_addr_t hotplug_mem_size =
1247 machine->maxram_size - machine->ram_size;
1248
1249 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1250 error_report("unsupported amount of memory slots: %"PRIu64,
1251 machine->ram_slots);
1252 exit(EXIT_FAILURE);
1253 }
1254
1255 pcms->hotplug_memory_base =
1256 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
1257
1258 if ((pcms->hotplug_memory_base + hotplug_mem_size) <
1259 hotplug_mem_size) {
1260 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1261 machine->maxram_size);
1262 exit(EXIT_FAILURE);
1263 }
1264
1265 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms),
1266 "hotplug-memory", hotplug_mem_size);
1267 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base,
1268 &pcms->hotplug_memory);
1269 }
1270
1271 /* Initialize PC system firmware */
1272 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1273
1274 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1275 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1276 vmstate_register_ram_global(option_rom_mr);
1277 memory_region_add_subregion_overlap(rom_memory,
1278 PC_ROM_MIN_VGA,
1279 option_rom_mr,
1280 1);
1281
1282 fw_cfg = bochs_bios_init();
1283 rom_set_fw(fw_cfg);
1284
1285 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) {
1286 uint64_t *val = g_malloc(sizeof(*val));
1287 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30));
1288 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1289 }
1290
1291 if (linux_boot) {
1292 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename,
1293 machine->kernel_cmdline, below_4g_mem_size);
1294 }
1295
1296 for (i = 0; i < nb_option_roms; i++) {
1297 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1298 }
1299 guest_info->fw_cfg = fw_cfg;
1300 return fw_cfg;
1301 }
1302
1303 qemu_irq *pc_allocate_cpu_irq(void)
1304 {
1305 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1306 }
1307
1308 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1309 {
1310 DeviceState *dev = NULL;
1311
1312 if (pci_bus) {
1313 PCIDevice *pcidev = pci_vga_init(pci_bus);
1314 dev = pcidev ? &pcidev->qdev : NULL;
1315 } else if (isa_bus) {
1316 ISADevice *isadev = isa_vga_init(isa_bus);
1317 dev = isadev ? DEVICE(isadev) : NULL;
1318 }
1319 return dev;
1320 }
1321
1322 static void cpu_request_exit(void *opaque, int irq, int level)
1323 {
1324 CPUState *cpu = current_cpu;
1325
1326 if (cpu && level) {
1327 cpu_exit(cpu);
1328 }
1329 }
1330
1331 static const MemoryRegionOps ioport80_io_ops = {
1332 .write = ioport80_write,
1333 .read = ioport80_read,
1334 .endianness = DEVICE_NATIVE_ENDIAN,
1335 .impl = {
1336 .min_access_size = 1,
1337 .max_access_size = 1,
1338 },
1339 };
1340
1341 static const MemoryRegionOps ioportF0_io_ops = {
1342 .write = ioportF0_write,
1343 .read = ioportF0_read,
1344 .endianness = DEVICE_NATIVE_ENDIAN,
1345 .impl = {
1346 .min_access_size = 1,
1347 .max_access_size = 1,
1348 },
1349 };
1350
1351 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1352 ISADevice **rtc_state,
1353 ISADevice **floppy,
1354 bool no_vmport,
1355 uint32 hpet_irqs)
1356 {
1357 int i;
1358 DriveInfo *fd[MAX_FD];
1359 DeviceState *hpet = NULL;
1360 int pit_isa_irq = 0;
1361 qemu_irq pit_alt_irq = NULL;
1362 qemu_irq rtc_irq = NULL;
1363 qemu_irq *a20_line;
1364 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1365 qemu_irq *cpu_exit_irq;
1366 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1367 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1368
1369 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1370 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1371
1372 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1373 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1374
1375 /*
1376 * Check if an HPET shall be created.
1377 *
1378 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1379 * when the HPET wants to take over. Thus we have to disable the latter.
1380 */
1381 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1382 /* In order to set property, here not using sysbus_try_create_simple */
1383 hpet = qdev_try_create(NULL, TYPE_HPET);
1384 if (hpet) {
1385 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1386 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1387 * IRQ8 and IRQ2.
1388 */
1389 uint8_t compat = object_property_get_int(OBJECT(hpet),
1390 HPET_INTCAP, NULL);
1391 if (!compat) {
1392 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1393 }
1394 qdev_init_nofail(hpet);
1395 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1396
1397 for (i = 0; i < GSI_NUM_PINS; i++) {
1398 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1399 }
1400 pit_isa_irq = -1;
1401 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1402 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1403 }
1404 }
1405 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1406
1407 qemu_register_boot_set(pc_boot_set, *rtc_state);
1408
1409 if (!xen_enabled()) {
1410 if (kvm_irqchip_in_kernel()) {
1411 pit = kvm_pit_init(isa_bus, 0x40);
1412 } else {
1413 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1414 }
1415 if (hpet) {
1416 /* connect PIT to output control line of the HPET */
1417 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1418 }
1419 pcspk_init(isa_bus, pit);
1420 }
1421
1422 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1423 if (serial_hds[i]) {
1424 serial_isa_init(isa_bus, i, serial_hds[i]);
1425 }
1426 }
1427
1428 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1429 if (parallel_hds[i]) {
1430 parallel_init(isa_bus, i, parallel_hds[i]);
1431 }
1432 }
1433
1434 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1435 i8042 = isa_create_simple(isa_bus, "i8042");
1436 i8042_setup_a20_line(i8042, &a20_line[0]);
1437 if (!no_vmport) {
1438 vmport_init(isa_bus);
1439 vmmouse = isa_try_create(isa_bus, "vmmouse");
1440 } else {
1441 vmmouse = NULL;
1442 }
1443 if (vmmouse) {
1444 DeviceState *dev = DEVICE(vmmouse);
1445 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1446 qdev_init_nofail(dev);
1447 }
1448 port92 = isa_create_simple(isa_bus, "port92");
1449 port92_init(port92, &a20_line[1]);
1450
1451 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1452 DMA_init(0, cpu_exit_irq);
1453
1454 for(i = 0; i < MAX_FD; i++) {
1455 fd[i] = drive_get(IF_FLOPPY, 0, i);
1456 }
1457 *floppy = fdctrl_init_isa(isa_bus, fd);
1458 }
1459
1460 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1461 {
1462 int i;
1463
1464 for (i = 0; i < nb_nics; i++) {
1465 NICInfo *nd = &nd_table[i];
1466
1467 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1468 pc_init_ne2k_isa(isa_bus, nd);
1469 } else {
1470 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1471 }
1472 }
1473 }
1474
1475 void pc_pci_device_init(PCIBus *pci_bus)
1476 {
1477 int max_bus;
1478 int bus;
1479
1480 max_bus = drive_get_max_bus(IF_SCSI);
1481 for (bus = 0; bus <= max_bus; bus++) {
1482 pci_create_simple(pci_bus, -1, "lsi53c895a");
1483 }
1484 }
1485
1486 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1487 {
1488 DeviceState *dev;
1489 SysBusDevice *d;
1490 unsigned int i;
1491
1492 if (kvm_irqchip_in_kernel()) {
1493 dev = qdev_create(NULL, "kvm-ioapic");
1494 } else {
1495 dev = qdev_create(NULL, "ioapic");
1496 }
1497 if (parent_name) {
1498 object_property_add_child(object_resolve_path(parent_name, NULL),
1499 "ioapic", OBJECT(dev), NULL);
1500 }
1501 qdev_init_nofail(dev);
1502 d = SYS_BUS_DEVICE(dev);
1503 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1504
1505 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1506 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1507 }
1508 }
1509
1510 static void pc_generic_machine_class_init(ObjectClass *oc, void *data)
1511 {
1512 MachineClass *mc = MACHINE_CLASS(oc);
1513 QEMUMachine *qm = data;
1514
1515 mc->name = qm->name;
1516 mc->alias = qm->alias;
1517 mc->desc = qm->desc;
1518 mc->init = qm->init;
1519 mc->reset = qm->reset;
1520 mc->hot_add_cpu = qm->hot_add_cpu;
1521 mc->kvm_type = qm->kvm_type;
1522 mc->block_default_type = qm->block_default_type;
1523 mc->max_cpus = qm->max_cpus;
1524 mc->no_serial = qm->no_serial;
1525 mc->no_parallel = qm->no_parallel;
1526 mc->use_virtcon = qm->use_virtcon;
1527 mc->use_sclp = qm->use_sclp;
1528 mc->no_floppy = qm->no_floppy;
1529 mc->no_cdrom = qm->no_cdrom;
1530 mc->no_sdcard = qm->no_sdcard;
1531 mc->is_default = qm->is_default;
1532 mc->default_machine_opts = qm->default_machine_opts;
1533 mc->default_boot_order = qm->default_boot_order;
1534 mc->compat_props = qm->compat_props;
1535 mc->hw_version = qm->hw_version;
1536 }
1537
1538 void qemu_register_pc_machine(QEMUMachine *m)
1539 {
1540 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL);
1541 TypeInfo ti = {
1542 .name = name,
1543 .parent = TYPE_PC_MACHINE,
1544 .class_init = pc_generic_machine_class_init,
1545 .class_data = (void *)m,
1546 };
1547
1548 type_register(&ti);
1549 g_free(name);
1550 }
1551
1552 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1553 DeviceState *dev, Error **errp)
1554 {
1555 int slot;
1556 HotplugHandlerClass *hhc;
1557 Error *local_err = NULL;
1558 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1559 MachineState *machine = MACHINE(hotplug_dev);
1560 PCDIMMDevice *dimm = PC_DIMM(dev);
1561 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1562 MemoryRegion *mr = ddc->get_memory_region(dimm);
1563 uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
1564 &local_err);
1565 if (local_err) {
1566 goto out;
1567 }
1568
1569 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base,
1570 memory_region_size(&pcms->hotplug_memory),
1571 !addr ? NULL : &addr,
1572 memory_region_size(mr), &local_err);
1573 if (local_err) {
1574 goto out;
1575 }
1576
1577 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err);
1578 if (local_err) {
1579 goto out;
1580 }
1581 trace_mhp_pc_dimm_assigned_address(addr);
1582
1583 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err);
1584 if (local_err) {
1585 goto out;
1586 }
1587
1588 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot,
1589 machine->ram_slots, &local_err);
1590 if (local_err) {
1591 goto out;
1592 }
1593 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err);
1594 if (local_err) {
1595 goto out;
1596 }
1597 trace_mhp_pc_dimm_assigned_slot(slot);
1598
1599 if (!pcms->acpi_dev) {
1600 error_setg(&local_err,
1601 "memory hotplug is not enabled: missing acpi device");
1602 goto out;
1603 }
1604
1605 memory_region_add_subregion(&pcms->hotplug_memory,
1606 addr - pcms->hotplug_memory_base, mr);
1607 vmstate_register_ram(mr, dev);
1608
1609 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1610 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1611 out:
1612 error_propagate(errp, local_err);
1613 }
1614
1615 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1616 DeviceState *dev, Error **errp)
1617 {
1618 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1619 pc_dimm_plug(hotplug_dev, dev, errp);
1620 }
1621 }
1622
1623 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
1624 DeviceState *dev)
1625 {
1626 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1627
1628 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1629 return HOTPLUG_HANDLER(machine);
1630 }
1631
1632 return pcmc->get_hotplug_handler ?
1633 pcmc->get_hotplug_handler(machine, dev) : NULL;
1634 }
1635
1636 static void
1637 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque,
1638 const char *name, Error **errp)
1639 {
1640 PCMachineState *pcms = PC_MACHINE(obj);
1641 int64_t value = memory_region_size(&pcms->hotplug_memory);
1642
1643 visit_type_int(v, &value, name, errp);
1644 }
1645
1646 static void pc_machine_initfn(Object *obj)
1647 {
1648 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int",
1649 pc_machine_get_hotplug_memory_region_size,
1650 NULL, NULL, NULL, NULL);
1651 }
1652
1653 static void pc_machine_class_init(ObjectClass *oc, void *data)
1654 {
1655 MachineClass *mc = MACHINE_CLASS(oc);
1656 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1657 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1658
1659 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
1660 mc->get_hotplug_handler = pc_get_hotpug_handler;
1661 hc->plug = pc_machine_device_plug_cb;
1662 }
1663
1664 static const TypeInfo pc_machine_info = {
1665 .name = TYPE_PC_MACHINE,
1666 .parent = TYPE_MACHINE,
1667 .abstract = true,
1668 .instance_size = sizeof(PCMachineState),
1669 .instance_init = pc_machine_initfn,
1670 .class_size = sizeof(PCMachineClass),
1671 .class_init = pc_machine_class_init,
1672 .interfaces = (InterfaceInfo[]) {
1673 { TYPE_HOTPLUG_HANDLER },
1674 { }
1675 },
1676 };
1677
1678 static void pc_machine_register_types(void)
1679 {
1680 type_register_static(&pc_machine_info);
1681 }
1682
1683 type_init(pc_machine_register_types)