pc: add memory hotplug handler to PC_MACHINE
[qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
29 #include "hw/ide.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
36 #include "elf.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
61 #include "hw/mem/pc-dimm.h"
62
63 /* debug PC/ISA interrupts */
64 //#define DEBUG_IRQ
65
66 #ifdef DEBUG_IRQ
67 #define DPRINTF(fmt, ...) \
68 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
69 #else
70 #define DPRINTF(fmt, ...)
71 #endif
72
73 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
74 #define ACPI_DATA_SIZE 0x10000
75 #define BIOS_CFG_IOPORT 0x510
76 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
77 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
78 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
79 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
80 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
81
82 #define E820_NR_ENTRIES 16
83
84 struct e820_entry {
85 uint64_t address;
86 uint64_t length;
87 uint32_t type;
88 } QEMU_PACKED __attribute((__aligned__(4)));
89
90 struct e820_table {
91 uint32_t count;
92 struct e820_entry entry[E820_NR_ENTRIES];
93 } QEMU_PACKED __attribute((__aligned__(4)));
94
95 static struct e820_table e820_reserve;
96 static struct e820_entry *e820_table;
97 static unsigned e820_entries;
98 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
99
100 void gsi_handler(void *opaque, int n, int level)
101 {
102 GSIState *s = opaque;
103
104 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
105 if (n < ISA_NUM_IRQS) {
106 qemu_set_irq(s->i8259_irq[n], level);
107 }
108 qemu_set_irq(s->ioapic_irq[n], level);
109 }
110
111 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
112 unsigned size)
113 {
114 }
115
116 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
117 {
118 return 0xffffffffffffffffULL;
119 }
120
121 /* MSDOS compatibility mode FPU exception support */
122 static qemu_irq ferr_irq;
123
124 void pc_register_ferr_irq(qemu_irq irq)
125 {
126 ferr_irq = irq;
127 }
128
129 /* XXX: add IGNNE support */
130 void cpu_set_ferr(CPUX86State *s)
131 {
132 qemu_irq_raise(ferr_irq);
133 }
134
135 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
136 unsigned size)
137 {
138 qemu_irq_lower(ferr_irq);
139 }
140
141 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
142 {
143 return 0xffffffffffffffffULL;
144 }
145
146 /* TSC handling */
147 uint64_t cpu_get_tsc(CPUX86State *env)
148 {
149 return cpu_get_ticks();
150 }
151
152 /* SMM support */
153
154 static cpu_set_smm_t smm_set;
155 static void *smm_arg;
156
157 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
158 {
159 assert(smm_set == NULL);
160 assert(smm_arg == NULL);
161 smm_set = callback;
162 smm_arg = arg;
163 }
164
165 void cpu_smm_update(CPUX86State *env)
166 {
167 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
168 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
169 }
170 }
171
172
173 /* IRQ handling */
174 int cpu_get_pic_interrupt(CPUX86State *env)
175 {
176 X86CPU *cpu = x86_env_get_cpu(env);
177 int intno;
178
179 intno = apic_get_interrupt(cpu->apic_state);
180 if (intno >= 0) {
181 return intno;
182 }
183 /* read the irq from the PIC */
184 if (!apic_accept_pic_intr(cpu->apic_state)) {
185 return -1;
186 }
187
188 intno = pic_read_irq(isa_pic);
189 return intno;
190 }
191
192 static void pic_irq_request(void *opaque, int irq, int level)
193 {
194 CPUState *cs = first_cpu;
195 X86CPU *cpu = X86_CPU(cs);
196
197 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
198 if (cpu->apic_state) {
199 CPU_FOREACH(cs) {
200 cpu = X86_CPU(cs);
201 if (apic_accept_pic_intr(cpu->apic_state)) {
202 apic_deliver_pic_intr(cpu->apic_state, level);
203 }
204 }
205 } else {
206 if (level) {
207 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
208 } else {
209 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
210 }
211 }
212 }
213
214 /* PC cmos mappings */
215
216 #define REG_EQUIPMENT_BYTE 0x14
217
218 static int cmos_get_fd_drive_type(FDriveType fd0)
219 {
220 int val;
221
222 switch (fd0) {
223 case FDRIVE_DRV_144:
224 /* 1.44 Mb 3"5 drive */
225 val = 4;
226 break;
227 case FDRIVE_DRV_288:
228 /* 2.88 Mb 3"5 drive */
229 val = 5;
230 break;
231 case FDRIVE_DRV_120:
232 /* 1.2 Mb 5"5 drive */
233 val = 2;
234 break;
235 case FDRIVE_DRV_NONE:
236 default:
237 val = 0;
238 break;
239 }
240 return val;
241 }
242
243 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
244 int16_t cylinders, int8_t heads, int8_t sectors)
245 {
246 rtc_set_memory(s, type_ofs, 47);
247 rtc_set_memory(s, info_ofs, cylinders);
248 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
249 rtc_set_memory(s, info_ofs + 2, heads);
250 rtc_set_memory(s, info_ofs + 3, 0xff);
251 rtc_set_memory(s, info_ofs + 4, 0xff);
252 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
253 rtc_set_memory(s, info_ofs + 6, cylinders);
254 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
255 rtc_set_memory(s, info_ofs + 8, sectors);
256 }
257
258 /* convert boot_device letter to something recognizable by the bios */
259 static int boot_device2nibble(char boot_device)
260 {
261 switch(boot_device) {
262 case 'a':
263 case 'b':
264 return 0x01; /* floppy boot */
265 case 'c':
266 return 0x02; /* hard drive boot */
267 case 'd':
268 return 0x03; /* CD-ROM boot */
269 case 'n':
270 return 0x04; /* Network boot */
271 }
272 return 0;
273 }
274
275 static int set_boot_dev(ISADevice *s, const char *boot_device)
276 {
277 #define PC_MAX_BOOT_DEVICES 3
278 int nbds, bds[3] = { 0, };
279 int i;
280
281 nbds = strlen(boot_device);
282 if (nbds > PC_MAX_BOOT_DEVICES) {
283 error_report("Too many boot devices for PC");
284 return(1);
285 }
286 for (i = 0; i < nbds; i++) {
287 bds[i] = boot_device2nibble(boot_device[i]);
288 if (bds[i] == 0) {
289 error_report("Invalid boot device for PC: '%c'",
290 boot_device[i]);
291 return(1);
292 }
293 }
294 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
295 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
296 return(0);
297 }
298
299 static int pc_boot_set(void *opaque, const char *boot_device)
300 {
301 return set_boot_dev(opaque, boot_device);
302 }
303
304 typedef struct pc_cmos_init_late_arg {
305 ISADevice *rtc_state;
306 BusState *idebus[2];
307 } pc_cmos_init_late_arg;
308
309 static void pc_cmos_init_late(void *opaque)
310 {
311 pc_cmos_init_late_arg *arg = opaque;
312 ISADevice *s = arg->rtc_state;
313 int16_t cylinders;
314 int8_t heads, sectors;
315 int val;
316 int i, trans;
317
318 val = 0;
319 if (ide_get_geometry(arg->idebus[0], 0,
320 &cylinders, &heads, &sectors) >= 0) {
321 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
322 val |= 0xf0;
323 }
324 if (ide_get_geometry(arg->idebus[0], 1,
325 &cylinders, &heads, &sectors) >= 0) {
326 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
327 val |= 0x0f;
328 }
329 rtc_set_memory(s, 0x12, val);
330
331 val = 0;
332 for (i = 0; i < 4; i++) {
333 /* NOTE: ide_get_geometry() returns the physical
334 geometry. It is always such that: 1 <= sects <= 63, 1
335 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
336 geometry can be different if a translation is done. */
337 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
338 &cylinders, &heads, &sectors) >= 0) {
339 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
340 assert((trans & ~3) == 0);
341 val |= trans << (i * 2);
342 }
343 }
344 rtc_set_memory(s, 0x39, val);
345
346 qemu_unregister_reset(pc_cmos_init_late, opaque);
347 }
348
349 typedef struct RTCCPUHotplugArg {
350 Notifier cpu_added_notifier;
351 ISADevice *rtc_state;
352 } RTCCPUHotplugArg;
353
354 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
355 {
356 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
357 cpu_added_notifier);
358 ISADevice *s = arg->rtc_state;
359
360 /* increment the number of CPUs */
361 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
362 }
363
364 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
365 const char *boot_device,
366 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
367 ISADevice *s)
368 {
369 int val, nb, i;
370 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
371 static pc_cmos_init_late_arg arg;
372 static RTCCPUHotplugArg cpu_hotplug_cb;
373
374 /* various important CMOS locations needed by PC/Bochs bios */
375
376 /* memory size */
377 /* base memory (first MiB) */
378 val = MIN(ram_size / 1024, 640);
379 rtc_set_memory(s, 0x15, val);
380 rtc_set_memory(s, 0x16, val >> 8);
381 /* extended memory (next 64MiB) */
382 if (ram_size > 1024 * 1024) {
383 val = (ram_size - 1024 * 1024) / 1024;
384 } else {
385 val = 0;
386 }
387 if (val > 65535)
388 val = 65535;
389 rtc_set_memory(s, 0x17, val);
390 rtc_set_memory(s, 0x18, val >> 8);
391 rtc_set_memory(s, 0x30, val);
392 rtc_set_memory(s, 0x31, val >> 8);
393 /* memory between 16MiB and 4GiB */
394 if (ram_size > 16 * 1024 * 1024) {
395 val = (ram_size - 16 * 1024 * 1024) / 65536;
396 } else {
397 val = 0;
398 }
399 if (val > 65535)
400 val = 65535;
401 rtc_set_memory(s, 0x34, val);
402 rtc_set_memory(s, 0x35, val >> 8);
403 /* memory above 4GiB */
404 val = above_4g_mem_size / 65536;
405 rtc_set_memory(s, 0x5b, val);
406 rtc_set_memory(s, 0x5c, val >> 8);
407 rtc_set_memory(s, 0x5d, val >> 16);
408
409 /* set the number of CPU */
410 rtc_set_memory(s, 0x5f, smp_cpus - 1);
411 /* init CPU hotplug notifier */
412 cpu_hotplug_cb.rtc_state = s;
413 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
414 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
415
416 if (set_boot_dev(s, boot_device)) {
417 exit(1);
418 }
419
420 /* floppy type */
421 if (floppy) {
422 for (i = 0; i < 2; i++) {
423 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
424 }
425 }
426 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
427 cmos_get_fd_drive_type(fd_type[1]);
428 rtc_set_memory(s, 0x10, val);
429
430 val = 0;
431 nb = 0;
432 if (fd_type[0] < FDRIVE_DRV_NONE) {
433 nb++;
434 }
435 if (fd_type[1] < FDRIVE_DRV_NONE) {
436 nb++;
437 }
438 switch (nb) {
439 case 0:
440 break;
441 case 1:
442 val |= 0x01; /* 1 drive, ready for boot */
443 break;
444 case 2:
445 val |= 0x41; /* 2 drives, ready for boot */
446 break;
447 }
448 val |= 0x02; /* FPU is there */
449 val |= 0x04; /* PS/2 mouse installed */
450 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
451
452 /* hard drives */
453 arg.rtc_state = s;
454 arg.idebus[0] = idebus0;
455 arg.idebus[1] = idebus1;
456 qemu_register_reset(pc_cmos_init_late, &arg);
457 }
458
459 #define TYPE_PORT92 "port92"
460 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
461
462 /* port 92 stuff: could be split off */
463 typedef struct Port92State {
464 ISADevice parent_obj;
465
466 MemoryRegion io;
467 uint8_t outport;
468 qemu_irq *a20_out;
469 } Port92State;
470
471 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
472 unsigned size)
473 {
474 Port92State *s = opaque;
475 int oldval = s->outport;
476
477 DPRINTF("port92: write 0x%02x\n", val);
478 s->outport = val;
479 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
480 if ((val & 1) && !(oldval & 1)) {
481 qemu_system_reset_request();
482 }
483 }
484
485 static uint64_t port92_read(void *opaque, hwaddr addr,
486 unsigned size)
487 {
488 Port92State *s = opaque;
489 uint32_t ret;
490
491 ret = s->outport;
492 DPRINTF("port92: read 0x%02x\n", ret);
493 return ret;
494 }
495
496 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
497 {
498 Port92State *s = PORT92(dev);
499
500 s->a20_out = a20_out;
501 }
502
503 static const VMStateDescription vmstate_port92_isa = {
504 .name = "port92",
505 .version_id = 1,
506 .minimum_version_id = 1,
507 .fields = (VMStateField[]) {
508 VMSTATE_UINT8(outport, Port92State),
509 VMSTATE_END_OF_LIST()
510 }
511 };
512
513 static void port92_reset(DeviceState *d)
514 {
515 Port92State *s = PORT92(d);
516
517 s->outport &= ~1;
518 }
519
520 static const MemoryRegionOps port92_ops = {
521 .read = port92_read,
522 .write = port92_write,
523 .impl = {
524 .min_access_size = 1,
525 .max_access_size = 1,
526 },
527 .endianness = DEVICE_LITTLE_ENDIAN,
528 };
529
530 static void port92_initfn(Object *obj)
531 {
532 Port92State *s = PORT92(obj);
533
534 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
535
536 s->outport = 0;
537 }
538
539 static void port92_realizefn(DeviceState *dev, Error **errp)
540 {
541 ISADevice *isadev = ISA_DEVICE(dev);
542 Port92State *s = PORT92(dev);
543
544 isa_register_ioport(isadev, &s->io, 0x92);
545 }
546
547 static void port92_class_initfn(ObjectClass *klass, void *data)
548 {
549 DeviceClass *dc = DEVICE_CLASS(klass);
550
551 dc->realize = port92_realizefn;
552 dc->reset = port92_reset;
553 dc->vmsd = &vmstate_port92_isa;
554 /*
555 * Reason: unlike ordinary ISA devices, this one needs additional
556 * wiring: its A20 output line needs to be wired up by
557 * port92_init().
558 */
559 dc->cannot_instantiate_with_device_add_yet = true;
560 }
561
562 static const TypeInfo port92_info = {
563 .name = TYPE_PORT92,
564 .parent = TYPE_ISA_DEVICE,
565 .instance_size = sizeof(Port92State),
566 .instance_init = port92_initfn,
567 .class_init = port92_class_initfn,
568 };
569
570 static void port92_register_types(void)
571 {
572 type_register_static(&port92_info);
573 }
574
575 type_init(port92_register_types)
576
577 static void handle_a20_line_change(void *opaque, int irq, int level)
578 {
579 X86CPU *cpu = opaque;
580
581 /* XXX: send to all CPUs ? */
582 /* XXX: add logic to handle multiple A20 line sources */
583 x86_cpu_set_a20(cpu, level);
584 }
585
586 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
587 {
588 int index = le32_to_cpu(e820_reserve.count);
589 struct e820_entry *entry;
590
591 if (type != E820_RAM) {
592 /* old FW_CFG_E820_TABLE entry -- reservations only */
593 if (index >= E820_NR_ENTRIES) {
594 return -EBUSY;
595 }
596 entry = &e820_reserve.entry[index++];
597
598 entry->address = cpu_to_le64(address);
599 entry->length = cpu_to_le64(length);
600 entry->type = cpu_to_le32(type);
601
602 e820_reserve.count = cpu_to_le32(index);
603 }
604
605 /* new "etc/e820" file -- include ram too */
606 e820_table = g_realloc(e820_table,
607 sizeof(struct e820_entry) * (e820_entries+1));
608 e820_table[e820_entries].address = cpu_to_le64(address);
609 e820_table[e820_entries].length = cpu_to_le64(length);
610 e820_table[e820_entries].type = cpu_to_le32(type);
611 e820_entries++;
612
613 return e820_entries;
614 }
615
616 int e820_get_num_entries(void)
617 {
618 return e820_entries;
619 }
620
621 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
622 {
623 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
624 *address = le64_to_cpu(e820_table[idx].address);
625 *length = le64_to_cpu(e820_table[idx].length);
626 return true;
627 }
628 return false;
629 }
630
631 /* Calculates the limit to CPU APIC ID values
632 *
633 * This function returns the limit for the APIC ID value, so that all
634 * CPU APIC IDs are < pc_apic_id_limit().
635 *
636 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
637 */
638 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
639 {
640 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
641 }
642
643 static FWCfgState *bochs_bios_init(void)
644 {
645 FWCfgState *fw_cfg;
646 uint8_t *smbios_tables, *smbios_anchor;
647 size_t smbios_tables_len, smbios_anchor_len;
648 uint64_t *numa_fw_cfg;
649 int i, j;
650 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
651
652 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
653 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
654 *
655 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
656 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
657 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
658 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
659 * may see".
660 *
661 * So, this means we must not use max_cpus, here, but the maximum possible
662 * APIC ID value, plus one.
663 *
664 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
665 * the APIC ID, not the "CPU index"
666 */
667 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
668 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
669 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
670 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
671 acpi_tables, acpi_tables_len);
672 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
673
674 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
675 if (smbios_tables) {
676 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
677 smbios_tables, smbios_tables_len);
678 }
679
680 smbios_get_tables(&smbios_tables, &smbios_tables_len,
681 &smbios_anchor, &smbios_anchor_len);
682 if (smbios_anchor) {
683 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
684 smbios_tables, smbios_tables_len);
685 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
686 smbios_anchor, smbios_anchor_len);
687 }
688
689 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
690 &e820_reserve, sizeof(e820_reserve));
691 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
692 sizeof(struct e820_entry) * e820_entries);
693
694 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
695 /* allocate memory for the NUMA channel: one (64bit) word for the number
696 * of nodes, one word for each VCPU->node and one word for each node to
697 * hold the amount of memory.
698 */
699 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
700 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
701 for (i = 0; i < max_cpus; i++) {
702 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
703 assert(apic_id < apic_id_limit);
704 for (j = 0; j < nb_numa_nodes; j++) {
705 if (test_bit(i, node_cpumask[j])) {
706 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
707 break;
708 }
709 }
710 }
711 for (i = 0; i < nb_numa_nodes; i++) {
712 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
713 }
714 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
715 (1 + apic_id_limit + nb_numa_nodes) *
716 sizeof(*numa_fw_cfg));
717
718 return fw_cfg;
719 }
720
721 static long get_file_size(FILE *f)
722 {
723 long where, size;
724
725 /* XXX: on Unix systems, using fstat() probably makes more sense */
726
727 where = ftell(f);
728 fseek(f, 0, SEEK_END);
729 size = ftell(f);
730 fseek(f, where, SEEK_SET);
731
732 return size;
733 }
734
735 static void load_linux(FWCfgState *fw_cfg,
736 const char *kernel_filename,
737 const char *initrd_filename,
738 const char *kernel_cmdline,
739 hwaddr max_ram_size)
740 {
741 uint16_t protocol;
742 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
743 uint32_t initrd_max;
744 uint8_t header[8192], *setup, *kernel, *initrd_data;
745 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
746 FILE *f;
747 char *vmode;
748
749 /* Align to 16 bytes as a paranoia measure */
750 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
751
752 /* load the kernel header */
753 f = fopen(kernel_filename, "rb");
754 if (!f || !(kernel_size = get_file_size(f)) ||
755 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
756 MIN(ARRAY_SIZE(header), kernel_size)) {
757 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
758 kernel_filename, strerror(errno));
759 exit(1);
760 }
761
762 /* kernel protocol version */
763 #if 0
764 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
765 #endif
766 if (ldl_p(header+0x202) == 0x53726448) {
767 protocol = lduw_p(header+0x206);
768 } else {
769 /* This looks like a multiboot kernel. If it is, let's stop
770 treating it like a Linux kernel. */
771 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
772 kernel_cmdline, kernel_size, header)) {
773 return;
774 }
775 protocol = 0;
776 }
777
778 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
779 /* Low kernel */
780 real_addr = 0x90000;
781 cmdline_addr = 0x9a000 - cmdline_size;
782 prot_addr = 0x10000;
783 } else if (protocol < 0x202) {
784 /* High but ancient kernel */
785 real_addr = 0x90000;
786 cmdline_addr = 0x9a000 - cmdline_size;
787 prot_addr = 0x100000;
788 } else {
789 /* High and recent kernel */
790 real_addr = 0x10000;
791 cmdline_addr = 0x20000;
792 prot_addr = 0x100000;
793 }
794
795 #if 0
796 fprintf(stderr,
797 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
798 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
799 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
800 real_addr,
801 cmdline_addr,
802 prot_addr);
803 #endif
804
805 /* highest address for loading the initrd */
806 if (protocol >= 0x203) {
807 initrd_max = ldl_p(header+0x22c);
808 } else {
809 initrd_max = 0x37ffffff;
810 }
811
812 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
813 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
814
815 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
816 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
817 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
818
819 if (protocol >= 0x202) {
820 stl_p(header+0x228, cmdline_addr);
821 } else {
822 stw_p(header+0x20, 0xA33F);
823 stw_p(header+0x22, cmdline_addr-real_addr);
824 }
825
826 /* handle vga= parameter */
827 vmode = strstr(kernel_cmdline, "vga=");
828 if (vmode) {
829 unsigned int video_mode;
830 /* skip "vga=" */
831 vmode += 4;
832 if (!strncmp(vmode, "normal", 6)) {
833 video_mode = 0xffff;
834 } else if (!strncmp(vmode, "ext", 3)) {
835 video_mode = 0xfffe;
836 } else if (!strncmp(vmode, "ask", 3)) {
837 video_mode = 0xfffd;
838 } else {
839 video_mode = strtol(vmode, NULL, 0);
840 }
841 stw_p(header+0x1fa, video_mode);
842 }
843
844 /* loader type */
845 /* High nybble = B reserved for QEMU; low nybble is revision number.
846 If this code is substantially changed, you may want to consider
847 incrementing the revision. */
848 if (protocol >= 0x200) {
849 header[0x210] = 0xB0;
850 }
851 /* heap */
852 if (protocol >= 0x201) {
853 header[0x211] |= 0x80; /* CAN_USE_HEAP */
854 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
855 }
856
857 /* load initrd */
858 if (initrd_filename) {
859 if (protocol < 0x200) {
860 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
861 exit(1);
862 }
863
864 initrd_size = get_image_size(initrd_filename);
865 if (initrd_size < 0) {
866 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
867 initrd_filename, strerror(errno));
868 exit(1);
869 }
870
871 initrd_addr = (initrd_max-initrd_size) & ~4095;
872
873 initrd_data = g_malloc(initrd_size);
874 load_image(initrd_filename, initrd_data);
875
876 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
877 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
878 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
879
880 stl_p(header+0x218, initrd_addr);
881 stl_p(header+0x21c, initrd_size);
882 }
883
884 /* load kernel and setup */
885 setup_size = header[0x1f1];
886 if (setup_size == 0) {
887 setup_size = 4;
888 }
889 setup_size = (setup_size+1)*512;
890 kernel_size -= setup_size;
891
892 setup = g_malloc(setup_size);
893 kernel = g_malloc(kernel_size);
894 fseek(f, 0, SEEK_SET);
895 if (fread(setup, 1, setup_size, f) != setup_size) {
896 fprintf(stderr, "fread() failed\n");
897 exit(1);
898 }
899 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
900 fprintf(stderr, "fread() failed\n");
901 exit(1);
902 }
903 fclose(f);
904 memcpy(setup, header, MIN(sizeof(header), setup_size));
905
906 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
907 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
908 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
909
910 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
911 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
912 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
913
914 option_rom[nb_option_roms].name = "linuxboot.bin";
915 option_rom[nb_option_roms].bootindex = 0;
916 nb_option_roms++;
917 }
918
919 #define NE2000_NB_MAX 6
920
921 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
922 0x280, 0x380 };
923 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
924
925 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
926 {
927 static int nb_ne2k = 0;
928
929 if (nb_ne2k == NE2000_NB_MAX)
930 return;
931 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
932 ne2000_irq[nb_ne2k], nd);
933 nb_ne2k++;
934 }
935
936 DeviceState *cpu_get_current_apic(void)
937 {
938 if (current_cpu) {
939 X86CPU *cpu = X86_CPU(current_cpu);
940 return cpu->apic_state;
941 } else {
942 return NULL;
943 }
944 }
945
946 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
947 {
948 X86CPU *cpu = opaque;
949
950 if (level) {
951 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
952 }
953 }
954
955 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
956 DeviceState *icc_bridge, Error **errp)
957 {
958 X86CPU *cpu;
959 Error *local_err = NULL;
960
961 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
962 if (local_err != NULL) {
963 error_propagate(errp, local_err);
964 return NULL;
965 }
966
967 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
968 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
969
970 if (local_err) {
971 error_propagate(errp, local_err);
972 object_unref(OBJECT(cpu));
973 cpu = NULL;
974 }
975 return cpu;
976 }
977
978 static const char *current_cpu_model;
979
980 void pc_hot_add_cpu(const int64_t id, Error **errp)
981 {
982 DeviceState *icc_bridge;
983 int64_t apic_id = x86_cpu_apic_id_from_index(id);
984
985 if (id < 0) {
986 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
987 return;
988 }
989
990 if (cpu_exists(apic_id)) {
991 error_setg(errp, "Unable to add CPU: %" PRIi64
992 ", it already exists", id);
993 return;
994 }
995
996 if (id >= max_cpus) {
997 error_setg(errp, "Unable to add CPU: %" PRIi64
998 ", max allowed: %d", id, max_cpus - 1);
999 return;
1000 }
1001
1002 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1003 error_setg(errp, "Unable to add CPU: %" PRIi64
1004 ", resulting APIC ID (%" PRIi64 ") is too large",
1005 id, apic_id);
1006 return;
1007 }
1008
1009 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
1010 TYPE_ICC_BRIDGE, NULL));
1011 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
1012 }
1013
1014 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1015 {
1016 int i;
1017 X86CPU *cpu = NULL;
1018 Error *error = NULL;
1019 unsigned long apic_id_limit;
1020
1021 /* init CPUs */
1022 if (cpu_model == NULL) {
1023 #ifdef TARGET_X86_64
1024 cpu_model = "qemu64";
1025 #else
1026 cpu_model = "qemu32";
1027 #endif
1028 }
1029 current_cpu_model = cpu_model;
1030
1031 apic_id_limit = pc_apic_id_limit(max_cpus);
1032 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1033 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1034 apic_id_limit - 1);
1035 exit(1);
1036 }
1037
1038 for (i = 0; i < smp_cpus; i++) {
1039 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1040 icc_bridge, &error);
1041 if (error) {
1042 error_report("%s", error_get_pretty(error));
1043 error_free(error);
1044 exit(1);
1045 }
1046 }
1047
1048 /* map APIC MMIO area if CPU has APIC */
1049 if (cpu && cpu->apic_state) {
1050 /* XXX: what if the base changes? */
1051 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1052 APIC_DEFAULT_ADDRESS, 0x1000);
1053 }
1054
1055 /* tell smbios about cpuid version and features */
1056 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1057 }
1058
1059 /* pci-info ROM file. Little endian format */
1060 typedef struct PcRomPciInfo {
1061 uint64_t w32_min;
1062 uint64_t w32_max;
1063 uint64_t w64_min;
1064 uint64_t w64_max;
1065 } PcRomPciInfo;
1066
1067 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1068 {
1069 PcRomPciInfo *info;
1070 Object *pci_info;
1071 bool ambiguous = false;
1072
1073 if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1074 return;
1075 }
1076 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1077 g_assert(!ambiguous);
1078 if (!pci_info) {
1079 return;
1080 }
1081
1082 info = g_malloc(sizeof *info);
1083 info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
1084 PCI_HOST_PROP_PCI_HOLE_START, NULL));
1085 info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
1086 PCI_HOST_PROP_PCI_HOLE_END, NULL));
1087 info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
1088 PCI_HOST_PROP_PCI_HOLE64_START, NULL));
1089 info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
1090 PCI_HOST_PROP_PCI_HOLE64_END, NULL));
1091 /* Pass PCI hole info to guest via a side channel.
1092 * Required so guest PCI enumeration does the right thing. */
1093 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1094 }
1095
1096 typedef struct PcGuestInfoState {
1097 PcGuestInfo info;
1098 Notifier machine_done;
1099 } PcGuestInfoState;
1100
1101 static
1102 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1103 {
1104 PcGuestInfoState *guest_info_state = container_of(notifier,
1105 PcGuestInfoState,
1106 machine_done);
1107 pc_fw_cfg_guest_info(&guest_info_state->info);
1108 acpi_setup(&guest_info_state->info);
1109 }
1110
1111 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1112 ram_addr_t above_4g_mem_size)
1113 {
1114 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1115 PcGuestInfo *guest_info = &guest_info_state->info;
1116 int i, j;
1117
1118 guest_info->ram_size_below_4g = below_4g_mem_size;
1119 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1120 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1121 guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1122 guest_info->numa_nodes = nb_numa_nodes;
1123 guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
1124 sizeof *guest_info->node_mem);
1125 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1126 sizeof *guest_info->node_cpu);
1127
1128 for (i = 0; i < max_cpus; i++) {
1129 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1130 assert(apic_id < guest_info->apic_id_limit);
1131 for (j = 0; j < nb_numa_nodes; j++) {
1132 if (test_bit(i, node_cpumask[j])) {
1133 guest_info->node_cpu[apic_id] = j;
1134 break;
1135 }
1136 }
1137 }
1138
1139 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1140 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1141 return guest_info;
1142 }
1143
1144 /* setup pci memory address space mapping into system address space */
1145 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1146 MemoryRegion *pci_address_space)
1147 {
1148 /* Set to lower priority than RAM */
1149 memory_region_add_subregion_overlap(system_memory, 0x0,
1150 pci_address_space, -1);
1151 }
1152
1153 void pc_acpi_init(const char *default_dsdt)
1154 {
1155 char *filename;
1156
1157 if (acpi_tables != NULL) {
1158 /* manually set via -acpitable, leave it alone */
1159 return;
1160 }
1161
1162 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1163 if (filename == NULL) {
1164 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1165 } else {
1166 char *arg;
1167 QemuOpts *opts;
1168 Error *err = NULL;
1169
1170 arg = g_strdup_printf("file=%s", filename);
1171
1172 /* creates a deep copy of "arg" */
1173 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1174 g_assert(opts != NULL);
1175
1176 acpi_table_add_builtin(opts, &err);
1177 if (err) {
1178 error_report("WARNING: failed to load %s: %s", filename,
1179 error_get_pretty(err));
1180 error_free(err);
1181 }
1182 g_free(arg);
1183 g_free(filename);
1184 }
1185 }
1186
1187 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1188 const char *kernel_filename,
1189 const char *kernel_cmdline,
1190 const char *initrd_filename,
1191 ram_addr_t below_4g_mem_size,
1192 ram_addr_t above_4g_mem_size,
1193 MemoryRegion *rom_memory,
1194 MemoryRegion **ram_memory,
1195 PcGuestInfo *guest_info)
1196 {
1197 int linux_boot, i;
1198 MemoryRegion *ram, *option_rom_mr;
1199 MemoryRegion *ram_below_4g, *ram_above_4g;
1200 FWCfgState *fw_cfg;
1201 ram_addr_t ram_size = below_4g_mem_size + above_4g_mem_size;
1202 MachineState *machine = MACHINE(qdev_get_machine());
1203 PCMachineState *pcms = PC_MACHINE(machine);
1204
1205 linux_boot = (kernel_filename != NULL);
1206
1207 /* Allocate RAM. We allocate it as a single memory region and use
1208 * aliases to address portions of it, mostly for backwards compatibility
1209 * with older qemus that used qemu_ram_alloc().
1210 */
1211 ram = g_malloc(sizeof(*ram));
1212 memory_region_init_ram(ram, NULL, "pc.ram", ram_size);
1213 vmstate_register_ram_global(ram);
1214 *ram_memory = ram;
1215 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1216 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1217 0, below_4g_mem_size);
1218 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1219 e820_add_entry(0, below_4g_mem_size, E820_RAM);
1220 if (above_4g_mem_size > 0) {
1221 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1222 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1223 below_4g_mem_size, above_4g_mem_size);
1224 memory_region_add_subregion(system_memory, 0x100000000ULL,
1225 ram_above_4g);
1226 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1227 }
1228
1229 if (!guest_info->has_reserved_memory &&
1230 (machine->ram_slots ||
1231 (machine->maxram_size > ram_size))) {
1232 MachineClass *mc = MACHINE_GET_CLASS(machine);
1233
1234 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1235 mc->name);
1236 exit(EXIT_FAILURE);
1237 }
1238
1239 /* initialize hotplug memory address space */
1240 if (guest_info->has_reserved_memory &&
1241 (ram_size < machine->maxram_size)) {
1242 ram_addr_t hotplug_mem_size =
1243 machine->maxram_size - ram_size;
1244
1245 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1246 error_report("unsupported amount of memory slots: %"PRIu64,
1247 machine->ram_slots);
1248 exit(EXIT_FAILURE);
1249 }
1250
1251 pcms->hotplug_memory_base =
1252 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
1253
1254 if ((pcms->hotplug_memory_base + hotplug_mem_size) <
1255 hotplug_mem_size) {
1256 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1257 machine->maxram_size);
1258 exit(EXIT_FAILURE);
1259 }
1260
1261 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms),
1262 "hotplug-memory", hotplug_mem_size);
1263 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base,
1264 &pcms->hotplug_memory);
1265 }
1266
1267 /* Initialize PC system firmware */
1268 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1269
1270 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1271 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1272 vmstate_register_ram_global(option_rom_mr);
1273 memory_region_add_subregion_overlap(rom_memory,
1274 PC_ROM_MIN_VGA,
1275 option_rom_mr,
1276 1);
1277
1278 fw_cfg = bochs_bios_init();
1279 rom_set_fw(fw_cfg);
1280
1281 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) {
1282 uint64_t *val = g_malloc(sizeof(*val));
1283 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30));
1284 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1285 }
1286
1287 if (linux_boot) {
1288 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1289 }
1290
1291 for (i = 0; i < nb_option_roms; i++) {
1292 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1293 }
1294 guest_info->fw_cfg = fw_cfg;
1295 return fw_cfg;
1296 }
1297
1298 qemu_irq *pc_allocate_cpu_irq(void)
1299 {
1300 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1301 }
1302
1303 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1304 {
1305 DeviceState *dev = NULL;
1306
1307 if (pci_bus) {
1308 PCIDevice *pcidev = pci_vga_init(pci_bus);
1309 dev = pcidev ? &pcidev->qdev : NULL;
1310 } else if (isa_bus) {
1311 ISADevice *isadev = isa_vga_init(isa_bus);
1312 dev = isadev ? DEVICE(isadev) : NULL;
1313 }
1314 return dev;
1315 }
1316
1317 static void cpu_request_exit(void *opaque, int irq, int level)
1318 {
1319 CPUState *cpu = current_cpu;
1320
1321 if (cpu && level) {
1322 cpu_exit(cpu);
1323 }
1324 }
1325
1326 static const MemoryRegionOps ioport80_io_ops = {
1327 .write = ioport80_write,
1328 .read = ioport80_read,
1329 .endianness = DEVICE_NATIVE_ENDIAN,
1330 .impl = {
1331 .min_access_size = 1,
1332 .max_access_size = 1,
1333 },
1334 };
1335
1336 static const MemoryRegionOps ioportF0_io_ops = {
1337 .write = ioportF0_write,
1338 .read = ioportF0_read,
1339 .endianness = DEVICE_NATIVE_ENDIAN,
1340 .impl = {
1341 .min_access_size = 1,
1342 .max_access_size = 1,
1343 },
1344 };
1345
1346 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1347 ISADevice **rtc_state,
1348 ISADevice **floppy,
1349 bool no_vmport,
1350 uint32 hpet_irqs)
1351 {
1352 int i;
1353 DriveInfo *fd[MAX_FD];
1354 DeviceState *hpet = NULL;
1355 int pit_isa_irq = 0;
1356 qemu_irq pit_alt_irq = NULL;
1357 qemu_irq rtc_irq = NULL;
1358 qemu_irq *a20_line;
1359 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1360 qemu_irq *cpu_exit_irq;
1361 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1362 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1363
1364 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1365 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1366
1367 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1368 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1369
1370 /*
1371 * Check if an HPET shall be created.
1372 *
1373 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1374 * when the HPET wants to take over. Thus we have to disable the latter.
1375 */
1376 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1377 /* In order to set property, here not using sysbus_try_create_simple */
1378 hpet = qdev_try_create(NULL, TYPE_HPET);
1379 if (hpet) {
1380 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1381 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1382 * IRQ8 and IRQ2.
1383 */
1384 uint8_t compat = object_property_get_int(OBJECT(hpet),
1385 HPET_INTCAP, NULL);
1386 if (!compat) {
1387 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1388 }
1389 qdev_init_nofail(hpet);
1390 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1391
1392 for (i = 0; i < GSI_NUM_PINS; i++) {
1393 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1394 }
1395 pit_isa_irq = -1;
1396 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1397 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1398 }
1399 }
1400 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1401
1402 qemu_register_boot_set(pc_boot_set, *rtc_state);
1403
1404 if (!xen_enabled()) {
1405 if (kvm_irqchip_in_kernel()) {
1406 pit = kvm_pit_init(isa_bus, 0x40);
1407 } else {
1408 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1409 }
1410 if (hpet) {
1411 /* connect PIT to output control line of the HPET */
1412 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1413 }
1414 pcspk_init(isa_bus, pit);
1415 }
1416
1417 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1418 if (serial_hds[i]) {
1419 serial_isa_init(isa_bus, i, serial_hds[i]);
1420 }
1421 }
1422
1423 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1424 if (parallel_hds[i]) {
1425 parallel_init(isa_bus, i, parallel_hds[i]);
1426 }
1427 }
1428
1429 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1430 i8042 = isa_create_simple(isa_bus, "i8042");
1431 i8042_setup_a20_line(i8042, &a20_line[0]);
1432 if (!no_vmport) {
1433 vmport_init(isa_bus);
1434 vmmouse = isa_try_create(isa_bus, "vmmouse");
1435 } else {
1436 vmmouse = NULL;
1437 }
1438 if (vmmouse) {
1439 DeviceState *dev = DEVICE(vmmouse);
1440 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1441 qdev_init_nofail(dev);
1442 }
1443 port92 = isa_create_simple(isa_bus, "port92");
1444 port92_init(port92, &a20_line[1]);
1445
1446 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1447 DMA_init(0, cpu_exit_irq);
1448
1449 for(i = 0; i < MAX_FD; i++) {
1450 fd[i] = drive_get(IF_FLOPPY, 0, i);
1451 }
1452 *floppy = fdctrl_init_isa(isa_bus, fd);
1453 }
1454
1455 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1456 {
1457 int i;
1458
1459 for (i = 0; i < nb_nics; i++) {
1460 NICInfo *nd = &nd_table[i];
1461
1462 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1463 pc_init_ne2k_isa(isa_bus, nd);
1464 } else {
1465 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1466 }
1467 }
1468 }
1469
1470 void pc_pci_device_init(PCIBus *pci_bus)
1471 {
1472 int max_bus;
1473 int bus;
1474
1475 max_bus = drive_get_max_bus(IF_SCSI);
1476 for (bus = 0; bus <= max_bus; bus++) {
1477 pci_create_simple(pci_bus, -1, "lsi53c895a");
1478 }
1479 }
1480
1481 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1482 {
1483 DeviceState *dev;
1484 SysBusDevice *d;
1485 unsigned int i;
1486
1487 if (kvm_irqchip_in_kernel()) {
1488 dev = qdev_create(NULL, "kvm-ioapic");
1489 } else {
1490 dev = qdev_create(NULL, "ioapic");
1491 }
1492 if (parent_name) {
1493 object_property_add_child(object_resolve_path(parent_name, NULL),
1494 "ioapic", OBJECT(dev), NULL);
1495 }
1496 qdev_init_nofail(dev);
1497 d = SYS_BUS_DEVICE(dev);
1498 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1499
1500 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1501 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1502 }
1503 }
1504
1505 static void pc_generic_machine_class_init(ObjectClass *oc, void *data)
1506 {
1507 MachineClass *mc = MACHINE_CLASS(oc);
1508 QEMUMachine *qm = data;
1509
1510 mc->name = qm->name;
1511 mc->alias = qm->alias;
1512 mc->desc = qm->desc;
1513 mc->init = qm->init;
1514 mc->reset = qm->reset;
1515 mc->hot_add_cpu = qm->hot_add_cpu;
1516 mc->kvm_type = qm->kvm_type;
1517 mc->block_default_type = qm->block_default_type;
1518 mc->max_cpus = qm->max_cpus;
1519 mc->no_serial = qm->no_serial;
1520 mc->no_parallel = qm->no_parallel;
1521 mc->use_virtcon = qm->use_virtcon;
1522 mc->use_sclp = qm->use_sclp;
1523 mc->no_floppy = qm->no_floppy;
1524 mc->no_cdrom = qm->no_cdrom;
1525 mc->no_sdcard = qm->no_sdcard;
1526 mc->is_default = qm->is_default;
1527 mc->default_machine_opts = qm->default_machine_opts;
1528 mc->default_boot_order = qm->default_boot_order;
1529 mc->compat_props = qm->compat_props;
1530 mc->hw_version = qm->hw_version;
1531 }
1532
1533 void qemu_register_pc_machine(QEMUMachine *m)
1534 {
1535 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL);
1536 TypeInfo ti = {
1537 .name = name,
1538 .parent = TYPE_PC_MACHINE,
1539 .class_init = pc_generic_machine_class_init,
1540 .class_data = (void *)m,
1541 };
1542
1543 type_register(&ti);
1544 g_free(name);
1545 }
1546
1547 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1548 DeviceState *dev, Error **errp)
1549 {
1550 Error *local_err = NULL;
1551 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1552 PCDIMMDevice *dimm = PC_DIMM(dev);
1553 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1554 MemoryRegion *mr = ddc->get_memory_region(dimm);
1555 uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
1556 &local_err);
1557 if (local_err) {
1558 goto out;
1559 }
1560
1561 memory_region_add_subregion(&pcms->hotplug_memory,
1562 addr - pcms->hotplug_memory_base, mr);
1563 vmstate_register_ram(mr, dev);
1564 out:
1565 error_propagate(errp, local_err);
1566 }
1567
1568 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1569 DeviceState *dev, Error **errp)
1570 {
1571 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1572 pc_dimm_plug(hotplug_dev, dev, errp);
1573 }
1574 }
1575
1576 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
1577 DeviceState *dev)
1578 {
1579 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1580
1581 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1582 return HOTPLUG_HANDLER(machine);
1583 }
1584
1585 return pcmc->get_hotplug_handler ?
1586 pcmc->get_hotplug_handler(machine, dev) : NULL;
1587 }
1588
1589 static void pc_machine_class_init(ObjectClass *oc, void *data)
1590 {
1591 MachineClass *mc = MACHINE_CLASS(oc);
1592 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1593 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1594
1595 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
1596 mc->get_hotplug_handler = pc_get_hotpug_handler;
1597 hc->plug = pc_machine_device_plug_cb;
1598 }
1599
1600 static const TypeInfo pc_machine_info = {
1601 .name = TYPE_PC_MACHINE,
1602 .parent = TYPE_MACHINE,
1603 .abstract = true,
1604 .instance_size = sizeof(PCMachineState),
1605 .class_size = sizeof(PCMachineClass),
1606 .class_init = pc_machine_class_init,
1607 .interfaces = (InterfaceInfo[]) {
1608 { TYPE_HOTPLUG_HANDLER },
1609 { }
1610 },
1611 };
1612
1613 static void pc_machine_register_types(void)
1614 {
1615 type_register_static(&pc_machine_info);
1616 }
1617
1618 type_init(pc_machine_register_types)