cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / hw / i386 / pc_q35.c
1 /*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30 #include "hw/hw.h"
31 #include "sysemu/arch_init.h"
32 #include "hw/smbus.h"
33 #include "hw/boards.h"
34 #include "hw/mc146818rtc.h"
35 #include "hw/xen.h"
36 #include "sysemu/kvm.h"
37 #include "hw/kvm/clock.h"
38 #include "hw/q35.h"
39 #include "exec/address-spaces.h"
40 #include "hw/ich9.h"
41 #include "hw/ide/pci.h"
42 #include "hw/ide/ahci.h"
43 #include "hw/usb.h"
44
45 /* ICH9 AHCI has 6 ports */
46 #define MAX_SATA_PORTS 6
47
48 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
49 * BIOS will read it and start S3 resume at POST Entry */
50 static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
51 {
52 ISADevice *s = opaque;
53
54 if (level) {
55 rtc_set_memory(s, 0xF, 0xFE);
56 }
57 }
58
59 /* PC hardware initialisation */
60 static void pc_q35_init(QEMUMachineInitArgs *args)
61 {
62 ram_addr_t ram_size = args->ram_size;
63 const char *cpu_model = args->cpu_model;
64 const char *kernel_filename = args->kernel_filename;
65 const char *kernel_cmdline = args->kernel_cmdline;
66 const char *initrd_filename = args->initrd_filename;
67 const char *boot_device = args->boot_device;
68 ram_addr_t below_4g_mem_size, above_4g_mem_size;
69 Q35PCIHost *q35_host;
70 PCIBus *host_bus;
71 PCIDevice *lpc;
72 BusState *idebus[MAX_SATA_PORTS];
73 ISADevice *rtc_state;
74 ISADevice *floppy;
75 MemoryRegion *pci_memory;
76 MemoryRegion *rom_memory;
77 MemoryRegion *ram_memory;
78 GSIState *gsi_state;
79 ISABus *isa_bus;
80 int pci_enabled = 1;
81 qemu_irq *cpu_irq;
82 qemu_irq *gsi;
83 qemu_irq *i8259;
84 int i;
85 ICH9LPCState *ich9_lpc;
86 PCIDevice *ahci;
87 qemu_irq *cmos_s3;
88
89 pc_cpus_init(cpu_model);
90 pc_acpi_init("q35-acpi-dsdt.aml");
91
92 kvmclock_create();
93
94 if (ram_size >= 0xb0000000) {
95 above_4g_mem_size = ram_size - 0xb0000000;
96 below_4g_mem_size = 0xb0000000;
97 } else {
98 above_4g_mem_size = 0;
99 below_4g_mem_size = ram_size;
100 }
101
102 /* pci enabled */
103 if (pci_enabled) {
104 pci_memory = g_new(MemoryRegion, 1);
105 memory_region_init(pci_memory, "pci", INT64_MAX);
106 rom_memory = pci_memory;
107 } else {
108 pci_memory = NULL;
109 rom_memory = get_system_memory();
110 }
111
112 /* allocate ram and load rom/bios */
113 if (!xen_enabled()) {
114 pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
115 initrd_filename, below_4g_mem_size, above_4g_mem_size,
116 rom_memory, &ram_memory);
117 }
118
119 /* irq lines */
120 gsi_state = g_malloc0(sizeof(*gsi_state));
121 if (kvm_irqchip_in_kernel()) {
122 kvm_pc_setup_irq_routing(pci_enabled);
123 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
124 GSI_NUM_PINS);
125 } else {
126 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
127 }
128
129 /* create pci host bus */
130 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
131
132 q35_host->mch.ram_memory = ram_memory;
133 q35_host->mch.pci_address_space = pci_memory;
134 q35_host->mch.system_memory = get_system_memory();
135 q35_host->mch.address_space_io = get_system_io();;
136 q35_host->mch.below_4g_mem_size = below_4g_mem_size;
137 q35_host->mch.above_4g_mem_size = above_4g_mem_size;
138 /* pci */
139 qdev_init_nofail(DEVICE(q35_host));
140 host_bus = q35_host->host.pci.bus;
141 /* create ISA bus */
142 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
143 ICH9_LPC_FUNC), true,
144 TYPE_ICH9_LPC_DEVICE);
145 ich9_lpc = ICH9_LPC_DEVICE(lpc);
146 ich9_lpc->pic = gsi;
147 ich9_lpc->ioapic = gsi_state->ioapic_irq;
148 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
149 ICH9_LPC_NB_PIRQS);
150 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
151 isa_bus = ich9_lpc->isa_bus;
152
153 /*end early*/
154 isa_bus_irqs(isa_bus, gsi);
155
156 if (kvm_irqchip_in_kernel()) {
157 i8259 = kvm_i8259_init(isa_bus);
158 } else if (xen_enabled()) {
159 i8259 = xen_interrupt_controller_init();
160 } else {
161 cpu_irq = pc_allocate_cpu_irq();
162 i8259 = i8259_init(isa_bus, cpu_irq[0]);
163 }
164
165 for (i = 0; i < ISA_NUM_IRQS; i++) {
166 gsi_state->i8259_irq[i] = i8259[i];
167 }
168 if (pci_enabled) {
169 ioapic_init_gsi(gsi_state, NULL);
170 }
171
172 pc_register_ferr_irq(gsi[13]);
173
174 /* init basic PC hardware */
175 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
176
177 /* connect pm stuff to lpc */
178 cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
179 ich9_lpc_pm_init(lpc, *cmos_s3);
180
181 /* ahci and SATA device, for q35 1 ahci controller is built-in */
182 ahci = pci_create_simple_multifunction(host_bus,
183 PCI_DEVFN(ICH9_SATA1_DEV,
184 ICH9_SATA1_FUNC),
185 true, "ich9-ahci");
186 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
187 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
188
189 if (usb_enabled(false)) {
190 /* Should we create 6 UHCI according to ich9 spec? */
191 ehci_create_ich9_with_companions(host_bus, 0x1d);
192 }
193
194 /* TODO: Populate SPD eeprom data. */
195 smbus_eeprom_init(ich9_smb_init(host_bus,
196 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
197 0xb100),
198 8, NULL, 0);
199
200 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
201 floppy, idebus[0], idebus[1], rtc_state);
202
203 /* the rest devices to which pci devfn is automatically assigned */
204 pc_vga_init(isa_bus, host_bus);
205 audio_init(isa_bus, host_bus);
206 pc_nic_init(isa_bus, host_bus);
207 if (pci_enabled) {
208 pc_pci_device_init(host_bus);
209 }
210 }
211
212 static QEMUMachine pc_q35_machine_v1_5 = {
213 .name = "pc-q35-1.5",
214 .alias = "q35",
215 .desc = "Standard PC (Q35 + ICH9, 2009)",
216 .init = pc_q35_init,
217 .max_cpus = 255,
218 DEFAULT_MACHINE_OPTIONS,
219 };
220
221 static QEMUMachine pc_q35_machine_v1_4 = {
222 .name = "pc-q35-1.4",
223 .desc = "Standard PC (Q35 + ICH9, 2009)",
224 .init = pc_q35_init,
225 .max_cpus = 255,
226 .compat_props = (GlobalProperty[]) {
227 PC_COMPAT_1_4,
228 { /* end of list */ }
229 },
230 DEFAULT_MACHINE_OPTIONS,
231 };
232
233 static void pc_q35_machine_init(void)
234 {
235 qemu_register_machine(&pc_q35_machine_v1_5);
236 qemu_register_machine(&pc_q35_machine_v1_4);
237 }
238
239 machine_init(pc_q35_machine_init);