pc: pass MachineState to pc_memory_init
[qemu.git] / hw / i386 / pc_q35.c
1 /*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30 #include "hw/hw.h"
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
45 #include "hw/usb.h"
46 #include "hw/cpu/icc_bus.h"
47
48 /* ICH9 AHCI has 6 ports */
49 #define MAX_SATA_PORTS 6
50
51 static bool has_pci_info;
52 static bool has_acpi_build = true;
53 static bool smbios_defaults = true;
54 static bool smbios_legacy_mode;
55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
56 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
57 * pages in the host.
58 */
59 static bool gigabyte_align = true;
60 static bool has_reserved_memory = true;
61
62 /* PC hardware initialisation */
63 static void pc_q35_init(MachineState *machine)
64 {
65 PCMachineState *pc_machine = PC_MACHINE(machine);
66 ram_addr_t below_4g_mem_size, above_4g_mem_size;
67 Q35PCIHost *q35_host;
68 PCIHostState *phb;
69 PCIBus *host_bus;
70 PCIDevice *lpc;
71 BusState *idebus[MAX_SATA_PORTS];
72 ISADevice *rtc_state;
73 ISADevice *floppy;
74 MemoryRegion *pci_memory;
75 MemoryRegion *rom_memory;
76 MemoryRegion *ram_memory;
77 GSIState *gsi_state;
78 ISABus *isa_bus;
79 int pci_enabled = 1;
80 qemu_irq *cpu_irq;
81 qemu_irq *gsi;
82 qemu_irq *i8259;
83 int i;
84 ICH9LPCState *ich9_lpc;
85 PCIDevice *ahci;
86 DeviceState *icc_bridge;
87 PcGuestInfo *guest_info;
88
89 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
90 fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
91 exit(1);
92 }
93
94 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
95 object_property_add_child(qdev_get_machine(), "icc-bridge",
96 OBJECT(icc_bridge), NULL);
97
98 pc_cpus_init(machine->cpu_model, icc_bridge);
99 pc_acpi_init("q35-acpi-dsdt.aml");
100
101 kvmclock_create();
102
103 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
104 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
105 * also known as MMCFG).
106 * If it doesn't, we need to split it in chunks below and above 4G.
107 * In any case, try to make sure that guest addresses aligned at
108 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
109 * For old machine types, use whatever split we used historically to avoid
110 * breaking migration.
111 */
112 if (machine->ram_size >= 0xb0000000) {
113 ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
114 above_4g_mem_size = machine->ram_size - lowmem;
115 below_4g_mem_size = lowmem;
116 } else {
117 above_4g_mem_size = 0;
118 below_4g_mem_size = machine->ram_size;
119 }
120
121 /* pci enabled */
122 if (pci_enabled) {
123 pci_memory = g_new(MemoryRegion, 1);
124 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
125 rom_memory = pci_memory;
126 } else {
127 pci_memory = NULL;
128 rom_memory = get_system_memory();
129 }
130
131 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
132 guest_info->has_pci_info = has_pci_info;
133 guest_info->isapc_ram_fw = false;
134 guest_info->has_acpi_build = has_acpi_build;
135 guest_info->has_reserved_memory = has_reserved_memory;
136
137 if (smbios_defaults) {
138 MachineClass *mc = MACHINE_GET_CLASS(machine);
139 /* These values are guest ABI, do not change */
140 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
141 mc->name, smbios_legacy_mode);
142 }
143
144 /* allocate ram and load rom/bios */
145 if (!xen_enabled()) {
146 pc_memory_init(machine, get_system_memory(),
147 below_4g_mem_size, above_4g_mem_size,
148 rom_memory, &ram_memory, guest_info);
149 }
150
151 /* irq lines */
152 gsi_state = g_malloc0(sizeof(*gsi_state));
153 if (kvm_irqchip_in_kernel()) {
154 kvm_pc_setup_irq_routing(pci_enabled);
155 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
156 GSI_NUM_PINS);
157 } else {
158 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
159 }
160
161 /* create pci host bus */
162 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
163
164 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
165 q35_host->mch.ram_memory = ram_memory;
166 q35_host->mch.pci_address_space = pci_memory;
167 q35_host->mch.system_memory = get_system_memory();
168 q35_host->mch.address_space_io = get_system_io();
169 q35_host->mch.below_4g_mem_size = below_4g_mem_size;
170 q35_host->mch.above_4g_mem_size = above_4g_mem_size;
171 q35_host->mch.guest_info = guest_info;
172 /* pci */
173 qdev_init_nofail(DEVICE(q35_host));
174 phb = PCI_HOST_BRIDGE(q35_host);
175 host_bus = phb->bus;
176 /* create ISA bus */
177 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
178 ICH9_LPC_FUNC), true,
179 TYPE_ICH9_LPC_DEVICE);
180
181 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
182 TYPE_HOTPLUG_HANDLER,
183 (Object **)&pc_machine->acpi_dev,
184 object_property_allow_set_link,
185 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
186 object_property_set_link(OBJECT(machine), OBJECT(lpc),
187 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
188
189 ich9_lpc = ICH9_LPC_DEVICE(lpc);
190 ich9_lpc->pic = gsi;
191 ich9_lpc->ioapic = gsi_state->ioapic_irq;
192 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
193 ICH9_LPC_NB_PIRQS);
194 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
195 isa_bus = ich9_lpc->isa_bus;
196
197 /*end early*/
198 isa_bus_irqs(isa_bus, gsi);
199
200 if (kvm_irqchip_in_kernel()) {
201 i8259 = kvm_i8259_init(isa_bus);
202 } else if (xen_enabled()) {
203 i8259 = xen_interrupt_controller_init();
204 } else {
205 cpu_irq = pc_allocate_cpu_irq();
206 i8259 = i8259_init(isa_bus, cpu_irq[0]);
207 }
208
209 for (i = 0; i < ISA_NUM_IRQS; i++) {
210 gsi_state->i8259_irq[i] = i8259[i];
211 }
212 if (pci_enabled) {
213 ioapic_init_gsi(gsi_state, NULL);
214 }
215 qdev_init_nofail(icc_bridge);
216
217 pc_register_ferr_irq(gsi[13]);
218
219 /* init basic PC hardware */
220 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);
221
222 /* connect pm stuff to lpc */
223 ich9_lpc_pm_init(lpc);
224
225 /* ahci and SATA device, for q35 1 ahci controller is built-in */
226 ahci = pci_create_simple_multifunction(host_bus,
227 PCI_DEVFN(ICH9_SATA1_DEV,
228 ICH9_SATA1_FUNC),
229 true, "ich9-ahci");
230 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
231 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
232
233 if (usb_enabled(false)) {
234 /* Should we create 6 UHCI according to ich9 spec? */
235 ehci_create_ich9_with_companions(host_bus, 0x1d);
236 }
237
238 /* TODO: Populate SPD eeprom data. */
239 smbus_eeprom_init(ich9_smb_init(host_bus,
240 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
241 0xb100),
242 8, NULL, 0);
243
244 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
245 floppy, idebus[0], idebus[1], rtc_state);
246
247 /* the rest devices to which pci devfn is automatically assigned */
248 pc_vga_init(isa_bus, host_bus);
249 pc_nic_init(isa_bus, host_bus);
250 if (pci_enabled) {
251 pc_pci_device_init(host_bus);
252 }
253 }
254
255 static void pc_compat_2_0(MachineState *machine)
256 {
257 smbios_legacy_mode = true;
258 has_reserved_memory = false;
259 }
260
261 static void pc_compat_1_7(MachineState *machine)
262 {
263 pc_compat_2_0(machine);
264 smbios_defaults = false;
265 gigabyte_align = false;
266 option_rom_has_mr = true;
267 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC);
268 }
269
270 static void pc_compat_1_6(MachineState *machine)
271 {
272 pc_compat_1_7(machine);
273 has_pci_info = false;
274 rom_file_has_mr = false;
275 has_acpi_build = false;
276 }
277
278 static void pc_compat_1_5(MachineState *machine)
279 {
280 pc_compat_1_6(machine);
281 }
282
283 static void pc_compat_1_4(MachineState *machine)
284 {
285 pc_compat_1_5(machine);
286 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
287 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
288 }
289
290 static void pc_q35_init_2_0(MachineState *machine)
291 {
292 pc_compat_2_0(machine);
293 pc_q35_init(machine);
294 }
295
296 static void pc_q35_init_1_7(MachineState *machine)
297 {
298 pc_compat_1_7(machine);
299 pc_q35_init(machine);
300 }
301
302 static void pc_q35_init_1_6(MachineState *machine)
303 {
304 pc_compat_1_6(machine);
305 pc_q35_init(machine);
306 }
307
308 static void pc_q35_init_1_5(MachineState *machine)
309 {
310 pc_compat_1_5(machine);
311 pc_q35_init(machine);
312 }
313
314 static void pc_q35_init_1_4(MachineState *machine)
315 {
316 pc_compat_1_4(machine);
317 pc_q35_init(machine);
318 }
319
320 #define PC_Q35_MACHINE_OPTIONS \
321 PC_DEFAULT_MACHINE_OPTIONS, \
322 .desc = "Standard PC (Q35 + ICH9, 2009)", \
323 .hot_add_cpu = pc_hot_add_cpu
324
325 #define PC_Q35_2_1_MACHINE_OPTIONS \
326 PC_Q35_MACHINE_OPTIONS, \
327 .default_machine_opts = "firmware=bios-256k.bin"
328
329 static QEMUMachine pc_q35_machine_v2_1 = {
330 PC_Q35_2_1_MACHINE_OPTIONS,
331 .name = "pc-q35-2.1",
332 .alias = "q35",
333 .init = pc_q35_init,
334 };
335
336 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
337
338 static QEMUMachine pc_q35_machine_v2_0 = {
339 PC_Q35_2_0_MACHINE_OPTIONS,
340 .name = "pc-q35-2.0",
341 .init = pc_q35_init_2_0,
342 .compat_props = (GlobalProperty[]) {
343 PC_Q35_COMPAT_2_0,
344 { /* end of list */ }
345 },
346 };
347
348 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
349
350 static QEMUMachine pc_q35_machine_v1_7 = {
351 PC_Q35_1_7_MACHINE_OPTIONS,
352 .name = "pc-q35-1.7",
353 .init = pc_q35_init_1_7,
354 .compat_props = (GlobalProperty[]) {
355 PC_Q35_COMPAT_1_7,
356 { /* end of list */ }
357 },
358 };
359
360 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
361
362 static QEMUMachine pc_q35_machine_v1_6 = {
363 PC_Q35_1_6_MACHINE_OPTIONS,
364 .name = "pc-q35-1.6",
365 .init = pc_q35_init_1_6,
366 .compat_props = (GlobalProperty[]) {
367 PC_Q35_COMPAT_1_6,
368 { /* end of list */ }
369 },
370 };
371
372 static QEMUMachine pc_q35_machine_v1_5 = {
373 PC_Q35_1_6_MACHINE_OPTIONS,
374 .name = "pc-q35-1.5",
375 .init = pc_q35_init_1_5,
376 .compat_props = (GlobalProperty[]) {
377 PC_Q35_COMPAT_1_5,
378 { /* end of list */ }
379 },
380 };
381
382 #define PC_Q35_1_4_MACHINE_OPTIONS \
383 PC_Q35_1_6_MACHINE_OPTIONS, \
384 .hot_add_cpu = NULL
385
386 static QEMUMachine pc_q35_machine_v1_4 = {
387 PC_Q35_1_4_MACHINE_OPTIONS,
388 .name = "pc-q35-1.4",
389 .init = pc_q35_init_1_4,
390 .compat_props = (GlobalProperty[]) {
391 PC_COMPAT_1_4,
392 { /* end of list */ }
393 },
394 };
395
396 static void pc_q35_machine_init(void)
397 {
398 qemu_register_pc_machine(&pc_q35_machine_v2_1);
399 qemu_register_pc_machine(&pc_q35_machine_v2_0);
400 qemu_register_pc_machine(&pc_q35_machine_v1_7);
401 qemu_register_pc_machine(&pc_q35_machine_v1_6);
402 qemu_register_pc_machine(&pc_q35_machine_v1_5);
403 qemu_register_pc_machine(&pc_q35_machine_v1_4);
404 }
405
406 machine_init(pc_q35_machine_init);