linux-user, arm: add syscall table generation support
[qemu.git] / hw / i386 / pc_q35.c
1 /*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/loader.h"
34 #include "sysemu/arch_init.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/xen/xen.h"
38 #include "sysemu/kvm.h"
39 #include "hw/kvm/clock.h"
40 #include "hw/pci-host/q35.h"
41 #include "hw/qdev-properties.h"
42 #include "exec/address-spaces.h"
43 #include "hw/i386/x86.h"
44 #include "hw/i386/pc.h"
45 #include "hw/i386/ich9.h"
46 #include "hw/i386/amd_iommu.h"
47 #include "hw/i386/intel_iommu.h"
48 #include "hw/display/ramfb.h"
49 #include "hw/firmware/smbios.h"
50 #include "hw/ide/pci.h"
51 #include "hw/ide/ahci.h"
52 #include "hw/usb.h"
53 #include "qapi/error.h"
54 #include "qemu/error-report.h"
55 #include "sysemu/numa.h"
56 #include "hw/mem/nvdimm.h"
57
58 /* ICH9 AHCI has 6 ports */
59 #define MAX_SATA_PORTS 6
60
61 struct ehci_companions {
62 const char *name;
63 int func;
64 int port;
65 };
66
67 static const struct ehci_companions ich9_1d[] = {
68 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
69 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
70 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
71 };
72
73 static const struct ehci_companions ich9_1a[] = {
74 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
75 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
76 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
77 };
78
79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
80 {
81 const struct ehci_companions *comp;
82 PCIDevice *ehci, *uhci;
83 BusState *usbbus;
84 const char *name;
85 int i;
86
87 switch (slot) {
88 case 0x1d:
89 name = "ich9-usb-ehci1";
90 comp = ich9_1d;
91 break;
92 case 0x1a:
93 name = "ich9-usb-ehci2";
94 comp = ich9_1a;
95 break;
96 default:
97 return -1;
98 }
99
100 ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
101 qdev_init_nofail(&ehci->qdev);
102 usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
103
104 for (i = 0; i < 3; i++) {
105 uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
106 true, comp[i].name);
107 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
108 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
109 qdev_init_nofail(&uhci->qdev);
110 }
111 return 0;
112 }
113
114 /* PC hardware initialisation */
115 static void pc_q35_init(MachineState *machine)
116 {
117 PCMachineState *pcms = PC_MACHINE(machine);
118 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
119 X86MachineState *x86ms = X86_MACHINE(machine);
120 Q35PCIHost *q35_host;
121 PCIHostState *phb;
122 PCIBus *host_bus;
123 PCIDevice *lpc;
124 DeviceState *lpc_dev;
125 BusState *idebus[MAX_SATA_PORTS];
126 ISADevice *rtc_state;
127 MemoryRegion *system_io = get_system_io();
128 MemoryRegion *pci_memory;
129 MemoryRegion *rom_memory;
130 MemoryRegion *ram_memory;
131 GSIState *gsi_state;
132 ISABus *isa_bus;
133 int i;
134 ICH9LPCState *ich9_lpc;
135 PCIDevice *ahci;
136 ram_addr_t lowmem;
137 DriveInfo *hd[MAX_SATA_PORTS];
138 MachineClass *mc = MACHINE_GET_CLASS(machine);
139
140 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
141 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
142 * also known as MMCFG).
143 * If it doesn't, we need to split it in chunks below and above 4G.
144 * In any case, try to make sure that guest addresses aligned at
145 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
146 */
147 if (machine->ram_size >= 0xb0000000) {
148 lowmem = 0x80000000;
149 } else {
150 lowmem = 0xb0000000;
151 }
152
153 /* Handle the machine opt max-ram-below-4g. It is basically doing
154 * min(qemu limit, user limit).
155 */
156 if (!x86ms->max_ram_below_4g) {
157 x86ms->max_ram_below_4g = 4 * GiB;
158 }
159 if (lowmem > x86ms->max_ram_below_4g) {
160 lowmem = x86ms->max_ram_below_4g;
161 if (machine->ram_size - lowmem > lowmem &&
162 lowmem & (1 * GiB - 1)) {
163 warn_report("There is possibly poor performance as the ram size "
164 " (0x%" PRIx64 ") is more then twice the size of"
165 " max-ram-below-4g (%"PRIu64") and"
166 " max-ram-below-4g is not a multiple of 1G.",
167 (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
168 }
169 }
170
171 if (machine->ram_size >= lowmem) {
172 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
173 x86ms->below_4g_mem_size = lowmem;
174 } else {
175 x86ms->above_4g_mem_size = 0;
176 x86ms->below_4g_mem_size = machine->ram_size;
177 }
178
179 if (xen_enabled()) {
180 xen_hvm_init(pcms, &ram_memory);
181 }
182
183 x86_cpus_init(x86ms, pcmc->default_cpu_version);
184
185 kvmclock_create();
186
187 /* pci enabled */
188 if (pcmc->pci_enabled) {
189 pci_memory = g_new(MemoryRegion, 1);
190 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
191 rom_memory = pci_memory;
192 } else {
193 pci_memory = NULL;
194 rom_memory = get_system_memory();
195 }
196
197 pc_guest_info_init(pcms);
198
199 if (pcmc->smbios_defaults) {
200 /* These values are guest ABI, do not change */
201 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
202 mc->name, pcmc->smbios_legacy_mode,
203 pcmc->smbios_uuid_encoded,
204 SMBIOS_ENTRY_POINT_21);
205 }
206
207 /* allocate ram and load rom/bios */
208 if (!xen_enabled()) {
209 pc_memory_init(pcms, get_system_memory(),
210 rom_memory, &ram_memory);
211 }
212
213 /* create pci host bus */
214 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
215
216 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
217 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
218 MCH_HOST_PROP_RAM_MEM, NULL);
219 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
220 MCH_HOST_PROP_PCI_MEM, NULL);
221 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
222 MCH_HOST_PROP_SYSTEM_MEM, NULL);
223 object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
224 MCH_HOST_PROP_IO_MEM, NULL);
225 object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size,
226 PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
227 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
228 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
229 /* pci */
230 qdev_init_nofail(DEVICE(q35_host));
231 phb = PCI_HOST_BRIDGE(q35_host);
232 host_bus = phb->bus;
233 /* create ISA bus */
234 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
235 ICH9_LPC_FUNC), true,
236 TYPE_ICH9_LPC_DEVICE);
237
238 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
239 TYPE_HOTPLUG_HANDLER,
240 (Object **)&pcms->acpi_dev,
241 object_property_allow_set_link,
242 OBJ_PROP_LINK_STRONG, &error_abort);
243 object_property_set_link(OBJECT(machine), OBJECT(lpc),
244 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
245
246 /* irq lines */
247 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
248
249 ich9_lpc = ICH9_LPC_DEVICE(lpc);
250 lpc_dev = DEVICE(lpc);
251 for (i = 0; i < GSI_NUM_PINS; i++) {
252 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
253 }
254 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
255 ICH9_LPC_NB_PIRQS);
256 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
257 isa_bus = ich9_lpc->isa_bus;
258
259 pc_i8259_create(isa_bus, gsi_state->i8259_irq);
260
261 if (pcmc->pci_enabled) {
262 ioapic_init_gsi(gsi_state, "q35");
263 }
264
265 if (tcg_enabled()) {
266 x86_register_ferr_irq(x86ms->gsi[13]);
267 }
268
269 assert(pcms->vmport != ON_OFF_AUTO__MAX);
270 if (pcms->vmport == ON_OFF_AUTO_AUTO) {
271 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
272 }
273
274 /* init basic PC hardware */
275 pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
276 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
277 0xff0104);
278
279 /* connect pm stuff to lpc */
280 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
281
282 if (pcms->sata_enabled) {
283 /* ahci and SATA device, for q35 1 ahci controller is built-in */
284 ahci = pci_create_simple_multifunction(host_bus,
285 PCI_DEVFN(ICH9_SATA1_DEV,
286 ICH9_SATA1_FUNC),
287 true, "ich9-ahci");
288 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
289 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
290 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
291 ide_drive_get(hd, ahci_get_num_ports(ahci));
292 ahci_ide_create_devs(ahci, hd);
293 } else {
294 idebus[0] = idebus[1] = NULL;
295 }
296
297 if (machine_usb(machine)) {
298 /* Should we create 6 UHCI according to ich9 spec? */
299 ehci_create_ich9_with_companions(host_bus, 0x1d);
300 }
301
302 if (pcms->smbus_enabled) {
303 /* TODO: Populate SPD eeprom data. */
304 pcms->smbus = ich9_smb_init(host_bus,
305 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
306 0xb100);
307 smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
308 }
309
310 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
311
312 /* the rest devices to which pci devfn is automatically assigned */
313 pc_vga_init(isa_bus, host_bus);
314 pc_nic_init(pcmc, isa_bus, host_bus);
315
316 if (machine->nvdimms_state->is_enabled) {
317 nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
318 x86ms->fw_cfg, OBJECT(pcms));
319 }
320 }
321
322 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
323 static void pc_init_##suffix(MachineState *machine) \
324 { \
325 void (*compat)(MachineState *m) = (compatfn); \
326 if (compat) { \
327 compat(machine); \
328 } \
329 pc_q35_init(machine); \
330 } \
331 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
332
333
334 static void pc_q35_machine_options(MachineClass *m)
335 {
336 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
337 pcmc->default_nic_model = "e1000e";
338
339 m->family = "pc_q35";
340 m->desc = "Standard PC (Q35 + ICH9, 2009)";
341 m->units_per_default_bus = 1;
342 m->default_machine_opts = "firmware=bios-256k.bin";
343 m->default_display = "std";
344 m->default_kernel_irqchip_split = false;
345 m->no_floppy = 1;
346 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
347 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
348 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
349 m->max_cpus = 288;
350 }
351
352 static void pc_q35_5_0_machine_options(MachineClass *m)
353 {
354 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
355 pc_q35_machine_options(m);
356 m->alias = "q35";
357 pcmc->default_cpu_version = 1;
358 }
359
360 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
361 pc_q35_5_0_machine_options);
362
363 static void pc_q35_4_2_machine_options(MachineClass *m)
364 {
365 pc_q35_5_0_machine_options(m);
366 m->alias = NULL;
367 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
368 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
369 }
370
371 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
372 pc_q35_4_2_machine_options);
373
374 static void pc_q35_4_1_machine_options(MachineClass *m)
375 {
376 pc_q35_4_2_machine_options(m);
377 m->alias = NULL;
378 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
379 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
380 }
381
382 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
383 pc_q35_4_1_machine_options);
384
385 static void pc_q35_4_0_1_machine_options(MachineClass *m)
386 {
387 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
388 pc_q35_4_1_machine_options(m);
389 m->alias = NULL;
390 pcmc->default_cpu_version = CPU_VERSION_LEGACY;
391 /*
392 * This is the default machine for the 4.0-stable branch. It is basically
393 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
394 * 4.0 compat props.
395 */
396 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
397 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
398 }
399
400 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
401 pc_q35_4_0_1_machine_options);
402
403 static void pc_q35_4_0_machine_options(MachineClass *m)
404 {
405 pc_q35_4_0_1_machine_options(m);
406 m->default_kernel_irqchip_split = true;
407 m->alias = NULL;
408 /* Compat props are applied by the 4.0.1 machine */
409 }
410
411 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
412 pc_q35_4_0_machine_options);
413
414 static void pc_q35_3_1_machine_options(MachineClass *m)
415 {
416 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
417
418 pc_q35_4_0_machine_options(m);
419 m->default_kernel_irqchip_split = false;
420 pcmc->do_not_add_smb_acpi = true;
421 m->smbus_no_migration_support = true;
422 m->alias = NULL;
423 pcmc->pvh_enabled = false;
424 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
425 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
426 }
427
428 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
429 pc_q35_3_1_machine_options);
430
431 static void pc_q35_3_0_machine_options(MachineClass *m)
432 {
433 pc_q35_3_1_machine_options(m);
434 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
435 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
436 }
437
438 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
439 pc_q35_3_0_machine_options);
440
441 static void pc_q35_2_12_machine_options(MachineClass *m)
442 {
443 pc_q35_3_0_machine_options(m);
444 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
445 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
446 }
447
448 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
449 pc_q35_2_12_machine_options);
450
451 static void pc_q35_2_11_machine_options(MachineClass *m)
452 {
453 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
454
455 pc_q35_2_12_machine_options(m);
456 pcmc->default_nic_model = "e1000";
457 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
458 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
459 }
460
461 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
462 pc_q35_2_11_machine_options);
463
464 static void pc_q35_2_10_machine_options(MachineClass *m)
465 {
466 pc_q35_2_11_machine_options(m);
467 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
468 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
469 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
470 m->auto_enable_numa_with_memhp = false;
471 }
472
473 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
474 pc_q35_2_10_machine_options);
475
476 static void pc_q35_2_9_machine_options(MachineClass *m)
477 {
478 pc_q35_2_10_machine_options(m);
479 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
480 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
481 }
482
483 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
484 pc_q35_2_9_machine_options);
485
486 static void pc_q35_2_8_machine_options(MachineClass *m)
487 {
488 pc_q35_2_9_machine_options(m);
489 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
490 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
491 }
492
493 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
494 pc_q35_2_8_machine_options);
495
496 static void pc_q35_2_7_machine_options(MachineClass *m)
497 {
498 pc_q35_2_8_machine_options(m);
499 m->max_cpus = 255;
500 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
501 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
502 }
503
504 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
505 pc_q35_2_7_machine_options);
506
507 static void pc_q35_2_6_machine_options(MachineClass *m)
508 {
509 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
510
511 pc_q35_2_7_machine_options(m);
512 pcmc->legacy_cpu_hotplug = true;
513 pcmc->linuxboot_dma_enabled = false;
514 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
515 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
516 }
517
518 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
519 pc_q35_2_6_machine_options);
520
521 static void pc_q35_2_5_machine_options(MachineClass *m)
522 {
523 X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
524
525 pc_q35_2_6_machine_options(m);
526 x86mc->save_tsc_khz = false;
527 m->legacy_fw_cfg_order = 1;
528 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
529 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
530 }
531
532 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
533 pc_q35_2_5_machine_options);
534
535 static void pc_q35_2_4_machine_options(MachineClass *m)
536 {
537 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
538
539 pc_q35_2_5_machine_options(m);
540 m->hw_version = "2.4.0";
541 pcmc->broken_reserved_end = true;
542 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
543 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
544 }
545
546 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
547 pc_q35_2_4_machine_options);