accel: Move Xen accelerator code under accel/xen/
[qemu.git] / hw / i386 / pc_q35.c
1 /*
2 * Q35 chipset based pc system emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on pc.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/loader.h"
34 #include "sysemu/arch_init.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/xen/xen.h"
38 #include "sysemu/kvm.h"
39 #include "sysemu/xen.h"
40 #include "hw/kvm/clock.h"
41 #include "hw/pci-host/q35.h"
42 #include "hw/qdev-properties.h"
43 #include "exec/address-spaces.h"
44 #include "hw/i386/x86.h"
45 #include "hw/i386/pc.h"
46 #include "hw/i386/ich9.h"
47 #include "hw/i386/amd_iommu.h"
48 #include "hw/i386/intel_iommu.h"
49 #include "hw/display/ramfb.h"
50 #include "hw/firmware/smbios.h"
51 #include "hw/ide/pci.h"
52 #include "hw/ide/ahci.h"
53 #include "hw/usb.h"
54 #include "qapi/error.h"
55 #include "qemu/error-report.h"
56 #include "sysemu/numa.h"
57 #include "hw/hyperv/vmbus-bridge.h"
58 #include "hw/mem/nvdimm.h"
59 #include "hw/i386/acpi-build.h"
60
61 /* ICH9 AHCI has 6 ports */
62 #define MAX_SATA_PORTS 6
63
64 struct ehci_companions {
65 const char *name;
66 int func;
67 int port;
68 };
69
70 static const struct ehci_companions ich9_1d[] = {
71 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
72 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
73 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
74 };
75
76 static const struct ehci_companions ich9_1a[] = {
77 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
78 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
79 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
80 };
81
82 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
83 {
84 const struct ehci_companions *comp;
85 PCIDevice *ehci, *uhci;
86 BusState *usbbus;
87 const char *name;
88 int i;
89
90 switch (slot) {
91 case 0x1d:
92 name = "ich9-usb-ehci1";
93 comp = ich9_1d;
94 break;
95 case 0x1a:
96 name = "ich9-usb-ehci2";
97 comp = ich9_1a;
98 break;
99 default:
100 return -1;
101 }
102
103 ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name);
104 qdev_init_nofail(&ehci->qdev);
105 usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
106
107 for (i = 0; i < 3; i++) {
108 uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func),
109 true, comp[i].name);
110 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
111 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
112 qdev_init_nofail(&uhci->qdev);
113 }
114 return 0;
115 }
116
117 /* PC hardware initialisation */
118 static void pc_q35_init(MachineState *machine)
119 {
120 PCMachineState *pcms = PC_MACHINE(machine);
121 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
122 X86MachineState *x86ms = X86_MACHINE(machine);
123 Q35PCIHost *q35_host;
124 PCIHostState *phb;
125 PCIBus *host_bus;
126 PCIDevice *lpc;
127 DeviceState *lpc_dev;
128 BusState *idebus[MAX_SATA_PORTS];
129 ISADevice *rtc_state;
130 MemoryRegion *system_io = get_system_io();
131 MemoryRegion *pci_memory;
132 MemoryRegion *rom_memory;
133 MemoryRegion *ram_memory;
134 GSIState *gsi_state;
135 ISABus *isa_bus;
136 int i;
137 ICH9LPCState *ich9_lpc;
138 PCIDevice *ahci;
139 ram_addr_t lowmem;
140 DriveInfo *hd[MAX_SATA_PORTS];
141 MachineClass *mc = MACHINE_GET_CLASS(machine);
142
143 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
144 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
145 * also known as MMCFG).
146 * If it doesn't, we need to split it in chunks below and above 4G.
147 * In any case, try to make sure that guest addresses aligned at
148 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
149 */
150 if (machine->ram_size >= 0xb0000000) {
151 lowmem = 0x80000000;
152 } else {
153 lowmem = 0xb0000000;
154 }
155
156 /* Handle the machine opt max-ram-below-4g. It is basically doing
157 * min(qemu limit, user limit).
158 */
159 if (!x86ms->max_ram_below_4g) {
160 x86ms->max_ram_below_4g = 4 * GiB;
161 }
162 if (lowmem > x86ms->max_ram_below_4g) {
163 lowmem = x86ms->max_ram_below_4g;
164 if (machine->ram_size - lowmem > lowmem &&
165 lowmem & (1 * GiB - 1)) {
166 warn_report("There is possibly poor performance as the ram size "
167 " (0x%" PRIx64 ") is more then twice the size of"
168 " max-ram-below-4g (%"PRIu64") and"
169 " max-ram-below-4g is not a multiple of 1G.",
170 (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
171 }
172 }
173
174 if (machine->ram_size >= lowmem) {
175 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
176 x86ms->below_4g_mem_size = lowmem;
177 } else {
178 x86ms->above_4g_mem_size = 0;
179 x86ms->below_4g_mem_size = machine->ram_size;
180 }
181
182 if (xen_enabled()) {
183 xen_hvm_init(pcms, &ram_memory);
184 }
185
186 x86_cpus_init(x86ms, pcmc->default_cpu_version);
187
188 kvmclock_create();
189
190 /* pci enabled */
191 if (pcmc->pci_enabled) {
192 pci_memory = g_new(MemoryRegion, 1);
193 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
194 rom_memory = pci_memory;
195 } else {
196 pci_memory = NULL;
197 rom_memory = get_system_memory();
198 }
199
200 pc_guest_info_init(pcms);
201
202 if (pcmc->smbios_defaults) {
203 /* These values are guest ABI, do not change */
204 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
205 mc->name, pcmc->smbios_legacy_mode,
206 pcmc->smbios_uuid_encoded,
207 SMBIOS_ENTRY_POINT_21);
208 }
209
210 /* allocate ram and load rom/bios */
211 if (!xen_enabled()) {
212 pc_memory_init(pcms, get_system_memory(),
213 rom_memory, &ram_memory);
214 }
215
216 /* create pci host bus */
217 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
218
219 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
220 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
221 MCH_HOST_PROP_RAM_MEM, NULL);
222 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
223 MCH_HOST_PROP_PCI_MEM, NULL);
224 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
225 MCH_HOST_PROP_SYSTEM_MEM, NULL);
226 object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
227 MCH_HOST_PROP_IO_MEM, NULL);
228 object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size,
229 PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
230 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
231 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
232 /* pci */
233 qdev_init_nofail(DEVICE(q35_host));
234 phb = PCI_HOST_BRIDGE(q35_host);
235 host_bus = phb->bus;
236 /* create ISA bus */
237 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
238 ICH9_LPC_FUNC), true,
239 TYPE_ICH9_LPC_DEVICE);
240
241 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
242 TYPE_HOTPLUG_HANDLER,
243 (Object **)&pcms->acpi_dev,
244 object_property_allow_set_link,
245 OBJ_PROP_LINK_STRONG);
246 object_property_set_link(OBJECT(machine), OBJECT(lpc),
247 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
248
249 /* irq lines */
250 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
251
252 ich9_lpc = ICH9_LPC_DEVICE(lpc);
253 lpc_dev = DEVICE(lpc);
254 for (i = 0; i < GSI_NUM_PINS; i++) {
255 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
256 }
257 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
258 ICH9_LPC_NB_PIRQS);
259 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
260 isa_bus = ich9_lpc->isa_bus;
261
262 pc_i8259_create(isa_bus, gsi_state->i8259_irq);
263
264 if (pcmc->pci_enabled) {
265 ioapic_init_gsi(gsi_state, "q35");
266 }
267
268 if (tcg_enabled()) {
269 x86_register_ferr_irq(x86ms->gsi[13]);
270 }
271
272 assert(pcms->vmport != ON_OFF_AUTO__MAX);
273 if (pcms->vmport == ON_OFF_AUTO_AUTO) {
274 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
275 }
276
277 /* init basic PC hardware */
278 pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
279 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
280 0xff0104);
281
282 /* connect pm stuff to lpc */
283 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
284
285 if (pcms->sata_enabled) {
286 /* ahci and SATA device, for q35 1 ahci controller is built-in */
287 ahci = pci_create_simple_multifunction(host_bus,
288 PCI_DEVFN(ICH9_SATA1_DEV,
289 ICH9_SATA1_FUNC),
290 true, "ich9-ahci");
291 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
292 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
293 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
294 ide_drive_get(hd, ahci_get_num_ports(ahci));
295 ahci_ide_create_devs(ahci, hd);
296 } else {
297 idebus[0] = idebus[1] = NULL;
298 }
299
300 if (machine_usb(machine)) {
301 /* Should we create 6 UHCI according to ich9 spec? */
302 ehci_create_ich9_with_companions(host_bus, 0x1d);
303 }
304
305 if (pcms->smbus_enabled) {
306 /* TODO: Populate SPD eeprom data. */
307 pcms->smbus = ich9_smb_init(host_bus,
308 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
309 0xb100);
310 smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
311 }
312
313 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
314
315 /* the rest devices to which pci devfn is automatically assigned */
316 pc_vga_init(isa_bus, host_bus);
317 pc_nic_init(pcmc, isa_bus, host_bus);
318
319 if (machine->nvdimms_state->is_enabled) {
320 nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
321 x86_nvdimm_acpi_dsmio,
322 x86ms->fw_cfg, OBJECT(pcms));
323 }
324 }
325
326 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
327 static void pc_init_##suffix(MachineState *machine) \
328 { \
329 void (*compat)(MachineState *m) = (compatfn); \
330 if (compat) { \
331 compat(machine); \
332 } \
333 pc_q35_init(machine); \
334 } \
335 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
336
337
338 static void pc_q35_machine_options(MachineClass *m)
339 {
340 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
341 pcmc->default_nic_model = "e1000e";
342
343 m->family = "pc_q35";
344 m->desc = "Standard PC (Q35 + ICH9, 2009)";
345 m->units_per_default_bus = 1;
346 m->default_machine_opts = "firmware=bios-256k.bin";
347 m->default_display = "std";
348 m->default_kernel_irqchip_split = false;
349 m->no_floppy = 1;
350 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
351 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
352 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
353 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
354 m->max_cpus = 288;
355 }
356
357 static void pc_q35_5_1_machine_options(MachineClass *m)
358 {
359 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
360 pc_q35_machine_options(m);
361 m->alias = "q35";
362 pcmc->default_cpu_version = 1;
363 }
364
365 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
366 pc_q35_5_1_machine_options);
367
368 static void pc_q35_5_0_machine_options(MachineClass *m)
369 {
370 pc_q35_5_1_machine_options(m);
371 m->alias = NULL;
372 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
373 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
374 }
375
376 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
377 pc_q35_5_0_machine_options);
378
379 static void pc_q35_4_2_machine_options(MachineClass *m)
380 {
381 pc_q35_5_0_machine_options(m);
382 m->alias = NULL;
383 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
384 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
385 }
386
387 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
388 pc_q35_4_2_machine_options);
389
390 static void pc_q35_4_1_machine_options(MachineClass *m)
391 {
392 pc_q35_4_2_machine_options(m);
393 m->alias = NULL;
394 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
395 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
396 }
397
398 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
399 pc_q35_4_1_machine_options);
400
401 static void pc_q35_4_0_1_machine_options(MachineClass *m)
402 {
403 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
404 pc_q35_4_1_machine_options(m);
405 m->alias = NULL;
406 pcmc->default_cpu_version = CPU_VERSION_LEGACY;
407 /*
408 * This is the default machine for the 4.0-stable branch. It is basically
409 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
410 * 4.0 compat props.
411 */
412 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
413 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
414 }
415
416 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
417 pc_q35_4_0_1_machine_options);
418
419 static void pc_q35_4_0_machine_options(MachineClass *m)
420 {
421 pc_q35_4_0_1_machine_options(m);
422 m->default_kernel_irqchip_split = true;
423 m->alias = NULL;
424 /* Compat props are applied by the 4.0.1 machine */
425 }
426
427 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
428 pc_q35_4_0_machine_options);
429
430 static void pc_q35_3_1_machine_options(MachineClass *m)
431 {
432 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
433
434 pc_q35_4_0_machine_options(m);
435 m->default_kernel_irqchip_split = false;
436 pcmc->do_not_add_smb_acpi = true;
437 m->smbus_no_migration_support = true;
438 m->alias = NULL;
439 pcmc->pvh_enabled = false;
440 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
441 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
442 }
443
444 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
445 pc_q35_3_1_machine_options);
446
447 static void pc_q35_3_0_machine_options(MachineClass *m)
448 {
449 pc_q35_3_1_machine_options(m);
450 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
451 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
452 }
453
454 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
455 pc_q35_3_0_machine_options);
456
457 static void pc_q35_2_12_machine_options(MachineClass *m)
458 {
459 pc_q35_3_0_machine_options(m);
460 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
461 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
462 }
463
464 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
465 pc_q35_2_12_machine_options);
466
467 static void pc_q35_2_11_machine_options(MachineClass *m)
468 {
469 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
470
471 pc_q35_2_12_machine_options(m);
472 pcmc->default_nic_model = "e1000";
473 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
474 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
475 }
476
477 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
478 pc_q35_2_11_machine_options);
479
480 static void pc_q35_2_10_machine_options(MachineClass *m)
481 {
482 pc_q35_2_11_machine_options(m);
483 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
484 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
485 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
486 m->auto_enable_numa_with_memhp = false;
487 }
488
489 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
490 pc_q35_2_10_machine_options);
491
492 static void pc_q35_2_9_machine_options(MachineClass *m)
493 {
494 pc_q35_2_10_machine_options(m);
495 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
496 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
497 }
498
499 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
500 pc_q35_2_9_machine_options);
501
502 static void pc_q35_2_8_machine_options(MachineClass *m)
503 {
504 pc_q35_2_9_machine_options(m);
505 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
506 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
507 }
508
509 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
510 pc_q35_2_8_machine_options);
511
512 static void pc_q35_2_7_machine_options(MachineClass *m)
513 {
514 pc_q35_2_8_machine_options(m);
515 m->max_cpus = 255;
516 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
517 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
518 }
519
520 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
521 pc_q35_2_7_machine_options);
522
523 static void pc_q35_2_6_machine_options(MachineClass *m)
524 {
525 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
526
527 pc_q35_2_7_machine_options(m);
528 pcmc->legacy_cpu_hotplug = true;
529 pcmc->linuxboot_dma_enabled = false;
530 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
531 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
532 }
533
534 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
535 pc_q35_2_6_machine_options);
536
537 static void pc_q35_2_5_machine_options(MachineClass *m)
538 {
539 X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
540
541 pc_q35_2_6_machine_options(m);
542 x86mc->save_tsc_khz = false;
543 m->legacy_fw_cfg_order = 1;
544 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
545 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
546 }
547
548 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
549 pc_q35_2_5_machine_options);
550
551 static void pc_q35_2_4_machine_options(MachineClass *m)
552 {
553 PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
554
555 pc_q35_2_5_machine_options(m);
556 m->hw_version = "2.4.0";
557 pcmc->broken_reserved_end = true;
558 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
559 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
560 }
561
562 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
563 pc_q35_2_4_machine_options);