hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / i386 / x86.c
1 /*
2 * Copyright (c) 2003-2004 Fabrice Bellard
3 * Copyright (c) 2019 Red Hat, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 */
23 #include "qemu/osdep.h"
24 #include "qemu/error-report.h"
25 #include "qemu/option.h"
26 #include "qemu/cutils.h"
27 #include "qemu/units.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/qmp/qerror.h"
31 #include "qapi/qapi-visit-common.h"
32 #include "qapi/visitor.h"
33 #include "sysemu/qtest.h"
34 #include "sysemu/numa.h"
35 #include "sysemu/replay.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/cpu-timers.h"
38 #include "trace.h"
39
40 #include "hw/i386/x86.h"
41 #include "target/i386/cpu.h"
42 #include "hw/i386/topology.h"
43 #include "hw/i386/fw_cfg.h"
44 #include "hw/intc/i8259.h"
45 #include "hw/rtc/mc146818rtc.h"
46
47 #include "hw/acpi/cpu_hotplug.h"
48 #include "hw/irq.h"
49 #include "hw/nmi.h"
50 #include "hw/loader.h"
51 #include "multiboot.h"
52 #include "elf.h"
53 #include "standard-headers/asm-x86/bootparam.h"
54 #include CONFIG_DEVICES
55 #include "kvm_i386.h"
56
57 #define BIOS_FILENAME "bios.bin"
58
59 /* Physical Address of PVH entry point read from kernel ELF NOTE */
60 static size_t pvh_start_addr;
61
62 inline void init_topo_info(X86CPUTopoInfo *topo_info,
63 const X86MachineState *x86ms)
64 {
65 MachineState *ms = MACHINE(x86ms);
66
67 topo_info->dies_per_pkg = x86ms->smp_dies;
68 topo_info->cores_per_die = ms->smp.cores;
69 topo_info->threads_per_core = ms->smp.threads;
70 }
71
72 /*
73 * Calculates initial APIC ID for a specific CPU index
74 *
75 * Currently we need to be able to calculate the APIC ID from the CPU index
76 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
77 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
78 * all CPUs up to max_cpus.
79 */
80 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
81 unsigned int cpu_index)
82 {
83 X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
84 X86CPUTopoInfo topo_info;
85 uint32_t correct_id;
86 static bool warned;
87
88 init_topo_info(&topo_info, x86ms);
89
90 correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
91 if (x86mc->compat_apic_id_mode) {
92 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
93 error_report("APIC IDs set in compatibility mode, "
94 "CPU topology won't match the configuration");
95 warned = true;
96 }
97 return cpu_index;
98 } else {
99 return correct_id;
100 }
101 }
102
103
104 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
105 {
106 Object *cpu = object_new(MACHINE(x86ms)->cpu_type);
107
108 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) {
109 goto out;
110 }
111 qdev_realize(DEVICE(cpu), NULL, errp);
112
113 out:
114 object_unref(cpu);
115 }
116
117 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
118 {
119 int i;
120 const CPUArchIdList *possible_cpus;
121 MachineState *ms = MACHINE(x86ms);
122 MachineClass *mc = MACHINE_GET_CLASS(x86ms);
123
124 x86_cpu_set_default_version(default_cpu_version);
125
126 /*
127 * Calculates the limit to CPU APIC ID values
128 *
129 * Limit for the APIC ID value, so that all
130 * CPU APIC IDs are < x86ms->apic_id_limit.
131 *
132 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
133 */
134 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
135 ms->smp.max_cpus - 1) + 1;
136 possible_cpus = mc->possible_cpu_arch_ids(ms);
137 for (i = 0; i < ms->smp.cpus; i++) {
138 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
139 }
140 }
141
142 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
143 {
144 if (cpus_count > 0xff) {
145 /*
146 * If the number of CPUs can't be represented in 8 bits, the
147 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
148 * to make old BIOSes fail more predictably.
149 */
150 rtc_set_memory(rtc, 0x5f, 0);
151 } else {
152 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
153 }
154 }
155
156 static int x86_apic_cmp(const void *a, const void *b)
157 {
158 CPUArchId *apic_a = (CPUArchId *)a;
159 CPUArchId *apic_b = (CPUArchId *)b;
160
161 return apic_a->arch_id - apic_b->arch_id;
162 }
163
164 /*
165 * returns pointer to CPUArchId descriptor that matches CPU's apic_id
166 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
167 * entry corresponding to CPU's apic_id returns NULL.
168 */
169 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
170 {
171 CPUArchId apic_id, *found_cpu;
172
173 apic_id.arch_id = id;
174 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
175 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
176 x86_apic_cmp);
177 if (found_cpu && idx) {
178 *idx = found_cpu - ms->possible_cpus->cpus;
179 }
180 return found_cpu;
181 }
182
183 void x86_cpu_plug(HotplugHandler *hotplug_dev,
184 DeviceState *dev, Error **errp)
185 {
186 CPUArchId *found_cpu;
187 Error *local_err = NULL;
188 X86CPU *cpu = X86_CPU(dev);
189 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
190
191 if (x86ms->acpi_dev) {
192 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err);
193 if (local_err) {
194 goto out;
195 }
196 }
197
198 /* increment the number of CPUs */
199 x86ms->boot_cpus++;
200 if (x86ms->rtc) {
201 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
202 }
203 if (x86ms->fw_cfg) {
204 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
205 }
206
207 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL);
208 found_cpu->cpu = OBJECT(dev);
209 out:
210 error_propagate(errp, local_err);
211 }
212
213 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
214 DeviceState *dev, Error **errp)
215 {
216 int idx = -1;
217 X86CPU *cpu = X86_CPU(dev);
218 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
219
220 if (!x86ms->acpi_dev) {
221 error_setg(errp, "CPU hot unplug not supported without ACPI");
222 return;
223 }
224
225 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx);
226 assert(idx != -1);
227 if (idx == 0) {
228 error_setg(errp, "Boot CPU is unpluggable");
229 return;
230 }
231
232 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
233 errp);
234 }
235
236 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
237 DeviceState *dev, Error **errp)
238 {
239 CPUArchId *found_cpu;
240 Error *local_err = NULL;
241 X86CPU *cpu = X86_CPU(dev);
242 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
243
244 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
245 if (local_err) {
246 goto out;
247 }
248
249 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL);
250 found_cpu->cpu = NULL;
251 qdev_unrealize(dev);
252
253 /* decrement the number of CPUs */
254 x86ms->boot_cpus--;
255 /* Update the number of CPUs in CMOS */
256 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
257 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
258 out:
259 error_propagate(errp, local_err);
260 }
261
262 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
263 DeviceState *dev, Error **errp)
264 {
265 int idx;
266 CPUState *cs;
267 CPUArchId *cpu_slot;
268 X86CPUTopoIDs topo_ids;
269 X86CPU *cpu = X86_CPU(dev);
270 CPUX86State *env = &cpu->env;
271 MachineState *ms = MACHINE(hotplug_dev);
272 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
273 unsigned int smp_cores = ms->smp.cores;
274 unsigned int smp_threads = ms->smp.threads;
275 X86CPUTopoInfo topo_info;
276
277 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
278 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
279 ms->cpu_type);
280 return;
281 }
282
283 if (x86ms->acpi_dev) {
284 Error *local_err = NULL;
285
286 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev,
287 &local_err);
288 if (local_err) {
289 error_propagate(errp, local_err);
290 return;
291 }
292 }
293
294 init_topo_info(&topo_info, x86ms);
295
296 env->nr_dies = x86ms->smp_dies;
297
298 /*
299 * If APIC ID is not set,
300 * set it based on socket/die/core/thread properties.
301 */
302 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
303 int max_socket = (ms->smp.max_cpus - 1) /
304 smp_threads / smp_cores / x86ms->smp_dies;
305
306 /*
307 * die-id was optional in QEMU 4.0 and older, so keep it optional
308 * if there's only one die per socket.
309 */
310 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
311 cpu->die_id = 0;
312 }
313
314 if (cpu->socket_id < 0) {
315 error_setg(errp, "CPU socket-id is not set");
316 return;
317 } else if (cpu->socket_id > max_socket) {
318 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
319 cpu->socket_id, max_socket);
320 return;
321 }
322 if (cpu->die_id < 0) {
323 error_setg(errp, "CPU die-id is not set");
324 return;
325 } else if (cpu->die_id > x86ms->smp_dies - 1) {
326 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
327 cpu->die_id, x86ms->smp_dies - 1);
328 return;
329 }
330 if (cpu->core_id < 0) {
331 error_setg(errp, "CPU core-id is not set");
332 return;
333 } else if (cpu->core_id > (smp_cores - 1)) {
334 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
335 cpu->core_id, smp_cores - 1);
336 return;
337 }
338 if (cpu->thread_id < 0) {
339 error_setg(errp, "CPU thread-id is not set");
340 return;
341 } else if (cpu->thread_id > (smp_threads - 1)) {
342 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
343 cpu->thread_id, smp_threads - 1);
344 return;
345 }
346
347 topo_ids.pkg_id = cpu->socket_id;
348 topo_ids.die_id = cpu->die_id;
349 topo_ids.core_id = cpu->core_id;
350 topo_ids.smt_id = cpu->thread_id;
351 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
352 }
353
354 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx);
355 if (!cpu_slot) {
356 MachineState *ms = MACHINE(x86ms);
357
358 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
359 error_setg(errp,
360 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
361 " APIC ID %" PRIu32 ", valid index range 0:%d",
362 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,
363 cpu->apic_id, ms->possible_cpus->len - 1);
364 return;
365 }
366
367 if (cpu_slot->cpu) {
368 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
369 idx, cpu->apic_id);
370 return;
371 }
372
373 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
374 * so that machine_query_hotpluggable_cpus would show correct values
375 */
376 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
377 * once -smp refactoring is complete and there will be CPU private
378 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
379 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
380 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
381 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
382 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
383 topo_ids.pkg_id);
384 return;
385 }
386 cpu->socket_id = topo_ids.pkg_id;
387
388 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
389 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
390 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
391 return;
392 }
393 cpu->die_id = topo_ids.die_id;
394
395 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
396 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
397 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
398 topo_ids.core_id);
399 return;
400 }
401 cpu->core_id = topo_ids.core_id;
402
403 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
404 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
405 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
406 topo_ids.smt_id);
407 return;
408 }
409 cpu->thread_id = topo_ids.smt_id;
410
411 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
412 !kvm_hv_vpindex_settable()) {
413 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
414 return;
415 }
416
417 cs = CPU(cpu);
418 cs->cpu_index = idx;
419
420 numa_cpu_pre_plug(cpu_slot, dev, errp);
421 }
422
423 CpuInstanceProperties
424 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
425 {
426 MachineClass *mc = MACHINE_GET_CLASS(ms);
427 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
428
429 assert(cpu_index < possible_cpus->len);
430 return possible_cpus->cpus[cpu_index].props;
431 }
432
433 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
434 {
435 X86CPUTopoIDs topo_ids;
436 X86MachineState *x86ms = X86_MACHINE(ms);
437 X86CPUTopoInfo topo_info;
438
439 init_topo_info(&topo_info, x86ms);
440
441 assert(idx < ms->possible_cpus->len);
442 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
443 &topo_info, &topo_ids);
444 return topo_ids.pkg_id % ms->numa_state->num_nodes;
445 }
446
447 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
448 {
449 X86MachineState *x86ms = X86_MACHINE(ms);
450 unsigned int max_cpus = ms->smp.max_cpus;
451 X86CPUTopoInfo topo_info;
452 int i;
453
454 if (ms->possible_cpus) {
455 /*
456 * make sure that max_cpus hasn't changed since the first use, i.e.
457 * -smp hasn't been parsed after it
458 */
459 assert(ms->possible_cpus->len == max_cpus);
460 return ms->possible_cpus;
461 }
462
463 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
464 sizeof(CPUArchId) * max_cpus);
465 ms->possible_cpus->len = max_cpus;
466
467 init_topo_info(&topo_info, x86ms);
468
469 for (i = 0; i < ms->possible_cpus->len; i++) {
470 X86CPUTopoIDs topo_ids;
471
472 ms->possible_cpus->cpus[i].type = ms->cpu_type;
473 ms->possible_cpus->cpus[i].vcpus_count = 1;
474 ms->possible_cpus->cpus[i].arch_id =
475 x86_cpu_apic_id_from_index(x86ms, i);
476 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
477 &topo_info, &topo_ids);
478 ms->possible_cpus->cpus[i].props.has_socket_id = true;
479 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
480 if (x86ms->smp_dies > 1) {
481 ms->possible_cpus->cpus[i].props.has_die_id = true;
482 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
483 }
484 ms->possible_cpus->cpus[i].props.has_core_id = true;
485 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
486 ms->possible_cpus->cpus[i].props.has_thread_id = true;
487 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id;
488 }
489 return ms->possible_cpus;
490 }
491
492 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
493 {
494 /* cpu index isn't used */
495 CPUState *cs;
496
497 CPU_FOREACH(cs) {
498 X86CPU *cpu = X86_CPU(cs);
499
500 if (!cpu->apic_state) {
501 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
502 } else {
503 apic_deliver_nmi(cpu->apic_state);
504 }
505 }
506 }
507
508 static long get_file_size(FILE *f)
509 {
510 long where, size;
511
512 /* XXX: on Unix systems, using fstat() probably makes more sense */
513
514 where = ftell(f);
515 fseek(f, 0, SEEK_END);
516 size = ftell(f);
517 fseek(f, where, SEEK_SET);
518
519 return size;
520 }
521
522 /* TSC handling */
523 uint64_t cpu_get_tsc(CPUX86State *env)
524 {
525 return cpus_get_elapsed_ticks();
526 }
527
528 /* IRQ handling */
529 static void pic_irq_request(void *opaque, int irq, int level)
530 {
531 CPUState *cs = first_cpu;
532 X86CPU *cpu = X86_CPU(cs);
533
534 trace_x86_pic_interrupt(irq, level);
535 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
536 CPU_FOREACH(cs) {
537 cpu = X86_CPU(cs);
538 if (apic_accept_pic_intr(cpu->apic_state)) {
539 apic_deliver_pic_intr(cpu->apic_state, level);
540 }
541 }
542 } else {
543 if (level) {
544 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
545 } else {
546 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
547 }
548 }
549 }
550
551 qemu_irq x86_allocate_cpu_irq(void)
552 {
553 return qemu_allocate_irq(pic_irq_request, NULL, 0);
554 }
555
556 int cpu_get_pic_interrupt(CPUX86State *env)
557 {
558 X86CPU *cpu = env_archcpu(env);
559 int intno;
560
561 if (!kvm_irqchip_in_kernel()) {
562 intno = apic_get_interrupt(cpu->apic_state);
563 if (intno >= 0) {
564 return intno;
565 }
566 /* read the irq from the PIC */
567 if (!apic_accept_pic_intr(cpu->apic_state)) {
568 return -1;
569 }
570 }
571
572 intno = pic_read_irq(isa_pic);
573 return intno;
574 }
575
576 DeviceState *cpu_get_current_apic(void)
577 {
578 if (current_cpu) {
579 X86CPU *cpu = X86_CPU(current_cpu);
580 return cpu->apic_state;
581 } else {
582 return NULL;
583 }
584 }
585
586 void gsi_handler(void *opaque, int n, int level)
587 {
588 GSIState *s = opaque;
589
590 trace_x86_gsi_interrupt(n, level);
591 if (n < ISA_NUM_IRQS) {
592 /* Under KVM, Kernel will forward to both PIC and IOAPIC */
593 qemu_set_irq(s->i8259_irq[n], level);
594 }
595 qemu_set_irq(s->ioapic_irq[n], level);
596 }
597
598 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
599 {
600 DeviceState *dev;
601 SysBusDevice *d;
602 unsigned int i;
603
604 assert(parent_name);
605 if (kvm_ioapic_in_kernel()) {
606 dev = qdev_new(TYPE_KVM_IOAPIC);
607 } else {
608 dev = qdev_new(TYPE_IOAPIC);
609 }
610 object_property_add_child(object_resolve_path(parent_name, NULL),
611 "ioapic", OBJECT(dev));
612 d = SYS_BUS_DEVICE(dev);
613 sysbus_realize_and_unref(d, &error_fatal);
614 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
615
616 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
617 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
618 }
619 }
620
621 struct setup_data {
622 uint64_t next;
623 uint32_t type;
624 uint32_t len;
625 uint8_t data[];
626 } __attribute__((packed));
627
628
629 /*
630 * The entry point into the kernel for PVH boot is different from
631 * the native entry point. The PVH entry is defined by the x86/HVM
632 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
633 *
634 * This function is passed to load_elf() when it is called from
635 * load_elfboot() which then additionally checks for an ELF Note of
636 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
637 * parse the PVH entry address from the ELF Note.
638 *
639 * Due to trickery in elf_opts.h, load_elf() is actually available as
640 * load_elf32() or load_elf64() and this routine needs to be able
641 * to deal with being called as 32 or 64 bit.
642 *
643 * The address of the PVH entry point is saved to the 'pvh_start_addr'
644 * global variable. (although the entry point is 32-bit, the kernel
645 * binary can be either 32-bit or 64-bit).
646 */
647 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
648 {
649 size_t *elf_note_data_addr;
650
651 /* Check if ELF Note header passed in is valid */
652 if (arg1 == NULL) {
653 return 0;
654 }
655
656 if (is64) {
657 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
658 uint64_t nhdr_size64 = sizeof(struct elf64_note);
659 uint64_t phdr_align = *(uint64_t *)arg2;
660 uint64_t nhdr_namesz = nhdr64->n_namesz;
661
662 elf_note_data_addr =
663 ((void *)nhdr64) + nhdr_size64 +
664 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
665 } else {
666 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
667 uint32_t nhdr_size32 = sizeof(struct elf32_note);
668 uint32_t phdr_align = *(uint32_t *)arg2;
669 uint32_t nhdr_namesz = nhdr32->n_namesz;
670
671 elf_note_data_addr =
672 ((void *)nhdr32) + nhdr_size32 +
673 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
674 }
675
676 pvh_start_addr = *elf_note_data_addr;
677
678 return pvh_start_addr;
679 }
680
681 static bool load_elfboot(const char *kernel_filename,
682 int kernel_file_size,
683 uint8_t *header,
684 size_t pvh_xen_start_addr,
685 FWCfgState *fw_cfg)
686 {
687 uint32_t flags = 0;
688 uint32_t mh_load_addr = 0;
689 uint32_t elf_kernel_size = 0;
690 uint64_t elf_entry;
691 uint64_t elf_low, elf_high;
692 int kernel_size;
693
694 if (ldl_p(header) != 0x464c457f) {
695 return false; /* no elfboot */
696 }
697
698 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
699 flags = elf_is64 ?
700 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
701
702 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
703 error_report("elfboot unsupported flags = %x", flags);
704 exit(1);
705 }
706
707 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
708 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
709 NULL, &elf_note_type, &elf_entry,
710 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE,
711 0, 0);
712
713 if (kernel_size < 0) {
714 error_report("Error while loading elf kernel");
715 exit(1);
716 }
717 mh_load_addr = elf_low;
718 elf_kernel_size = elf_high - elf_low;
719
720 if (pvh_start_addr == 0) {
721 error_report("Error loading uncompressed kernel without PVH ELF Note");
722 exit(1);
723 }
724 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
725 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
726 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
727
728 return true;
729 }
730
731 void x86_load_linux(X86MachineState *x86ms,
732 FWCfgState *fw_cfg,
733 int acpi_data_size,
734 bool pvh_enabled,
735 bool linuxboot_dma_enabled)
736 {
737 uint16_t protocol;
738 int setup_size, kernel_size, cmdline_size;
739 int dtb_size, setup_data_offset;
740 uint32_t initrd_max;
741 uint8_t header[8192], *setup, *kernel;
742 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
743 FILE *f;
744 char *vmode;
745 MachineState *machine = MACHINE(x86ms);
746 struct setup_data *setup_data;
747 const char *kernel_filename = machine->kernel_filename;
748 const char *initrd_filename = machine->initrd_filename;
749 const char *dtb_filename = machine->dtb;
750 const char *kernel_cmdline = machine->kernel_cmdline;
751
752 /* Align to 16 bytes as a paranoia measure */
753 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
754
755 /* load the kernel header */
756 f = fopen(kernel_filename, "rb");
757 if (!f) {
758 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
759 kernel_filename, strerror(errno));
760 exit(1);
761 }
762
763 kernel_size = get_file_size(f);
764 if (!kernel_size ||
765 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
766 MIN(ARRAY_SIZE(header), kernel_size)) {
767 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
768 kernel_filename, strerror(errno));
769 exit(1);
770 }
771
772 /* kernel protocol version */
773 if (ldl_p(header + 0x202) == 0x53726448) {
774 protocol = lduw_p(header + 0x206);
775 } else {
776 /*
777 * This could be a multiboot kernel. If it is, let's stop treating it
778 * like a Linux kernel.
779 * Note: some multiboot images could be in the ELF format (the same of
780 * PVH), so we try multiboot first since we check the multiboot magic
781 * header before to load it.
782 */
783 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
784 kernel_cmdline, kernel_size, header)) {
785 return;
786 }
787 /*
788 * Check if the file is an uncompressed kernel file (ELF) and load it,
789 * saving the PVH entry point used by the x86/HVM direct boot ABI.
790 * If load_elfboot() is successful, populate the fw_cfg info.
791 */
792 if (pvh_enabled &&
793 load_elfboot(kernel_filename, kernel_size,
794 header, pvh_start_addr, fw_cfg)) {
795 fclose(f);
796
797 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
798 strlen(kernel_cmdline) + 1);
799 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
800
801 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
802 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
803 header, sizeof(header));
804
805 /* load initrd */
806 if (initrd_filename) {
807 GMappedFile *mapped_file;
808 gsize initrd_size;
809 gchar *initrd_data;
810 GError *gerr = NULL;
811
812 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
813 if (!mapped_file) {
814 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
815 initrd_filename, gerr->message);
816 exit(1);
817 }
818 x86ms->initrd_mapped_file = mapped_file;
819
820 initrd_data = g_mapped_file_get_contents(mapped_file);
821 initrd_size = g_mapped_file_get_length(mapped_file);
822 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
823 if (initrd_size >= initrd_max) {
824 fprintf(stderr, "qemu: initrd is too large, cannot support."
825 "(max: %"PRIu32", need %"PRId64")\n",
826 initrd_max, (uint64_t)initrd_size);
827 exit(1);
828 }
829
830 initrd_addr = (initrd_max - initrd_size) & ~4095;
831
832 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
833 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
834 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
835 initrd_size);
836 }
837
838 option_rom[nb_option_roms].bootindex = 0;
839 option_rom[nb_option_roms].name = "pvh.bin";
840 nb_option_roms++;
841
842 return;
843 }
844 protocol = 0;
845 }
846
847 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
848 /* Low kernel */
849 real_addr = 0x90000;
850 cmdline_addr = 0x9a000 - cmdline_size;
851 prot_addr = 0x10000;
852 } else if (protocol < 0x202) {
853 /* High but ancient kernel */
854 real_addr = 0x90000;
855 cmdline_addr = 0x9a000 - cmdline_size;
856 prot_addr = 0x100000;
857 } else {
858 /* High and recent kernel */
859 real_addr = 0x10000;
860 cmdline_addr = 0x20000;
861 prot_addr = 0x100000;
862 }
863
864 /* highest address for loading the initrd */
865 if (protocol >= 0x20c &&
866 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
867 /*
868 * Linux has supported initrd up to 4 GB for a very long time (2007,
869 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
870 * though it only sets initrd_max to 2 GB to "work around bootloader
871 * bugs". Luckily, QEMU firmware(which does something like bootloader)
872 * has supported this.
873 *
874 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
875 * be loaded into any address.
876 *
877 * In addition, initrd_max is uint32_t simply because QEMU doesn't
878 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
879 * field).
880 *
881 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
882 */
883 initrd_max = UINT32_MAX;
884 } else if (protocol >= 0x203) {
885 initrd_max = ldl_p(header + 0x22c);
886 } else {
887 initrd_max = 0x37ffffff;
888 }
889
890 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) {
891 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
892 }
893
894 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
895 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
896 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
897
898 if (protocol >= 0x202) {
899 stl_p(header + 0x228, cmdline_addr);
900 } else {
901 stw_p(header + 0x20, 0xA33F);
902 stw_p(header + 0x22, cmdline_addr - real_addr);
903 }
904
905 /* handle vga= parameter */
906 vmode = strstr(kernel_cmdline, "vga=");
907 if (vmode) {
908 unsigned int video_mode;
909 const char *end;
910 int ret;
911 /* skip "vga=" */
912 vmode += 4;
913 if (!strncmp(vmode, "normal", 6)) {
914 video_mode = 0xffff;
915 } else if (!strncmp(vmode, "ext", 3)) {
916 video_mode = 0xfffe;
917 } else if (!strncmp(vmode, "ask", 3)) {
918 video_mode = 0xfffd;
919 } else {
920 ret = qemu_strtoui(vmode, &end, 0, &video_mode);
921 if (ret != 0 || (*end && *end != ' ')) {
922 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n");
923 exit(1);
924 }
925 }
926 stw_p(header + 0x1fa, video_mode);
927 }
928
929 /* loader type */
930 /*
931 * High nybble = B reserved for QEMU; low nybble is revision number.
932 * If this code is substantially changed, you may want to consider
933 * incrementing the revision.
934 */
935 if (protocol >= 0x200) {
936 header[0x210] = 0xB0;
937 }
938 /* heap */
939 if (protocol >= 0x201) {
940 header[0x211] |= 0x80; /* CAN_USE_HEAP */
941 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
942 }
943
944 /* load initrd */
945 if (initrd_filename) {
946 GMappedFile *mapped_file;
947 gsize initrd_size;
948 gchar *initrd_data;
949 GError *gerr = NULL;
950
951 if (protocol < 0x200) {
952 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
953 exit(1);
954 }
955
956 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
957 if (!mapped_file) {
958 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
959 initrd_filename, gerr->message);
960 exit(1);
961 }
962 x86ms->initrd_mapped_file = mapped_file;
963
964 initrd_data = g_mapped_file_get_contents(mapped_file);
965 initrd_size = g_mapped_file_get_length(mapped_file);
966 if (initrd_size >= initrd_max) {
967 fprintf(stderr, "qemu: initrd is too large, cannot support."
968 "(max: %"PRIu32", need %"PRId64")\n",
969 initrd_max, (uint64_t)initrd_size);
970 exit(1);
971 }
972
973 initrd_addr = (initrd_max - initrd_size) & ~4095;
974
975 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
976 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
977 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
978
979 stl_p(header + 0x218, initrd_addr);
980 stl_p(header + 0x21c, initrd_size);
981 }
982
983 /* load kernel and setup */
984 setup_size = header[0x1f1];
985 if (setup_size == 0) {
986 setup_size = 4;
987 }
988 setup_size = (setup_size + 1) * 512;
989 if (setup_size > kernel_size) {
990 fprintf(stderr, "qemu: invalid kernel header\n");
991 exit(1);
992 }
993 kernel_size -= setup_size;
994
995 setup = g_malloc(setup_size);
996 kernel = g_malloc(kernel_size);
997 fseek(f, 0, SEEK_SET);
998 if (fread(setup, 1, setup_size, f) != setup_size) {
999 fprintf(stderr, "fread() failed\n");
1000 exit(1);
1001 }
1002 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1003 fprintf(stderr, "fread() failed\n");
1004 exit(1);
1005 }
1006 fclose(f);
1007
1008 /* append dtb to kernel */
1009 if (dtb_filename) {
1010 if (protocol < 0x209) {
1011 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1012 exit(1);
1013 }
1014
1015 dtb_size = get_image_size(dtb_filename);
1016 if (dtb_size <= 0) {
1017 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1018 dtb_filename, strerror(errno));
1019 exit(1);
1020 }
1021
1022 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1023 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1024 kernel = g_realloc(kernel, kernel_size);
1025
1026 stq_p(header + 0x250, prot_addr + setup_data_offset);
1027
1028 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1029 setup_data->next = 0;
1030 setup_data->type = cpu_to_le32(SETUP_DTB);
1031 setup_data->len = cpu_to_le32(dtb_size);
1032
1033 load_image_size(dtb_filename, setup_data->data, dtb_size);
1034 }
1035
1036 memcpy(setup, header, MIN(sizeof(header), setup_size));
1037
1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1040 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1041
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1043 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1044 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1045
1046 option_rom[nb_option_roms].bootindex = 0;
1047 option_rom[nb_option_roms].name = "linuxboot.bin";
1048 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1049 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1050 }
1051 nb_option_roms++;
1052 }
1053
1054 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
1055 {
1056 char *filename;
1057 MemoryRegion *bios, *isa_bios;
1058 int bios_size, isa_bios_size;
1059 int ret;
1060
1061 /* BIOS load */
1062 if (bios_name == NULL) {
1063 bios_name = BIOS_FILENAME;
1064 }
1065 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1066 if (filename) {
1067 bios_size = get_image_size(filename);
1068 } else {
1069 bios_size = -1;
1070 }
1071 if (bios_size <= 0 ||
1072 (bios_size % 65536) != 0) {
1073 goto bios_error;
1074 }
1075 bios = g_malloc(sizeof(*bios));
1076 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal);
1077 if (!isapc_ram_fw) {
1078 memory_region_set_readonly(bios, true);
1079 }
1080 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1081 if (ret != 0) {
1082 bios_error:
1083 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1084 exit(1);
1085 }
1086 g_free(filename);
1087
1088 /* map the last 128KB of the BIOS in ISA space */
1089 isa_bios_size = MIN(bios_size, 128 * KiB);
1090 isa_bios = g_malloc(sizeof(*isa_bios));
1091 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
1092 bios_size - isa_bios_size, isa_bios_size);
1093 memory_region_add_subregion_overlap(rom_memory,
1094 0x100000 - isa_bios_size,
1095 isa_bios,
1096 1);
1097 if (!isapc_ram_fw) {
1098 memory_region_set_readonly(isa_bios, true);
1099 }
1100
1101 /* map all the bios at the top of memory */
1102 memory_region_add_subregion(rom_memory,
1103 (uint32_t)(-bios_size),
1104 bios);
1105 }
1106
1107 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms)
1108 {
1109 bool smm_available = false;
1110
1111 if (x86ms->smm == ON_OFF_AUTO_OFF) {
1112 return false;
1113 }
1114
1115 if (tcg_enabled() || qtest_enabled()) {
1116 smm_available = true;
1117 } else if (kvm_enabled()) {
1118 smm_available = kvm_has_smm();
1119 }
1120
1121 if (smm_available) {
1122 return true;
1123 }
1124
1125 if (x86ms->smm == ON_OFF_AUTO_ON) {
1126 error_report("System Management Mode not supported by this hypervisor.");
1127 exit(1);
1128 }
1129 return false;
1130 }
1131
1132 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name,
1133 void *opaque, Error **errp)
1134 {
1135 X86MachineState *x86ms = X86_MACHINE(obj);
1136 OnOffAuto smm = x86ms->smm;
1137
1138 visit_type_OnOffAuto(v, name, &smm, errp);
1139 }
1140
1141 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name,
1142 void *opaque, Error **errp)
1143 {
1144 X86MachineState *x86ms = X86_MACHINE(obj);
1145
1146 visit_type_OnOffAuto(v, name, &x86ms->smm, errp);
1147 }
1148
1149 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms)
1150 {
1151 if (x86ms->acpi == ON_OFF_AUTO_OFF) {
1152 return false;
1153 }
1154 return true;
1155 }
1156
1157 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name,
1158 void *opaque, Error **errp)
1159 {
1160 X86MachineState *x86ms = X86_MACHINE(obj);
1161 OnOffAuto acpi = x86ms->acpi;
1162
1163 visit_type_OnOffAuto(v, name, &acpi, errp);
1164 }
1165
1166 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name,
1167 void *opaque, Error **errp)
1168 {
1169 X86MachineState *x86ms = X86_MACHINE(obj);
1170
1171 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp);
1172 }
1173
1174 static void x86_machine_initfn(Object *obj)
1175 {
1176 X86MachineState *x86ms = X86_MACHINE(obj);
1177
1178 x86ms->smm = ON_OFF_AUTO_AUTO;
1179 x86ms->acpi = ON_OFF_AUTO_AUTO;
1180 x86ms->smp_dies = 1;
1181 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS;
1182 }
1183
1184 static void x86_machine_class_init(ObjectClass *oc, void *data)
1185 {
1186 MachineClass *mc = MACHINE_CLASS(oc);
1187 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1188 NMIClass *nc = NMI_CLASS(oc);
1189
1190 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1191 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1192 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1193 x86mc->compat_apic_id_mode = false;
1194 x86mc->save_tsc_khz = true;
1195 nc->nmi_monitor_handler = x86_nmi;
1196
1197 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto",
1198 x86_machine_get_smm, x86_machine_set_smm,
1199 NULL, NULL);
1200 object_class_property_set_description(oc, X86_MACHINE_SMM,
1201 "Enable SMM");
1202
1203 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto",
1204 x86_machine_get_acpi, x86_machine_set_acpi,
1205 NULL, NULL);
1206 object_class_property_set_description(oc, X86_MACHINE_ACPI,
1207 "Enable ACPI");
1208 }
1209
1210 static const TypeInfo x86_machine_info = {
1211 .name = TYPE_X86_MACHINE,
1212 .parent = TYPE_MACHINE,
1213 .abstract = true,
1214 .instance_size = sizeof(X86MachineState),
1215 .instance_init = x86_machine_initfn,
1216 .class_size = sizeof(X86MachineClass),
1217 .class_init = x86_machine_class_init,
1218 .interfaces = (InterfaceInfo[]) {
1219 { TYPE_NMI },
1220 { }
1221 },
1222 };
1223
1224 static void x86_machine_register_types(void)
1225 {
1226 type_register_static(&x86_machine_info);
1227 }
1228
1229 type_init(x86_machine_register_types)