trace: switch position of headers to what Meson requires
[qemu.git] / hw / i386 / x86.c
1 /*
2 * Copyright (c) 2003-2004 Fabrice Bellard
3 * Copyright (c) 2019 Red Hat, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 */
23 #include "qemu/osdep.h"
24 #include "qemu/error-report.h"
25 #include "qemu/option.h"
26 #include "qemu/cutils.h"
27 #include "qemu/units.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/qmp/qerror.h"
31 #include "qapi/qapi-visit-common.h"
32 #include "qapi/visitor.h"
33 #include "sysemu/qtest.h"
34 #include "sysemu/numa.h"
35 #include "sysemu/replay.h"
36 #include "sysemu/sysemu.h"
37 #include "trace.h"
38
39 #include "hw/i386/x86.h"
40 #include "target/i386/cpu.h"
41 #include "hw/i386/topology.h"
42 #include "hw/i386/fw_cfg.h"
43 #include "hw/intc/i8259.h"
44
45 #include "hw/acpi/cpu_hotplug.h"
46 #include "hw/irq.h"
47 #include "hw/nmi.h"
48 #include "hw/loader.h"
49 #include "multiboot.h"
50 #include "elf.h"
51 #include "standard-headers/asm-x86/bootparam.h"
52 #include "config-devices.h"
53 #include "kvm_i386.h"
54
55 #define BIOS_FILENAME "bios.bin"
56
57 /* Physical Address of PVH entry point read from kernel ELF NOTE */
58 static size_t pvh_start_addr;
59
60 inline void init_topo_info(X86CPUTopoInfo *topo_info,
61 const X86MachineState *x86ms)
62 {
63 MachineState *ms = MACHINE(x86ms);
64
65 topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
66 topo_info->dies_per_pkg = x86ms->smp_dies;
67 topo_info->cores_per_die = ms->smp.cores;
68 topo_info->threads_per_core = ms->smp.threads;
69 }
70
71 /*
72 * Set up with the new EPYC topology handlers
73 *
74 * AMD uses different apic id encoding for EPYC based cpus. Override
75 * the default topo handlers with EPYC encoding handlers.
76 */
77 static void x86_set_epyc_topo_handlers(MachineState *machine)
78 {
79 X86MachineState *x86ms = X86_MACHINE(machine);
80
81 x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc;
82 x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc;
83 x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc;
84 x86ms->apicid_pkg_offset = apicid_pkg_offset_epyc;
85 }
86
87 /*
88 * Calculates initial APIC ID for a specific CPU index
89 *
90 * Currently we need to be able to calculate the APIC ID from the CPU index
91 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
92 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
93 * all CPUs up to max_cpus.
94 */
95 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
96 unsigned int cpu_index)
97 {
98 X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
99 X86CPUTopoInfo topo_info;
100 uint32_t correct_id;
101 static bool warned;
102
103 init_topo_info(&topo_info, x86ms);
104
105 correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index);
106 if (x86mc->compat_apic_id_mode) {
107 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
108 error_report("APIC IDs set in compatibility mode, "
109 "CPU topology won't match the configuration");
110 warned = true;
111 }
112 return cpu_index;
113 } else {
114 return correct_id;
115 }
116 }
117
118
119 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
120 {
121 Object *cpu = object_new(MACHINE(x86ms)->cpu_type);
122
123 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) {
124 goto out;
125 }
126 qdev_realize(DEVICE(cpu), NULL, errp);
127
128 out:
129 object_unref(cpu);
130 }
131
132 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
133 {
134 int i;
135 const CPUArchIdList *possible_cpus;
136 MachineState *ms = MACHINE(x86ms);
137 MachineClass *mc = MACHINE_GET_CLASS(x86ms);
138
139 /* Check for apicid encoding */
140 if (cpu_x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
141 x86_set_epyc_topo_handlers(ms);
142 }
143
144 x86_cpu_set_default_version(default_cpu_version);
145
146 /*
147 * Calculates the limit to CPU APIC ID values
148 *
149 * Limit for the APIC ID value, so that all
150 * CPU APIC IDs are < x86ms->apic_id_limit.
151 *
152 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
153 */
154 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
155 ms->smp.max_cpus - 1) + 1;
156 possible_cpus = mc->possible_cpu_arch_ids(ms);
157
158 for (i = 0; i < ms->possible_cpus->len; i++) {
159 ms->possible_cpus->cpus[i].arch_id =
160 x86_cpu_apic_id_from_index(x86ms, i);
161 }
162
163 for (i = 0; i < ms->smp.cpus; i++) {
164 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
165 }
166 }
167
168 CpuInstanceProperties
169 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
170 {
171 MachineClass *mc = MACHINE_GET_CLASS(ms);
172 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
173
174 assert(cpu_index < possible_cpus->len);
175 return possible_cpus->cpus[cpu_index].props;
176 }
177
178 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
179 {
180 X86CPUTopoIDs topo_ids;
181 X86MachineState *x86ms = X86_MACHINE(ms);
182 X86CPUTopoInfo topo_info;
183
184 init_topo_info(&topo_info, x86ms);
185
186 assert(idx < ms->possible_cpus->len);
187 x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
188 return topo_ids.pkg_id % ms->numa_state->num_nodes;
189 }
190
191 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
192 {
193 X86MachineState *x86ms = X86_MACHINE(ms);
194 unsigned int max_cpus = ms->smp.max_cpus;
195 X86CPUTopoInfo topo_info;
196 int i;
197
198 if (ms->possible_cpus) {
199 /*
200 * make sure that max_cpus hasn't changed since the first use, i.e.
201 * -smp hasn't been parsed after it
202 */
203 assert(ms->possible_cpus->len == max_cpus);
204 return ms->possible_cpus;
205 }
206
207 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
208 sizeof(CPUArchId) * max_cpus);
209 ms->possible_cpus->len = max_cpus;
210
211 init_topo_info(&topo_info, x86ms);
212
213 for (i = 0; i < ms->possible_cpus->len; i++) {
214 X86CPUTopoIDs topo_ids;
215
216 ms->possible_cpus->cpus[i].type = ms->cpu_type;
217 ms->possible_cpus->cpus[i].vcpus_count = 1;
218 x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
219 ms->possible_cpus->cpus[i].props.has_socket_id = true;
220 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
221 if (x86ms->smp_dies > 1) {
222 ms->possible_cpus->cpus[i].props.has_die_id = true;
223 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
224 }
225 ms->possible_cpus->cpus[i].props.has_core_id = true;
226 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
227 ms->possible_cpus->cpus[i].props.has_thread_id = true;
228 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id;
229 }
230 return ms->possible_cpus;
231 }
232
233 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
234 {
235 /* cpu index isn't used */
236 CPUState *cs;
237
238 CPU_FOREACH(cs) {
239 X86CPU *cpu = X86_CPU(cs);
240
241 if (!cpu->apic_state) {
242 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
243 } else {
244 apic_deliver_nmi(cpu->apic_state);
245 }
246 }
247 }
248
249 static long get_file_size(FILE *f)
250 {
251 long where, size;
252
253 /* XXX: on Unix systems, using fstat() probably makes more sense */
254
255 where = ftell(f);
256 fseek(f, 0, SEEK_END);
257 size = ftell(f);
258 fseek(f, where, SEEK_SET);
259
260 return size;
261 }
262
263 /* TSC handling */
264 uint64_t cpu_get_tsc(CPUX86State *env)
265 {
266 return cpu_get_ticks();
267 }
268
269 /* IRQ handling */
270 static void pic_irq_request(void *opaque, int irq, int level)
271 {
272 CPUState *cs = first_cpu;
273 X86CPU *cpu = X86_CPU(cs);
274
275 trace_x86_pic_interrupt(irq, level);
276 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
277 CPU_FOREACH(cs) {
278 cpu = X86_CPU(cs);
279 if (apic_accept_pic_intr(cpu->apic_state)) {
280 apic_deliver_pic_intr(cpu->apic_state, level);
281 }
282 }
283 } else {
284 if (level) {
285 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
286 } else {
287 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
288 }
289 }
290 }
291
292 qemu_irq x86_allocate_cpu_irq(void)
293 {
294 return qemu_allocate_irq(pic_irq_request, NULL, 0);
295 }
296
297 int cpu_get_pic_interrupt(CPUX86State *env)
298 {
299 X86CPU *cpu = env_archcpu(env);
300 int intno;
301
302 if (!kvm_irqchip_in_kernel()) {
303 intno = apic_get_interrupt(cpu->apic_state);
304 if (intno >= 0) {
305 return intno;
306 }
307 /* read the irq from the PIC */
308 if (!apic_accept_pic_intr(cpu->apic_state)) {
309 return -1;
310 }
311 }
312
313 intno = pic_read_irq(isa_pic);
314 return intno;
315 }
316
317 DeviceState *cpu_get_current_apic(void)
318 {
319 if (current_cpu) {
320 X86CPU *cpu = X86_CPU(current_cpu);
321 return cpu->apic_state;
322 } else {
323 return NULL;
324 }
325 }
326
327 void gsi_handler(void *opaque, int n, int level)
328 {
329 GSIState *s = opaque;
330
331 trace_x86_gsi_interrupt(n, level);
332 if (n < ISA_NUM_IRQS) {
333 /* Under KVM, Kernel will forward to both PIC and IOAPIC */
334 qemu_set_irq(s->i8259_irq[n], level);
335 }
336 qemu_set_irq(s->ioapic_irq[n], level);
337 }
338
339 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
340 {
341 DeviceState *dev;
342 SysBusDevice *d;
343 unsigned int i;
344
345 assert(parent_name);
346 if (kvm_ioapic_in_kernel()) {
347 dev = qdev_new(TYPE_KVM_IOAPIC);
348 } else {
349 dev = qdev_new(TYPE_IOAPIC);
350 }
351 object_property_add_child(object_resolve_path(parent_name, NULL),
352 "ioapic", OBJECT(dev));
353 d = SYS_BUS_DEVICE(dev);
354 sysbus_realize_and_unref(d, &error_fatal);
355 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
356
357 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
358 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
359 }
360 }
361
362 struct setup_data {
363 uint64_t next;
364 uint32_t type;
365 uint32_t len;
366 uint8_t data[];
367 } __attribute__((packed));
368
369
370 /*
371 * The entry point into the kernel for PVH boot is different from
372 * the native entry point. The PVH entry is defined by the x86/HVM
373 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
374 *
375 * This function is passed to load_elf() when it is called from
376 * load_elfboot() which then additionally checks for an ELF Note of
377 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
378 * parse the PVH entry address from the ELF Note.
379 *
380 * Due to trickery in elf_opts.h, load_elf() is actually available as
381 * load_elf32() or load_elf64() and this routine needs to be able
382 * to deal with being called as 32 or 64 bit.
383 *
384 * The address of the PVH entry point is saved to the 'pvh_start_addr'
385 * global variable. (although the entry point is 32-bit, the kernel
386 * binary can be either 32-bit or 64-bit).
387 */
388 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
389 {
390 size_t *elf_note_data_addr;
391
392 /* Check if ELF Note header passed in is valid */
393 if (arg1 == NULL) {
394 return 0;
395 }
396
397 if (is64) {
398 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
399 uint64_t nhdr_size64 = sizeof(struct elf64_note);
400 uint64_t phdr_align = *(uint64_t *)arg2;
401 uint64_t nhdr_namesz = nhdr64->n_namesz;
402
403 elf_note_data_addr =
404 ((void *)nhdr64) + nhdr_size64 +
405 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
406 } else {
407 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
408 uint32_t nhdr_size32 = sizeof(struct elf32_note);
409 uint32_t phdr_align = *(uint32_t *)arg2;
410 uint32_t nhdr_namesz = nhdr32->n_namesz;
411
412 elf_note_data_addr =
413 ((void *)nhdr32) + nhdr_size32 +
414 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
415 }
416
417 pvh_start_addr = *elf_note_data_addr;
418
419 return pvh_start_addr;
420 }
421
422 static bool load_elfboot(const char *kernel_filename,
423 int kernel_file_size,
424 uint8_t *header,
425 size_t pvh_xen_start_addr,
426 FWCfgState *fw_cfg)
427 {
428 uint32_t flags = 0;
429 uint32_t mh_load_addr = 0;
430 uint32_t elf_kernel_size = 0;
431 uint64_t elf_entry;
432 uint64_t elf_low, elf_high;
433 int kernel_size;
434
435 if (ldl_p(header) != 0x464c457f) {
436 return false; /* no elfboot */
437 }
438
439 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
440 flags = elf_is64 ?
441 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
442
443 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
444 error_report("elfboot unsupported flags = %x", flags);
445 exit(1);
446 }
447
448 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
449 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
450 NULL, &elf_note_type, &elf_entry,
451 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE,
452 0, 0);
453
454 if (kernel_size < 0) {
455 error_report("Error while loading elf kernel");
456 exit(1);
457 }
458 mh_load_addr = elf_low;
459 elf_kernel_size = elf_high - elf_low;
460
461 if (pvh_start_addr == 0) {
462 error_report("Error loading uncompressed kernel without PVH ELF Note");
463 exit(1);
464 }
465 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
466 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
468
469 return true;
470 }
471
472 void x86_load_linux(X86MachineState *x86ms,
473 FWCfgState *fw_cfg,
474 int acpi_data_size,
475 bool pvh_enabled,
476 bool linuxboot_dma_enabled)
477 {
478 uint16_t protocol;
479 int setup_size, kernel_size, cmdline_size;
480 int dtb_size, setup_data_offset;
481 uint32_t initrd_max;
482 uint8_t header[8192], *setup, *kernel;
483 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
484 FILE *f;
485 char *vmode;
486 MachineState *machine = MACHINE(x86ms);
487 struct setup_data *setup_data;
488 const char *kernel_filename = machine->kernel_filename;
489 const char *initrd_filename = machine->initrd_filename;
490 const char *dtb_filename = machine->dtb;
491 const char *kernel_cmdline = machine->kernel_cmdline;
492
493 /* Align to 16 bytes as a paranoia measure */
494 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
495
496 /* load the kernel header */
497 f = fopen(kernel_filename, "rb");
498 if (!f) {
499 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
500 kernel_filename, strerror(errno));
501 exit(1);
502 }
503
504 kernel_size = get_file_size(f);
505 if (!kernel_size ||
506 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
507 MIN(ARRAY_SIZE(header), kernel_size)) {
508 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
509 kernel_filename, strerror(errno));
510 exit(1);
511 }
512
513 /* kernel protocol version */
514 if (ldl_p(header + 0x202) == 0x53726448) {
515 protocol = lduw_p(header + 0x206);
516 } else {
517 /*
518 * This could be a multiboot kernel. If it is, let's stop treating it
519 * like a Linux kernel.
520 * Note: some multiboot images could be in the ELF format (the same of
521 * PVH), so we try multiboot first since we check the multiboot magic
522 * header before to load it.
523 */
524 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
525 kernel_cmdline, kernel_size, header)) {
526 return;
527 }
528 /*
529 * Check if the file is an uncompressed kernel file (ELF) and load it,
530 * saving the PVH entry point used by the x86/HVM direct boot ABI.
531 * If load_elfboot() is successful, populate the fw_cfg info.
532 */
533 if (pvh_enabled &&
534 load_elfboot(kernel_filename, kernel_size,
535 header, pvh_start_addr, fw_cfg)) {
536 fclose(f);
537
538 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
539 strlen(kernel_cmdline) + 1);
540 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
541
542 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
543 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
544 header, sizeof(header));
545
546 /* load initrd */
547 if (initrd_filename) {
548 GMappedFile *mapped_file;
549 gsize initrd_size;
550 gchar *initrd_data;
551 GError *gerr = NULL;
552
553 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
554 if (!mapped_file) {
555 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
556 initrd_filename, gerr->message);
557 exit(1);
558 }
559 x86ms->initrd_mapped_file = mapped_file;
560
561 initrd_data = g_mapped_file_get_contents(mapped_file);
562 initrd_size = g_mapped_file_get_length(mapped_file);
563 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
564 if (initrd_size >= initrd_max) {
565 fprintf(stderr, "qemu: initrd is too large, cannot support."
566 "(max: %"PRIu32", need %"PRId64")\n",
567 initrd_max, (uint64_t)initrd_size);
568 exit(1);
569 }
570
571 initrd_addr = (initrd_max - initrd_size) & ~4095;
572
573 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
574 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
575 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
576 initrd_size);
577 }
578
579 option_rom[nb_option_roms].bootindex = 0;
580 option_rom[nb_option_roms].name = "pvh.bin";
581 nb_option_roms++;
582
583 return;
584 }
585 protocol = 0;
586 }
587
588 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
589 /* Low kernel */
590 real_addr = 0x90000;
591 cmdline_addr = 0x9a000 - cmdline_size;
592 prot_addr = 0x10000;
593 } else if (protocol < 0x202) {
594 /* High but ancient kernel */
595 real_addr = 0x90000;
596 cmdline_addr = 0x9a000 - cmdline_size;
597 prot_addr = 0x100000;
598 } else {
599 /* High and recent kernel */
600 real_addr = 0x10000;
601 cmdline_addr = 0x20000;
602 prot_addr = 0x100000;
603 }
604
605 /* highest address for loading the initrd */
606 if (protocol >= 0x20c &&
607 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
608 /*
609 * Linux has supported initrd up to 4 GB for a very long time (2007,
610 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
611 * though it only sets initrd_max to 2 GB to "work around bootloader
612 * bugs". Luckily, QEMU firmware(which does something like bootloader)
613 * has supported this.
614 *
615 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
616 * be loaded into any address.
617 *
618 * In addition, initrd_max is uint32_t simply because QEMU doesn't
619 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
620 * field).
621 *
622 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
623 */
624 initrd_max = UINT32_MAX;
625 } else if (protocol >= 0x203) {
626 initrd_max = ldl_p(header + 0x22c);
627 } else {
628 initrd_max = 0x37ffffff;
629 }
630
631 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) {
632 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
633 }
634
635 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
636 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
637 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
638
639 if (protocol >= 0x202) {
640 stl_p(header + 0x228, cmdline_addr);
641 } else {
642 stw_p(header + 0x20, 0xA33F);
643 stw_p(header + 0x22, cmdline_addr - real_addr);
644 }
645
646 /* handle vga= parameter */
647 vmode = strstr(kernel_cmdline, "vga=");
648 if (vmode) {
649 unsigned int video_mode;
650 const char *end;
651 int ret;
652 /* skip "vga=" */
653 vmode += 4;
654 if (!strncmp(vmode, "normal", 6)) {
655 video_mode = 0xffff;
656 } else if (!strncmp(vmode, "ext", 3)) {
657 video_mode = 0xfffe;
658 } else if (!strncmp(vmode, "ask", 3)) {
659 video_mode = 0xfffd;
660 } else {
661 ret = qemu_strtoui(vmode, &end, 0, &video_mode);
662 if (ret != 0 || (*end && *end != ' ')) {
663 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n");
664 exit(1);
665 }
666 }
667 stw_p(header + 0x1fa, video_mode);
668 }
669
670 /* loader type */
671 /*
672 * High nybble = B reserved for QEMU; low nybble is revision number.
673 * If this code is substantially changed, you may want to consider
674 * incrementing the revision.
675 */
676 if (protocol >= 0x200) {
677 header[0x210] = 0xB0;
678 }
679 /* heap */
680 if (protocol >= 0x201) {
681 header[0x211] |= 0x80; /* CAN_USE_HEAP */
682 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
683 }
684
685 /* load initrd */
686 if (initrd_filename) {
687 GMappedFile *mapped_file;
688 gsize initrd_size;
689 gchar *initrd_data;
690 GError *gerr = NULL;
691
692 if (protocol < 0x200) {
693 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
694 exit(1);
695 }
696
697 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
698 if (!mapped_file) {
699 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
700 initrd_filename, gerr->message);
701 exit(1);
702 }
703 x86ms->initrd_mapped_file = mapped_file;
704
705 initrd_data = g_mapped_file_get_contents(mapped_file);
706 initrd_size = g_mapped_file_get_length(mapped_file);
707 if (initrd_size >= initrd_max) {
708 fprintf(stderr, "qemu: initrd is too large, cannot support."
709 "(max: %"PRIu32", need %"PRId64")\n",
710 initrd_max, (uint64_t)initrd_size);
711 exit(1);
712 }
713
714 initrd_addr = (initrd_max - initrd_size) & ~4095;
715
716 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
717 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
718 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
719
720 stl_p(header + 0x218, initrd_addr);
721 stl_p(header + 0x21c, initrd_size);
722 }
723
724 /* load kernel and setup */
725 setup_size = header[0x1f1];
726 if (setup_size == 0) {
727 setup_size = 4;
728 }
729 setup_size = (setup_size + 1) * 512;
730 if (setup_size > kernel_size) {
731 fprintf(stderr, "qemu: invalid kernel header\n");
732 exit(1);
733 }
734 kernel_size -= setup_size;
735
736 setup = g_malloc(setup_size);
737 kernel = g_malloc(kernel_size);
738 fseek(f, 0, SEEK_SET);
739 if (fread(setup, 1, setup_size, f) != setup_size) {
740 fprintf(stderr, "fread() failed\n");
741 exit(1);
742 }
743 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
744 fprintf(stderr, "fread() failed\n");
745 exit(1);
746 }
747 fclose(f);
748
749 /* append dtb to kernel */
750 if (dtb_filename) {
751 if (protocol < 0x209) {
752 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
753 exit(1);
754 }
755
756 dtb_size = get_image_size(dtb_filename);
757 if (dtb_size <= 0) {
758 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
759 dtb_filename, strerror(errno));
760 exit(1);
761 }
762
763 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
764 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
765 kernel = g_realloc(kernel, kernel_size);
766
767 stq_p(header + 0x250, prot_addr + setup_data_offset);
768
769 setup_data = (struct setup_data *)(kernel + setup_data_offset);
770 setup_data->next = 0;
771 setup_data->type = cpu_to_le32(SETUP_DTB);
772 setup_data->len = cpu_to_le32(dtb_size);
773
774 load_image_size(dtb_filename, setup_data->data, dtb_size);
775 }
776
777 memcpy(setup, header, MIN(sizeof(header), setup_size));
778
779 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
781 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
782
783 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
784 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
785 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
786
787 option_rom[nb_option_roms].bootindex = 0;
788 option_rom[nb_option_roms].name = "linuxboot.bin";
789 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
790 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
791 }
792 nb_option_roms++;
793 }
794
795 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
796 {
797 char *filename;
798 MemoryRegion *bios, *isa_bios;
799 int bios_size, isa_bios_size;
800 int ret;
801
802 /* BIOS load */
803 if (bios_name == NULL) {
804 bios_name = BIOS_FILENAME;
805 }
806 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
807 if (filename) {
808 bios_size = get_image_size(filename);
809 } else {
810 bios_size = -1;
811 }
812 if (bios_size <= 0 ||
813 (bios_size % 65536) != 0) {
814 goto bios_error;
815 }
816 bios = g_malloc(sizeof(*bios));
817 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal);
818 if (!isapc_ram_fw) {
819 memory_region_set_readonly(bios, true);
820 }
821 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
822 if (ret != 0) {
823 bios_error:
824 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
825 exit(1);
826 }
827 g_free(filename);
828
829 /* map the last 128KB of the BIOS in ISA space */
830 isa_bios_size = MIN(bios_size, 128 * KiB);
831 isa_bios = g_malloc(sizeof(*isa_bios));
832 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
833 bios_size - isa_bios_size, isa_bios_size);
834 memory_region_add_subregion_overlap(rom_memory,
835 0x100000 - isa_bios_size,
836 isa_bios,
837 1);
838 if (!isapc_ram_fw) {
839 memory_region_set_readonly(isa_bios, true);
840 }
841
842 /* map all the bios at the top of memory */
843 memory_region_add_subregion(rom_memory,
844 (uint32_t)(-bios_size),
845 bios);
846 }
847
848 bool x86_machine_is_smm_enabled(X86MachineState *x86ms)
849 {
850 bool smm_available = false;
851
852 if (x86ms->smm == ON_OFF_AUTO_OFF) {
853 return false;
854 }
855
856 if (tcg_enabled() || qtest_enabled()) {
857 smm_available = true;
858 } else if (kvm_enabled()) {
859 smm_available = kvm_has_smm();
860 }
861
862 if (smm_available) {
863 return true;
864 }
865
866 if (x86ms->smm == ON_OFF_AUTO_ON) {
867 error_report("System Management Mode not supported by this hypervisor.");
868 exit(1);
869 }
870 return false;
871 }
872
873 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name,
874 void *opaque, Error **errp)
875 {
876 X86MachineState *x86ms = X86_MACHINE(obj);
877 OnOffAuto smm = x86ms->smm;
878
879 visit_type_OnOffAuto(v, name, &smm, errp);
880 }
881
882 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name,
883 void *opaque, Error **errp)
884 {
885 X86MachineState *x86ms = X86_MACHINE(obj);
886
887 visit_type_OnOffAuto(v, name, &x86ms->smm, errp);
888 }
889
890 bool x86_machine_is_acpi_enabled(X86MachineState *x86ms)
891 {
892 if (x86ms->acpi == ON_OFF_AUTO_OFF) {
893 return false;
894 }
895 return true;
896 }
897
898 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name,
899 void *opaque, Error **errp)
900 {
901 X86MachineState *x86ms = X86_MACHINE(obj);
902 OnOffAuto acpi = x86ms->acpi;
903
904 visit_type_OnOffAuto(v, name, &acpi, errp);
905 }
906
907 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name,
908 void *opaque, Error **errp)
909 {
910 X86MachineState *x86ms = X86_MACHINE(obj);
911
912 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp);
913 }
914
915 static void x86_machine_initfn(Object *obj)
916 {
917 X86MachineState *x86ms = X86_MACHINE(obj);
918
919 x86ms->smm = ON_OFF_AUTO_AUTO;
920 x86ms->acpi = ON_OFF_AUTO_AUTO;
921 x86ms->smp_dies = 1;
922
923 x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
924 x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
925 x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
926 x86ms->apicid_pkg_offset = apicid_pkg_offset;
927 }
928
929 static void x86_machine_class_init(ObjectClass *oc, void *data)
930 {
931 MachineClass *mc = MACHINE_CLASS(oc);
932 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
933 NMIClass *nc = NMI_CLASS(oc);
934
935 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
936 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
937 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
938 x86mc->compat_apic_id_mode = false;
939 x86mc->save_tsc_khz = true;
940 nc->nmi_monitor_handler = x86_nmi;
941
942 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto",
943 x86_machine_get_smm, x86_machine_set_smm,
944 NULL, NULL);
945 object_class_property_set_description(oc, X86_MACHINE_SMM,
946 "Enable SMM");
947
948 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto",
949 x86_machine_get_acpi, x86_machine_set_acpi,
950 NULL, NULL);
951 object_class_property_set_description(oc, X86_MACHINE_ACPI,
952 "Enable ACPI");
953 }
954
955 static const TypeInfo x86_machine_info = {
956 .name = TYPE_X86_MACHINE,
957 .parent = TYPE_MACHINE,
958 .abstract = true,
959 .instance_size = sizeof(X86MachineState),
960 .instance_init = x86_machine_initfn,
961 .class_size = sizeof(X86MachineClass),
962 .class_init = x86_machine_class_init,
963 .interfaces = (InterfaceInfo[]) {
964 { TYPE_NMI },
965 { }
966 },
967 };
968
969 static void x86_machine_register_types(void)
970 {
971 type_register_static(&x86_machine_info);
972 }
973
974 type_init(x86_machine_register_types)