Revert "hw/i386: Introduce apicid functions inside X86MachineState"
[qemu.git] / hw / i386 / x86.c
1 /*
2 * Copyright (c) 2003-2004 Fabrice Bellard
3 * Copyright (c) 2019 Red Hat, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 */
23 #include "qemu/osdep.h"
24 #include "qemu/error-report.h"
25 #include "qemu/option.h"
26 #include "qemu/cutils.h"
27 #include "qemu/units.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/qmp/qerror.h"
31 #include "qapi/qapi-visit-common.h"
32 #include "qapi/visitor.h"
33 #include "sysemu/qtest.h"
34 #include "sysemu/numa.h"
35 #include "sysemu/replay.h"
36 #include "sysemu/sysemu.h"
37 #include "trace.h"
38
39 #include "hw/i386/x86.h"
40 #include "target/i386/cpu.h"
41 #include "hw/i386/topology.h"
42 #include "hw/i386/fw_cfg.h"
43 #include "hw/intc/i8259.h"
44
45 #include "hw/acpi/cpu_hotplug.h"
46 #include "hw/irq.h"
47 #include "hw/nmi.h"
48 #include "hw/loader.h"
49 #include "multiboot.h"
50 #include "elf.h"
51 #include "standard-headers/asm-x86/bootparam.h"
52 #include CONFIG_DEVICES
53 #include "kvm_i386.h"
54
55 #define BIOS_FILENAME "bios.bin"
56
57 /* Physical Address of PVH entry point read from kernel ELF NOTE */
58 static size_t pvh_start_addr;
59
60 inline void init_topo_info(X86CPUTopoInfo *topo_info,
61 const X86MachineState *x86ms)
62 {
63 MachineState *ms = MACHINE(x86ms);
64
65 topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
66 topo_info->dies_per_pkg = x86ms->smp_dies;
67 topo_info->cores_per_die = ms->smp.cores;
68 topo_info->threads_per_core = ms->smp.threads;
69 }
70
71 /*
72 * Calculates initial APIC ID for a specific CPU index
73 *
74 * Currently we need to be able to calculate the APIC ID from the CPU index
75 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
76 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
77 * all CPUs up to max_cpus.
78 */
79 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
80 unsigned int cpu_index)
81 {
82 X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
83 X86CPUTopoInfo topo_info;
84 uint32_t correct_id;
85 static bool warned;
86
87 init_topo_info(&topo_info, x86ms);
88
89 correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
90 if (x86mc->compat_apic_id_mode) {
91 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
92 error_report("APIC IDs set in compatibility mode, "
93 "CPU topology won't match the configuration");
94 warned = true;
95 }
96 return cpu_index;
97 } else {
98 return correct_id;
99 }
100 }
101
102
103 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
104 {
105 Object *cpu = object_new(MACHINE(x86ms)->cpu_type);
106
107 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) {
108 goto out;
109 }
110 qdev_realize(DEVICE(cpu), NULL, errp);
111
112 out:
113 object_unref(cpu);
114 }
115
116 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
117 {
118 int i;
119 const CPUArchIdList *possible_cpus;
120 MachineState *ms = MACHINE(x86ms);
121 MachineClass *mc = MACHINE_GET_CLASS(x86ms);
122
123 x86_cpu_set_default_version(default_cpu_version);
124
125 /*
126 * Calculates the limit to CPU APIC ID values
127 *
128 * Limit for the APIC ID value, so that all
129 * CPU APIC IDs are < x86ms->apic_id_limit.
130 *
131 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
132 */
133 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
134 ms->smp.max_cpus - 1) + 1;
135 possible_cpus = mc->possible_cpu_arch_ids(ms);
136 for (i = 0; i < ms->smp.cpus; i++) {
137 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
138 }
139 }
140
141 CpuInstanceProperties
142 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
143 {
144 MachineClass *mc = MACHINE_GET_CLASS(ms);
145 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
146
147 assert(cpu_index < possible_cpus->len);
148 return possible_cpus->cpus[cpu_index].props;
149 }
150
151 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
152 {
153 X86CPUTopoIDs topo_ids;
154 X86MachineState *x86ms = X86_MACHINE(ms);
155 X86CPUTopoInfo topo_info;
156
157 init_topo_info(&topo_info, x86ms);
158
159 assert(idx < ms->possible_cpus->len);
160 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
161 &topo_info, &topo_ids);
162 return topo_ids.pkg_id % ms->numa_state->num_nodes;
163 }
164
165 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
166 {
167 X86MachineState *x86ms = X86_MACHINE(ms);
168 unsigned int max_cpus = ms->smp.max_cpus;
169 X86CPUTopoInfo topo_info;
170 int i;
171
172 if (ms->possible_cpus) {
173 /*
174 * make sure that max_cpus hasn't changed since the first use, i.e.
175 * -smp hasn't been parsed after it
176 */
177 assert(ms->possible_cpus->len == max_cpus);
178 return ms->possible_cpus;
179 }
180
181 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
182 sizeof(CPUArchId) * max_cpus);
183 ms->possible_cpus->len = max_cpus;
184
185 init_topo_info(&topo_info, x86ms);
186
187 for (i = 0; i < ms->possible_cpus->len; i++) {
188 X86CPUTopoIDs topo_ids;
189
190 ms->possible_cpus->cpus[i].type = ms->cpu_type;
191 ms->possible_cpus->cpus[i].vcpus_count = 1;
192 ms->possible_cpus->cpus[i].arch_id =
193 x86_cpu_apic_id_from_index(x86ms, i);
194 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
195 &topo_info, &topo_ids);
196 ms->possible_cpus->cpus[i].props.has_socket_id = true;
197 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
198 if (x86ms->smp_dies > 1) {
199 ms->possible_cpus->cpus[i].props.has_die_id = true;
200 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
201 }
202 ms->possible_cpus->cpus[i].props.has_core_id = true;
203 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
204 ms->possible_cpus->cpus[i].props.has_thread_id = true;
205 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id;
206 }
207 return ms->possible_cpus;
208 }
209
210 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
211 {
212 /* cpu index isn't used */
213 CPUState *cs;
214
215 CPU_FOREACH(cs) {
216 X86CPU *cpu = X86_CPU(cs);
217
218 if (!cpu->apic_state) {
219 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
220 } else {
221 apic_deliver_nmi(cpu->apic_state);
222 }
223 }
224 }
225
226 static long get_file_size(FILE *f)
227 {
228 long where, size;
229
230 /* XXX: on Unix systems, using fstat() probably makes more sense */
231
232 where = ftell(f);
233 fseek(f, 0, SEEK_END);
234 size = ftell(f);
235 fseek(f, where, SEEK_SET);
236
237 return size;
238 }
239
240 /* TSC handling */
241 uint64_t cpu_get_tsc(CPUX86State *env)
242 {
243 return cpu_get_ticks();
244 }
245
246 /* IRQ handling */
247 static void pic_irq_request(void *opaque, int irq, int level)
248 {
249 CPUState *cs = first_cpu;
250 X86CPU *cpu = X86_CPU(cs);
251
252 trace_x86_pic_interrupt(irq, level);
253 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
254 CPU_FOREACH(cs) {
255 cpu = X86_CPU(cs);
256 if (apic_accept_pic_intr(cpu->apic_state)) {
257 apic_deliver_pic_intr(cpu->apic_state, level);
258 }
259 }
260 } else {
261 if (level) {
262 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
263 } else {
264 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
265 }
266 }
267 }
268
269 qemu_irq x86_allocate_cpu_irq(void)
270 {
271 return qemu_allocate_irq(pic_irq_request, NULL, 0);
272 }
273
274 int cpu_get_pic_interrupt(CPUX86State *env)
275 {
276 X86CPU *cpu = env_archcpu(env);
277 int intno;
278
279 if (!kvm_irqchip_in_kernel()) {
280 intno = apic_get_interrupt(cpu->apic_state);
281 if (intno >= 0) {
282 return intno;
283 }
284 /* read the irq from the PIC */
285 if (!apic_accept_pic_intr(cpu->apic_state)) {
286 return -1;
287 }
288 }
289
290 intno = pic_read_irq(isa_pic);
291 return intno;
292 }
293
294 DeviceState *cpu_get_current_apic(void)
295 {
296 if (current_cpu) {
297 X86CPU *cpu = X86_CPU(current_cpu);
298 return cpu->apic_state;
299 } else {
300 return NULL;
301 }
302 }
303
304 void gsi_handler(void *opaque, int n, int level)
305 {
306 GSIState *s = opaque;
307
308 trace_x86_gsi_interrupt(n, level);
309 if (n < ISA_NUM_IRQS) {
310 /* Under KVM, Kernel will forward to both PIC and IOAPIC */
311 qemu_set_irq(s->i8259_irq[n], level);
312 }
313 qemu_set_irq(s->ioapic_irq[n], level);
314 }
315
316 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
317 {
318 DeviceState *dev;
319 SysBusDevice *d;
320 unsigned int i;
321
322 assert(parent_name);
323 if (kvm_ioapic_in_kernel()) {
324 dev = qdev_new(TYPE_KVM_IOAPIC);
325 } else {
326 dev = qdev_new(TYPE_IOAPIC);
327 }
328 object_property_add_child(object_resolve_path(parent_name, NULL),
329 "ioapic", OBJECT(dev));
330 d = SYS_BUS_DEVICE(dev);
331 sysbus_realize_and_unref(d, &error_fatal);
332 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
333
334 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
335 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
336 }
337 }
338
339 struct setup_data {
340 uint64_t next;
341 uint32_t type;
342 uint32_t len;
343 uint8_t data[];
344 } __attribute__((packed));
345
346
347 /*
348 * The entry point into the kernel for PVH boot is different from
349 * the native entry point. The PVH entry is defined by the x86/HVM
350 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
351 *
352 * This function is passed to load_elf() when it is called from
353 * load_elfboot() which then additionally checks for an ELF Note of
354 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
355 * parse the PVH entry address from the ELF Note.
356 *
357 * Due to trickery in elf_opts.h, load_elf() is actually available as
358 * load_elf32() or load_elf64() and this routine needs to be able
359 * to deal with being called as 32 or 64 bit.
360 *
361 * The address of the PVH entry point is saved to the 'pvh_start_addr'
362 * global variable. (although the entry point is 32-bit, the kernel
363 * binary can be either 32-bit or 64-bit).
364 */
365 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
366 {
367 size_t *elf_note_data_addr;
368
369 /* Check if ELF Note header passed in is valid */
370 if (arg1 == NULL) {
371 return 0;
372 }
373
374 if (is64) {
375 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
376 uint64_t nhdr_size64 = sizeof(struct elf64_note);
377 uint64_t phdr_align = *(uint64_t *)arg2;
378 uint64_t nhdr_namesz = nhdr64->n_namesz;
379
380 elf_note_data_addr =
381 ((void *)nhdr64) + nhdr_size64 +
382 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
383 } else {
384 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
385 uint32_t nhdr_size32 = sizeof(struct elf32_note);
386 uint32_t phdr_align = *(uint32_t *)arg2;
387 uint32_t nhdr_namesz = nhdr32->n_namesz;
388
389 elf_note_data_addr =
390 ((void *)nhdr32) + nhdr_size32 +
391 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
392 }
393
394 pvh_start_addr = *elf_note_data_addr;
395
396 return pvh_start_addr;
397 }
398
399 static bool load_elfboot(const char *kernel_filename,
400 int kernel_file_size,
401 uint8_t *header,
402 size_t pvh_xen_start_addr,
403 FWCfgState *fw_cfg)
404 {
405 uint32_t flags = 0;
406 uint32_t mh_load_addr = 0;
407 uint32_t elf_kernel_size = 0;
408 uint64_t elf_entry;
409 uint64_t elf_low, elf_high;
410 int kernel_size;
411
412 if (ldl_p(header) != 0x464c457f) {
413 return false; /* no elfboot */
414 }
415
416 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
417 flags = elf_is64 ?
418 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
419
420 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
421 error_report("elfboot unsupported flags = %x", flags);
422 exit(1);
423 }
424
425 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
426 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
427 NULL, &elf_note_type, &elf_entry,
428 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE,
429 0, 0);
430
431 if (kernel_size < 0) {
432 error_report("Error while loading elf kernel");
433 exit(1);
434 }
435 mh_load_addr = elf_low;
436 elf_kernel_size = elf_high - elf_low;
437
438 if (pvh_start_addr == 0) {
439 error_report("Error loading uncompressed kernel without PVH ELF Note");
440 exit(1);
441 }
442 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
443 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
444 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
445
446 return true;
447 }
448
449 void x86_load_linux(X86MachineState *x86ms,
450 FWCfgState *fw_cfg,
451 int acpi_data_size,
452 bool pvh_enabled,
453 bool linuxboot_dma_enabled)
454 {
455 uint16_t protocol;
456 int setup_size, kernel_size, cmdline_size;
457 int dtb_size, setup_data_offset;
458 uint32_t initrd_max;
459 uint8_t header[8192], *setup, *kernel;
460 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
461 FILE *f;
462 char *vmode;
463 MachineState *machine = MACHINE(x86ms);
464 struct setup_data *setup_data;
465 const char *kernel_filename = machine->kernel_filename;
466 const char *initrd_filename = machine->initrd_filename;
467 const char *dtb_filename = machine->dtb;
468 const char *kernel_cmdline = machine->kernel_cmdline;
469
470 /* Align to 16 bytes as a paranoia measure */
471 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
472
473 /* load the kernel header */
474 f = fopen(kernel_filename, "rb");
475 if (!f) {
476 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
477 kernel_filename, strerror(errno));
478 exit(1);
479 }
480
481 kernel_size = get_file_size(f);
482 if (!kernel_size ||
483 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
484 MIN(ARRAY_SIZE(header), kernel_size)) {
485 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
486 kernel_filename, strerror(errno));
487 exit(1);
488 }
489
490 /* kernel protocol version */
491 if (ldl_p(header + 0x202) == 0x53726448) {
492 protocol = lduw_p(header + 0x206);
493 } else {
494 /*
495 * This could be a multiboot kernel. If it is, let's stop treating it
496 * like a Linux kernel.
497 * Note: some multiboot images could be in the ELF format (the same of
498 * PVH), so we try multiboot first since we check the multiboot magic
499 * header before to load it.
500 */
501 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
502 kernel_cmdline, kernel_size, header)) {
503 return;
504 }
505 /*
506 * Check if the file is an uncompressed kernel file (ELF) and load it,
507 * saving the PVH entry point used by the x86/HVM direct boot ABI.
508 * If load_elfboot() is successful, populate the fw_cfg info.
509 */
510 if (pvh_enabled &&
511 load_elfboot(kernel_filename, kernel_size,
512 header, pvh_start_addr, fw_cfg)) {
513 fclose(f);
514
515 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
516 strlen(kernel_cmdline) + 1);
517 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
518
519 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
520 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
521 header, sizeof(header));
522
523 /* load initrd */
524 if (initrd_filename) {
525 GMappedFile *mapped_file;
526 gsize initrd_size;
527 gchar *initrd_data;
528 GError *gerr = NULL;
529
530 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
531 if (!mapped_file) {
532 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
533 initrd_filename, gerr->message);
534 exit(1);
535 }
536 x86ms->initrd_mapped_file = mapped_file;
537
538 initrd_data = g_mapped_file_get_contents(mapped_file);
539 initrd_size = g_mapped_file_get_length(mapped_file);
540 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
541 if (initrd_size >= initrd_max) {
542 fprintf(stderr, "qemu: initrd is too large, cannot support."
543 "(max: %"PRIu32", need %"PRId64")\n",
544 initrd_max, (uint64_t)initrd_size);
545 exit(1);
546 }
547
548 initrd_addr = (initrd_max - initrd_size) & ~4095;
549
550 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
551 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
552 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
553 initrd_size);
554 }
555
556 option_rom[nb_option_roms].bootindex = 0;
557 option_rom[nb_option_roms].name = "pvh.bin";
558 nb_option_roms++;
559
560 return;
561 }
562 protocol = 0;
563 }
564
565 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
566 /* Low kernel */
567 real_addr = 0x90000;
568 cmdline_addr = 0x9a000 - cmdline_size;
569 prot_addr = 0x10000;
570 } else if (protocol < 0x202) {
571 /* High but ancient kernel */
572 real_addr = 0x90000;
573 cmdline_addr = 0x9a000 - cmdline_size;
574 prot_addr = 0x100000;
575 } else {
576 /* High and recent kernel */
577 real_addr = 0x10000;
578 cmdline_addr = 0x20000;
579 prot_addr = 0x100000;
580 }
581
582 /* highest address for loading the initrd */
583 if (protocol >= 0x20c &&
584 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
585 /*
586 * Linux has supported initrd up to 4 GB for a very long time (2007,
587 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
588 * though it only sets initrd_max to 2 GB to "work around bootloader
589 * bugs". Luckily, QEMU firmware(which does something like bootloader)
590 * has supported this.
591 *
592 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
593 * be loaded into any address.
594 *
595 * In addition, initrd_max is uint32_t simply because QEMU doesn't
596 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
597 * field).
598 *
599 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
600 */
601 initrd_max = UINT32_MAX;
602 } else if (protocol >= 0x203) {
603 initrd_max = ldl_p(header + 0x22c);
604 } else {
605 initrd_max = 0x37ffffff;
606 }
607
608 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) {
609 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
610 }
611
612 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
613 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
614 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
615
616 if (protocol >= 0x202) {
617 stl_p(header + 0x228, cmdline_addr);
618 } else {
619 stw_p(header + 0x20, 0xA33F);
620 stw_p(header + 0x22, cmdline_addr - real_addr);
621 }
622
623 /* handle vga= parameter */
624 vmode = strstr(kernel_cmdline, "vga=");
625 if (vmode) {
626 unsigned int video_mode;
627 const char *end;
628 int ret;
629 /* skip "vga=" */
630 vmode += 4;
631 if (!strncmp(vmode, "normal", 6)) {
632 video_mode = 0xffff;
633 } else if (!strncmp(vmode, "ext", 3)) {
634 video_mode = 0xfffe;
635 } else if (!strncmp(vmode, "ask", 3)) {
636 video_mode = 0xfffd;
637 } else {
638 ret = qemu_strtoui(vmode, &end, 0, &video_mode);
639 if (ret != 0 || (*end && *end != ' ')) {
640 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n");
641 exit(1);
642 }
643 }
644 stw_p(header + 0x1fa, video_mode);
645 }
646
647 /* loader type */
648 /*
649 * High nybble = B reserved for QEMU; low nybble is revision number.
650 * If this code is substantially changed, you may want to consider
651 * incrementing the revision.
652 */
653 if (protocol >= 0x200) {
654 header[0x210] = 0xB0;
655 }
656 /* heap */
657 if (protocol >= 0x201) {
658 header[0x211] |= 0x80; /* CAN_USE_HEAP */
659 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
660 }
661
662 /* load initrd */
663 if (initrd_filename) {
664 GMappedFile *mapped_file;
665 gsize initrd_size;
666 gchar *initrd_data;
667 GError *gerr = NULL;
668
669 if (protocol < 0x200) {
670 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
671 exit(1);
672 }
673
674 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
675 if (!mapped_file) {
676 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
677 initrd_filename, gerr->message);
678 exit(1);
679 }
680 x86ms->initrd_mapped_file = mapped_file;
681
682 initrd_data = g_mapped_file_get_contents(mapped_file);
683 initrd_size = g_mapped_file_get_length(mapped_file);
684 if (initrd_size >= initrd_max) {
685 fprintf(stderr, "qemu: initrd is too large, cannot support."
686 "(max: %"PRIu32", need %"PRId64")\n",
687 initrd_max, (uint64_t)initrd_size);
688 exit(1);
689 }
690
691 initrd_addr = (initrd_max - initrd_size) & ~4095;
692
693 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
694 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
695 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
696
697 stl_p(header + 0x218, initrd_addr);
698 stl_p(header + 0x21c, initrd_size);
699 }
700
701 /* load kernel and setup */
702 setup_size = header[0x1f1];
703 if (setup_size == 0) {
704 setup_size = 4;
705 }
706 setup_size = (setup_size + 1) * 512;
707 if (setup_size > kernel_size) {
708 fprintf(stderr, "qemu: invalid kernel header\n");
709 exit(1);
710 }
711 kernel_size -= setup_size;
712
713 setup = g_malloc(setup_size);
714 kernel = g_malloc(kernel_size);
715 fseek(f, 0, SEEK_SET);
716 if (fread(setup, 1, setup_size, f) != setup_size) {
717 fprintf(stderr, "fread() failed\n");
718 exit(1);
719 }
720 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
721 fprintf(stderr, "fread() failed\n");
722 exit(1);
723 }
724 fclose(f);
725
726 /* append dtb to kernel */
727 if (dtb_filename) {
728 if (protocol < 0x209) {
729 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
730 exit(1);
731 }
732
733 dtb_size = get_image_size(dtb_filename);
734 if (dtb_size <= 0) {
735 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
736 dtb_filename, strerror(errno));
737 exit(1);
738 }
739
740 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
741 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
742 kernel = g_realloc(kernel, kernel_size);
743
744 stq_p(header + 0x250, prot_addr + setup_data_offset);
745
746 setup_data = (struct setup_data *)(kernel + setup_data_offset);
747 setup_data->next = 0;
748 setup_data->type = cpu_to_le32(SETUP_DTB);
749 setup_data->len = cpu_to_le32(dtb_size);
750
751 load_image_size(dtb_filename, setup_data->data, dtb_size);
752 }
753
754 memcpy(setup, header, MIN(sizeof(header), setup_size));
755
756 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
757 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
758 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
759
760 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
761 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
762 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
763
764 option_rom[nb_option_roms].bootindex = 0;
765 option_rom[nb_option_roms].name = "linuxboot.bin";
766 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
767 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
768 }
769 nb_option_roms++;
770 }
771
772 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
773 {
774 char *filename;
775 MemoryRegion *bios, *isa_bios;
776 int bios_size, isa_bios_size;
777 int ret;
778
779 /* BIOS load */
780 if (bios_name == NULL) {
781 bios_name = BIOS_FILENAME;
782 }
783 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
784 if (filename) {
785 bios_size = get_image_size(filename);
786 } else {
787 bios_size = -1;
788 }
789 if (bios_size <= 0 ||
790 (bios_size % 65536) != 0) {
791 goto bios_error;
792 }
793 bios = g_malloc(sizeof(*bios));
794 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal);
795 if (!isapc_ram_fw) {
796 memory_region_set_readonly(bios, true);
797 }
798 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
799 if (ret != 0) {
800 bios_error:
801 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
802 exit(1);
803 }
804 g_free(filename);
805
806 /* map the last 128KB of the BIOS in ISA space */
807 isa_bios_size = MIN(bios_size, 128 * KiB);
808 isa_bios = g_malloc(sizeof(*isa_bios));
809 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
810 bios_size - isa_bios_size, isa_bios_size);
811 memory_region_add_subregion_overlap(rom_memory,
812 0x100000 - isa_bios_size,
813 isa_bios,
814 1);
815 if (!isapc_ram_fw) {
816 memory_region_set_readonly(isa_bios, true);
817 }
818
819 /* map all the bios at the top of memory */
820 memory_region_add_subregion(rom_memory,
821 (uint32_t)(-bios_size),
822 bios);
823 }
824
825 bool x86_machine_is_smm_enabled(X86MachineState *x86ms)
826 {
827 bool smm_available = false;
828
829 if (x86ms->smm == ON_OFF_AUTO_OFF) {
830 return false;
831 }
832
833 if (tcg_enabled() || qtest_enabled()) {
834 smm_available = true;
835 } else if (kvm_enabled()) {
836 smm_available = kvm_has_smm();
837 }
838
839 if (smm_available) {
840 return true;
841 }
842
843 if (x86ms->smm == ON_OFF_AUTO_ON) {
844 error_report("System Management Mode not supported by this hypervisor.");
845 exit(1);
846 }
847 return false;
848 }
849
850 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name,
851 void *opaque, Error **errp)
852 {
853 X86MachineState *x86ms = X86_MACHINE(obj);
854 OnOffAuto smm = x86ms->smm;
855
856 visit_type_OnOffAuto(v, name, &smm, errp);
857 }
858
859 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name,
860 void *opaque, Error **errp)
861 {
862 X86MachineState *x86ms = X86_MACHINE(obj);
863
864 visit_type_OnOffAuto(v, name, &x86ms->smm, errp);
865 }
866
867 bool x86_machine_is_acpi_enabled(X86MachineState *x86ms)
868 {
869 if (x86ms->acpi == ON_OFF_AUTO_OFF) {
870 return false;
871 }
872 return true;
873 }
874
875 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name,
876 void *opaque, Error **errp)
877 {
878 X86MachineState *x86ms = X86_MACHINE(obj);
879 OnOffAuto acpi = x86ms->acpi;
880
881 visit_type_OnOffAuto(v, name, &acpi, errp);
882 }
883
884 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name,
885 void *opaque, Error **errp)
886 {
887 X86MachineState *x86ms = X86_MACHINE(obj);
888
889 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp);
890 }
891
892 static void x86_machine_initfn(Object *obj)
893 {
894 X86MachineState *x86ms = X86_MACHINE(obj);
895
896 x86ms->smm = ON_OFF_AUTO_AUTO;
897 x86ms->acpi = ON_OFF_AUTO_AUTO;
898 x86ms->smp_dies = 1;
899 }
900
901 static void x86_machine_class_init(ObjectClass *oc, void *data)
902 {
903 MachineClass *mc = MACHINE_CLASS(oc);
904 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
905 NMIClass *nc = NMI_CLASS(oc);
906
907 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
908 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
909 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
910 x86mc->compat_apic_id_mode = false;
911 x86mc->save_tsc_khz = true;
912 nc->nmi_monitor_handler = x86_nmi;
913
914 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto",
915 x86_machine_get_smm, x86_machine_set_smm,
916 NULL, NULL);
917 object_class_property_set_description(oc, X86_MACHINE_SMM,
918 "Enable SMM");
919
920 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto",
921 x86_machine_get_acpi, x86_machine_set_acpi,
922 NULL, NULL);
923 object_class_property_set_description(oc, X86_MACHINE_ACPI,
924 "Enable ACPI");
925 }
926
927 static const TypeInfo x86_machine_info = {
928 .name = TYPE_X86_MACHINE,
929 .parent = TYPE_MACHINE,
930 .abstract = true,
931 .instance_size = sizeof(X86MachineState),
932 .instance_init = x86_machine_initfn,
933 .class_size = sizeof(X86MachineClass),
934 .class_init = x86_machine_class_init,
935 .interfaces = (InterfaceInfo[]) {
936 { TYPE_NMI },
937 { }
938 },
939 };
940
941 static void x86_machine_register_types(void)
942 {
943 type_register_static(&x86_machine_info);
944 }
945
946 type_init(x86_machine_register_types)