ahci: add is_ncq predicate helper
[qemu.git] / hw / ide / ahci.h
1 /*
2 * QEMU AHCI Emulation
3 *
4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #ifndef HW_IDE_AHCI_H
25 #define HW_IDE_AHCI_H
26
27 #define AHCI_MEM_BAR_SIZE 0x1000
28 #define AHCI_MAX_PORTS 32
29 #define AHCI_MAX_SG 168 /* hardware max is 64K */
30 #define AHCI_DMA_BOUNDARY 0xffffffff
31 #define AHCI_USE_CLUSTERING 0
32 #define AHCI_MAX_CMDS 32
33 #define AHCI_CMD_SZ 32
34 #define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
35 #define AHCI_RX_FIS_SZ 256
36 #define AHCI_CMD_TBL_CDB 0x40
37 #define AHCI_CMD_TBL_HDR_SZ 0x80
38 #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
39 #define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
40 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
41 AHCI_RX_FIS_SZ)
42
43 #define AHCI_IRQ_ON_SG (1U << 31)
44 #define AHCI_CMD_ATAPI (1 << 5)
45 #define AHCI_CMD_WRITE (1 << 6)
46 #define AHCI_CMD_PREFETCH (1 << 7)
47 #define AHCI_CMD_RESET (1 << 8)
48 #define AHCI_CMD_CLR_BUSY (1 << 10)
49
50 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
51 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
52 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
53
54 /* global controller registers */
55 #define HOST_CAP 0x00 /* host capabilities */
56 #define HOST_CTL 0x04 /* global host control */
57 #define HOST_IRQ_STAT 0x08 /* interrupt status */
58 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
59 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
60
61 /* HOST_CTL bits */
62 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
63 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
64 #define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */
65
66 /* HOST_CAP bits */
67 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */
68 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */
69 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */
70 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
71 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
72 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
73
74 /* registers for each SATA port */
75 #define PORT_LST_ADDR 0x00 /* command list DMA addr */
76 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
77 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
78 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
79 #define PORT_IRQ_STAT 0x10 /* interrupt status */
80 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
81 #define PORT_CMD 0x18 /* port command */
82 #define PORT_TFDATA 0x20 /* taskfile data */
83 #define PORT_SIG 0x24 /* device TF signature */
84 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
85 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
86 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
87 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
88 #define PORT_CMD_ISSUE 0x38 /* command issue */
89 #define PORT_RESERVED 0x3c /* reserved */
90
91 /* PORT_IRQ_{STAT,MASK} bits */
92 #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */
93 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
94 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
95 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
96 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
97 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
98 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
99 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
100
101 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
102 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
103 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
104 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
105 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
106 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
107 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
108 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
109 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
110
111 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
112 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
113 PORT_IRQ_UNK_FIS)
114 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
115 PORT_IRQ_HBUS_DATA_ERR)
116 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
117 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
118 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
119
120 /* PORT_CMD bits */
121 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
122 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
123 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
124 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
125 #define PORT_CMD_CLO (1 << 3) /* Command list override */
126 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
127 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
128 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
129
130 #define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
131 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
132 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
133 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
134
135 /* ap->flags bits */
136 #define AHCI_FLAG_NO_NCQ (1 << 24)
137 #define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
138 #define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */
139 #define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */
140 #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */
141
142 #define ATA_SRST (1 << 2) /* software reset */
143
144 #define STATE_RUN 0
145 #define STATE_RESET 1
146
147 #define SATA_SCR_SSTATUS_DET_NODEV 0x0
148 #define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
149
150 #define SATA_SCR_SSTATUS_SPD_NODEV 0x00
151 #define SATA_SCR_SSTATUS_SPD_GEN1 0x10
152
153 #define SATA_SCR_SSTATUS_IPM_NODEV 0x000
154 #define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
155
156 #define AHCI_SCR_SCTL_DET 0xf
157
158 #define SATA_FIS_TYPE_REGISTER_H2D 0x27
159 #define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
160
161 #define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
162 #define AHCI_CMD_HDR_PRDT_LEN 16
163
164 #define SATA_SIGNATURE_CDROM 0xeb140000
165 #define SATA_SIGNATURE_DISK 0x00000101
166
167 #define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
168 /* Shouldn't this be 0x2c? */
169
170 #define AHCI_PORT_REGS_START_ADDR 0x100
171 #define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
172 #define AHCI_PORT_ADDR_OFFSET_LEN 0x80
173
174 #define AHCI_NUM_COMMAND_SLOTS 31
175 #define AHCI_SUPPORTED_SPEED 20
176 #define AHCI_SUPPORTED_SPEED_GEN1 1
177 #define AHCI_VERSION_1_0 0x10000
178
179 #define AHCI_PROGMODE_MAJOR_REV_1 1
180
181 #define AHCI_COMMAND_TABLE_ACMD 0x40
182
183 #define AHCI_PRDT_SIZE_MASK 0x3fffff
184
185 #define IDE_FEATURE_DMA 1
186
187 #define READ_FPDMA_QUEUED 0x60
188 #define WRITE_FPDMA_QUEUED 0x61
189 #define NCQ_NON_DATA 0x63
190 #define RECEIVE_FPDMA_QUEUED 0x65
191 #define SEND_FPDMA_QUEUED 0x64
192
193 #define RES_FIS_DSFIS 0x00
194 #define RES_FIS_PSFIS 0x20
195 #define RES_FIS_RFIS 0x40
196 #define RES_FIS_SDBFIS 0x58
197 #define RES_FIS_UFIS 0x60
198
199 #define SATA_CAP_SIZE 0x8
200 #define SATA_CAP_REV 0x2
201 #define SATA_CAP_BAR 0x4
202
203 typedef struct AHCIControlRegs {
204 uint32_t cap;
205 uint32_t ghc;
206 uint32_t irqstatus;
207 uint32_t impl;
208 uint32_t version;
209 } AHCIControlRegs;
210
211 typedef struct AHCIPortRegs {
212 uint32_t lst_addr;
213 uint32_t lst_addr_hi;
214 uint32_t fis_addr;
215 uint32_t fis_addr_hi;
216 uint32_t irq_stat;
217 uint32_t irq_mask;
218 uint32_t cmd;
219 uint32_t unused0;
220 uint32_t tfdata;
221 uint32_t sig;
222 uint32_t scr_stat;
223 uint32_t scr_ctl;
224 uint32_t scr_err;
225 uint32_t scr_act;
226 uint32_t cmd_issue;
227 uint32_t reserved;
228 } AHCIPortRegs;
229
230 typedef struct AHCICmdHdr {
231 uint32_t opts;
232 uint32_t status;
233 uint64_t tbl_addr;
234 uint32_t reserved[4];
235 } QEMU_PACKED AHCICmdHdr;
236
237 typedef struct AHCI_SG {
238 uint64_t addr;
239 uint32_t reserved;
240 uint32_t flags_size;
241 } QEMU_PACKED AHCI_SG;
242
243 typedef struct AHCIDevice AHCIDevice;
244
245 typedef struct NCQTransferState {
246 AHCIDevice *drive;
247 BlockAIOCB *aiocb;
248 QEMUSGList sglist;
249 BlockAcctCookie acct;
250 uint16_t sector_count;
251 uint64_t lba;
252 uint8_t tag;
253 int slot;
254 int used;
255 } NCQTransferState;
256
257 struct AHCIDevice {
258 IDEDMA dma;
259 IDEBus port;
260 int port_no;
261 uint32_t port_state;
262 uint32_t finished;
263 AHCIPortRegs port_regs;
264 struct AHCIState *hba;
265 QEMUBH *check_bh;
266 uint8_t *lst;
267 uint8_t *res_fis;
268 bool done_atapi_packet;
269 int32_t busy_slot;
270 bool init_d2h_sent;
271 AHCICmdHdr *cur_cmd;
272 NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
273 };
274
275 typedef struct AHCIState {
276 AHCIDevice *dev;
277 AHCIControlRegs control_regs;
278 MemoryRegion mem;
279 MemoryRegion idp; /* Index-Data Pair I/O port space */
280 unsigned idp_offset; /* Offset of index in I/O port space */
281 uint32_t idp_index; /* Current IDP index */
282 int32_t ports;
283 qemu_irq irq;
284 AddressSpace *as;
285 } AHCIState;
286
287 typedef struct AHCIPCIState {
288 /*< private >*/
289 PCIDevice parent_obj;
290 /*< public >*/
291
292 AHCIState ahci;
293 } AHCIPCIState;
294
295 #define TYPE_ICH9_AHCI "ich9-ahci"
296
297 #define ICH_AHCI(obj) \
298 OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
299
300 extern const VMStateDescription vmstate_ahci;
301
302 #define VMSTATE_AHCI(_field, _state) { \
303 .name = (stringify(_field)), \
304 .size = sizeof(AHCIState), \
305 .vmsd = &vmstate_ahci, \
306 .flags = VMS_STRUCT, \
307 .offset = vmstate_offset_value(_state, _field, AHCIState), \
308 }
309
310 typedef struct NCQFrame {
311 uint8_t fis_type;
312 uint8_t c;
313 uint8_t command;
314 uint8_t sector_count_low;
315 uint8_t lba0;
316 uint8_t lba1;
317 uint8_t lba2;
318 uint8_t fua;
319 uint8_t lba3;
320 uint8_t lba4;
321 uint8_t lba5;
322 uint8_t sector_count_high;
323 uint8_t tag;
324 uint8_t reserved5;
325 uint8_t reserved6;
326 uint8_t control;
327 uint8_t reserved7;
328 uint8_t reserved8;
329 uint8_t reserved9;
330 uint8_t reserved10;
331 } QEMU_PACKED NCQFrame;
332
333 typedef struct SDBFIS {
334 uint8_t type;
335 uint8_t flags;
336 uint8_t status;
337 uint8_t error;
338 uint32_t payload;
339 } QEMU_PACKED SDBFIS;
340
341 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
342 void ahci_uninit(AHCIState *s);
343
344 void ahci_reset(AHCIState *s);
345
346 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
347
348 #endif /* HW_IDE_AHCI_H */