pcie_aer: support configurable AER capa version
[qemu.git] / hw / ide / cmd646.c
1 /*
2 * QEMU IDE Emulation: PCI cmd646 support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/isa/isa.h"
30 #include "sysemu/block-backend.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33
34 #include "hw/ide/pci.h"
35
36 /* CMD646 specific */
37 #define CFR 0x50
38 #define CFR_INTR_CH0 0x04
39 #define CNTRL 0x51
40 #define CNTRL_EN_CH0 0x04
41 #define CNTRL_EN_CH1 0x08
42 #define ARTTIM23 0x57
43 #define ARTTIM23_INTR_CH1 0x10
44 #define MRDMODE 0x71
45 #define MRDMODE_INTR_CH0 0x04
46 #define MRDMODE_INTR_CH1 0x08
47 #define MRDMODE_BLK_CH0 0x10
48 #define MRDMODE_BLK_CH1 0x20
49 #define UDIDETCR0 0x73
50 #define UDIDETCR1 0x7B
51
52 static void cmd646_update_irq(PCIDevice *pd);
53
54 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
55 unsigned size)
56 {
57 CMD646BAR *cmd646bar = opaque;
58
59 if (addr != 2 || size != 1) {
60 return ((uint64_t)1 << (size * 8)) - 1;
61 }
62 return ide_status_read(cmd646bar->bus, addr + 2);
63 }
64
65 static void cmd646_cmd_write(void *opaque, hwaddr addr,
66 uint64_t data, unsigned size)
67 {
68 CMD646BAR *cmd646bar = opaque;
69
70 if (addr != 2 || size != 1) {
71 return;
72 }
73 ide_cmd_write(cmd646bar->bus, addr + 2, data);
74 }
75
76 static const MemoryRegionOps cmd646_cmd_ops = {
77 .read = cmd646_cmd_read,
78 .write = cmd646_cmd_write,
79 .endianness = DEVICE_LITTLE_ENDIAN,
80 };
81
82 static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
83 unsigned size)
84 {
85 CMD646BAR *cmd646bar = opaque;
86
87 if (size == 1) {
88 return ide_ioport_read(cmd646bar->bus, addr);
89 } else if (addr == 0) {
90 if (size == 2) {
91 return ide_data_readw(cmd646bar->bus, addr);
92 } else {
93 return ide_data_readl(cmd646bar->bus, addr);
94 }
95 }
96 return ((uint64_t)1 << (size * 8)) - 1;
97 }
98
99 static void cmd646_data_write(void *opaque, hwaddr addr,
100 uint64_t data, unsigned size)
101 {
102 CMD646BAR *cmd646bar = opaque;
103
104 if (size == 1) {
105 ide_ioport_write(cmd646bar->bus, addr, data);
106 } else if (addr == 0) {
107 if (size == 2) {
108 ide_data_writew(cmd646bar->bus, addr, data);
109 } else {
110 ide_data_writel(cmd646bar->bus, addr, data);
111 }
112 }
113 }
114
115 static const MemoryRegionOps cmd646_data_ops = {
116 .read = cmd646_data_read,
117 .write = cmd646_data_write,
118 .endianness = DEVICE_LITTLE_ENDIAN,
119 };
120
121 static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
122 {
123 IDEBus *bus = &d->bus[bus_num];
124 CMD646BAR *bar = &d->cmd646_bar[bus_num];
125
126 bar->bus = bus;
127 bar->pci_dev = d;
128 memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
129 "cmd646-cmd", 4);
130 memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
131 "cmd646-data", 8);
132 }
133
134 static void cmd646_update_dma_interrupts(PCIDevice *pd)
135 {
136 /* Sync DMA interrupt status from UDMA interrupt status */
137 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
138 pd->config[CFR] |= CFR_INTR_CH0;
139 } else {
140 pd->config[CFR] &= ~CFR_INTR_CH0;
141 }
142
143 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
144 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
145 } else {
146 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
147 }
148 }
149
150 static void cmd646_update_udma_interrupts(PCIDevice *pd)
151 {
152 /* Sync UDMA interrupt status from DMA interrupt status */
153 if (pd->config[CFR] & CFR_INTR_CH0) {
154 pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
155 } else {
156 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
157 }
158
159 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
160 pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
161 } else {
162 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
163 }
164 }
165
166 static uint64_t bmdma_read(void *opaque, hwaddr addr,
167 unsigned size)
168 {
169 BMDMAState *bm = opaque;
170 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
171 uint32_t val;
172
173 if (size != 1) {
174 return ((uint64_t)1 << (size * 8)) - 1;
175 }
176
177 switch(addr & 3) {
178 case 0:
179 val = bm->cmd;
180 break;
181 case 1:
182 val = pci_dev->config[MRDMODE];
183 break;
184 case 2:
185 val = bm->status;
186 break;
187 case 3:
188 if (bm == &bm->pci_dev->bmdma[0]) {
189 val = pci_dev->config[UDIDETCR0];
190 } else {
191 val = pci_dev->config[UDIDETCR1];
192 }
193 break;
194 default:
195 val = 0xff;
196 break;
197 }
198 #ifdef DEBUG_IDE
199 printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
200 #endif
201 return val;
202 }
203
204 static void bmdma_write(void *opaque, hwaddr addr,
205 uint64_t val, unsigned size)
206 {
207 BMDMAState *bm = opaque;
208 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
209
210 if (size != 1) {
211 return;
212 }
213
214 #ifdef DEBUG_IDE
215 printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
216 #endif
217 switch(addr & 3) {
218 case 0:
219 bmdma_cmd_writeb(bm, val);
220 break;
221 case 1:
222 pci_dev->config[MRDMODE] =
223 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
224 cmd646_update_dma_interrupts(pci_dev);
225 cmd646_update_irq(pci_dev);
226 break;
227 case 2:
228 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
229 break;
230 case 3:
231 if (bm == &bm->pci_dev->bmdma[0]) {
232 pci_dev->config[UDIDETCR0] = val;
233 } else {
234 pci_dev->config[UDIDETCR1] = val;
235 }
236 break;
237 }
238 }
239
240 static const MemoryRegionOps cmd646_bmdma_ops = {
241 .read = bmdma_read,
242 .write = bmdma_write,
243 };
244
245 static void bmdma_setup_bar(PCIIDEState *d)
246 {
247 BMDMAState *bm;
248 int i;
249
250 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
251 for(i = 0;i < 2; i++) {
252 bm = &d->bmdma[i];
253 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
254 "cmd646-bmdma-bus", 4);
255 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
256 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
257 &bmdma_addr_ioport_ops, bm,
258 "cmd646-bmdma-ioport", 4);
259 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
260 }
261 }
262
263 static void cmd646_update_irq(PCIDevice *pd)
264 {
265 int pci_level;
266
267 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
268 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
269 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
270 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
271 pci_set_irq(pd, pci_level);
272 }
273
274 /* the PCI irq level is the logical OR of the two channels */
275 static void cmd646_set_irq(void *opaque, int channel, int level)
276 {
277 PCIIDEState *d = opaque;
278 PCIDevice *pd = PCI_DEVICE(d);
279 int irq_mask;
280
281 irq_mask = MRDMODE_INTR_CH0 << channel;
282 if (level) {
283 pd->config[MRDMODE] |= irq_mask;
284 } else {
285 pd->config[MRDMODE] &= ~irq_mask;
286 }
287 cmd646_update_dma_interrupts(pd);
288 cmd646_update_irq(pd);
289 }
290
291 static void cmd646_reset(void *opaque)
292 {
293 PCIIDEState *d = opaque;
294 unsigned int i;
295
296 for (i = 0; i < 2; i++) {
297 ide_bus_reset(&d->bus[i]);
298 }
299 }
300
301 static uint32_t cmd646_pci_config_read(PCIDevice *d,
302 uint32_t address, int len)
303 {
304 return pci_default_read_config(d, address, len);
305 }
306
307 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
308 int l)
309 {
310 uint32_t i;
311
312 pci_default_write_config(d, addr, val, l);
313
314 for (i = addr; i < addr + l; i++) {
315 switch (i) {
316 case CFR:
317 case ARTTIM23:
318 cmd646_update_udma_interrupts(d);
319 break;
320 case MRDMODE:
321 cmd646_update_dma_interrupts(d);
322 break;
323 }
324 }
325
326 cmd646_update_irq(d);
327 }
328
329 /* CMD646 PCI IDE controller */
330 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
331 {
332 PCIIDEState *d = PCI_IDE(dev);
333 uint8_t *pci_conf = dev->config;
334 qemu_irq *irq;
335 int i;
336
337 pci_conf[PCI_CLASS_PROG] = 0x8f;
338
339 pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
340 if (d->secondary) {
341 /* XXX: if not enabled, really disable the seconday IDE controller */
342 pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
343 }
344
345 /* Set write-to-clear interrupt bits */
346 dev->wmask[CFR] = 0x0;
347 dev->w1cmask[CFR] = CFR_INTR_CH0;
348 dev->wmask[ARTTIM23] = 0x0;
349 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
350 dev->wmask[MRDMODE] = 0x0;
351 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
352
353 setup_cmd646_bar(d, 0);
354 setup_cmd646_bar(d, 1);
355 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
356 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
357 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
358 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
359 bmdma_setup_bar(d);
360 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
361
362 /* TODO: RST# value should be 0 */
363 pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
364
365 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
366 for (i = 0; i < 2; i++) {
367 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
368 ide_init2(&d->bus[i], irq[i]);
369
370 bmdma_init(&d->bus[i], &d->bmdma[i], d);
371 d->bmdma[i].bus = &d->bus[i];
372 ide_register_restart_cb(&d->bus[i]);
373 }
374
375 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
376 qemu_register_reset(cmd646_reset, d);
377 }
378
379 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
380 {
381 PCIIDEState *d = PCI_IDE(dev);
382 unsigned i;
383
384 for (i = 0; i < 2; ++i) {
385 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
386 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
387 }
388 }
389
390 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
391 int secondary_ide_enabled)
392 {
393 PCIDevice *dev;
394
395 dev = pci_create(bus, -1, "cmd646-ide");
396 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
397 qdev_init_nofail(&dev->qdev);
398
399 pci_ide_create_devs(dev, hd_table);
400 }
401
402 static Property cmd646_ide_properties[] = {
403 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
404 DEFINE_PROP_END_OF_LIST(),
405 };
406
407 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
408 {
409 DeviceClass *dc = DEVICE_CLASS(klass);
410 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
411
412 k->realize = pci_cmd646_ide_realize;
413 k->exit = pci_cmd646_ide_exitfn;
414 k->vendor_id = PCI_VENDOR_ID_CMD;
415 k->device_id = PCI_DEVICE_ID_CMD_646;
416 k->revision = 0x07;
417 k->class_id = PCI_CLASS_STORAGE_IDE;
418 k->config_read = cmd646_pci_config_read;
419 k->config_write = cmd646_pci_config_write;
420 dc->props = cmd646_ide_properties;
421 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
422 }
423
424 static const TypeInfo cmd646_ide_info = {
425 .name = "cmd646-ide",
426 .parent = TYPE_PCI_IDE,
427 .class_init = cmd646_ide_class_init,
428 };
429
430 static void cmd646_ide_register_types(void)
431 {
432 type_register_static(&cmd646_ide_info);
433 }
434
435 type_init(cmd646_ide_register_types)