272b7734b55f5e7
[qemu.git] / hw / ide / ich.c
1 /*
2 * QEMU ICH Emulation
3 *
4 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
5 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 *
21 * lspci dump of a ICH-9 real device
22 *
23 * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
24 * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
25 * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
26 * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
27 * Latency: 0
28 * Interrupt: pin B routed to IRQ 222
29 * Region 0: I/O ports at d000 [size=8]
30 * Region 1: I/O ports at cc00 [size=4]
31 * Region 2: I/O ports at c880 [size=8]
32 * Region 3: I/O ports at c800 [size=4]
33 * Region 4: I/O ports at c480 [size=32]
34 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
36 * Address: fee0f00c Data: 41d9
37 * Capabilities: [70] Power Management version 3
38 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
40 * Capabilities: [a8] SATA HBA <?>
41 * Capabilities: [b0] Vendor Specific Information <?>
42 * Kernel driver in use: ahci
43 * Kernel modules: ahci
44 * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
45 * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
46 * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
47 * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
48 * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
49 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
51 * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
52 * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
53 * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
54 * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
55 * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
56 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
57 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
58 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
59 * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
60 *
61 */
62
63 #include <hw/hw.h>
64 #include <hw/msi.h>
65 #include <hw/pc.h>
66 #include <hw/pci.h>
67 #include <hw/isa.h>
68 #include "block.h"
69 #include "dma.h"
70
71 #include <hw/ide/pci.h>
72 #include <hw/ide/ahci.h>
73
74 #define ICH9_SATA_CAP_OFFSET 0xA8
75
76 #define ICH9_IDP_BAR 4
77 #define ICH9_MEM_BAR 5
78
79 #define ICH9_IDP_INDEX 0x10
80 #define ICH9_IDP_INDEX_LOG2 0x04
81
82 static const VMStateDescription vmstate_ahci = {
83 .name = "ahci",
84 .unmigratable = 1,
85 };
86
87 static void pci_ich9_reset(DeviceState *dev)
88 {
89 struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
90
91 ahci_reset(&d->ahci);
92 }
93
94 static int pci_ich9_ahci_init(PCIDevice *dev)
95 {
96 struct AHCIPCIState *d;
97 int sata_cap_offset;
98 uint8_t *sata_cap;
99 d = DO_UPCAST(struct AHCIPCIState, card, dev);
100
101 ahci_init(&d->ahci, &dev->qdev, pci_dma_context(dev), 6);
102
103 pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
104
105 d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
106 d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
107 pci_config_set_interrupt_pin(d->card.config, 1);
108
109 /* XXX Software should program this register */
110 d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
111
112 msi_init(dev, 0x50, 1, true, false);
113 d->ahci.irq = d->card.irq[0];
114
115 pci_register_bar(&d->card, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
116 &d->ahci.idp);
117 pci_register_bar(&d->card, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
118 &d->ahci.mem);
119
120 sata_cap_offset = pci_add_capability(&d->card, PCI_CAP_ID_SATA,
121 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
122 if (sata_cap_offset < 0) {
123 return sata_cap_offset;
124 }
125
126 sata_cap = d->card.config + sata_cap_offset;
127 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
128 pci_set_long(sata_cap + SATA_CAP_BAR,
129 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
130 d->ahci.idp_offset = ICH9_IDP_INDEX;
131
132 return 0;
133 }
134
135 static void pci_ich9_uninit(PCIDevice *dev)
136 {
137 struct AHCIPCIState *d;
138 d = DO_UPCAST(struct AHCIPCIState, card, dev);
139
140 msi_uninit(dev);
141 ahci_uninit(&d->ahci);
142 }
143
144 static void ich_ahci_class_init(ObjectClass *klass, void *data)
145 {
146 DeviceClass *dc = DEVICE_CLASS(klass);
147 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
148
149 k->init = pci_ich9_ahci_init;
150 k->exit = pci_ich9_uninit;
151 k->vendor_id = PCI_VENDOR_ID_INTEL;
152 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
153 k->revision = 0x02;
154 k->class_id = PCI_CLASS_STORAGE_SATA;
155 dc->vmsd = &vmstate_ahci;
156 dc->reset = pci_ich9_reset;
157 }
158
159 static TypeInfo ich_ahci_info = {
160 .name = "ich9-ahci",
161 .parent = TYPE_PCI_DEVICE,
162 .instance_size = sizeof(AHCIPCIState),
163 .class_init = ich_ahci_class_init,
164 };
165
166 static void ich_ahci_register_types(void)
167 {
168 type_register_static(&ich_ahci_info);
169 }
170
171 type_init(ich_ahci_register_types)