meson: convert qapi-specific to meson
[qemu.git] / hw / ide / microdrive.c
1 /*
2 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/pcmcia.h"
28 #include "migration/vmstate.h"
29 #include "qapi/error.h"
30 #include "qemu/module.h"
31 #include "sysemu/dma.h"
32
33 #include "hw/ide/internal.h"
34
35 #define TYPE_MICRODRIVE "microdrive"
36 #define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)
37
38 /***********************************************************/
39 /* CF-ATA Microdrive */
40
41 #define METADATA_SIZE 0x20
42
43 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
44
45 typedef struct MicroDriveState {
46 /*< private >*/
47 PCMCIACardState parent_obj;
48 /*< public >*/
49
50 IDEBus bus;
51 uint32_t attr_base;
52 uint32_t io_base;
53
54 /* Card state */
55 uint8_t opt;
56 uint8_t stat;
57 uint8_t pins;
58
59 uint8_t ctrl;
60 uint16_t io;
61 uint8_t cycle;
62 } MicroDriveState;
63
64 /* Register bitfields */
65 enum md_opt {
66 OPT_MODE_MMAP = 0,
67 OPT_MODE_IOMAP16 = 1,
68 OPT_MODE_IOMAP1 = 2,
69 OPT_MODE_IOMAP2 = 3,
70 OPT_MODE = 0x3f,
71 OPT_LEVIREQ = 0x40,
72 OPT_SRESET = 0x80,
73 };
74 enum md_cstat {
75 STAT_INT = 0x02,
76 STAT_PWRDWN = 0x04,
77 STAT_XE = 0x10,
78 STAT_IOIS8 = 0x20,
79 STAT_SIGCHG = 0x40,
80 STAT_CHANGED = 0x80,
81 };
82 enum md_pins {
83 PINS_MRDY = 0x02,
84 PINS_CRDY = 0x20,
85 };
86 enum md_ctrl {
87 CTRL_IEN = 0x02,
88 CTRL_SRST = 0x04,
89 };
90
91 static inline void md_interrupt_update(MicroDriveState *s)
92 {
93 PCMCIACardState *card = PCMCIA_CARD(s);
94
95 if (card->slot == NULL) {
96 return;
97 }
98
99 qemu_set_irq(card->slot->irq,
100 !(s->stat & STAT_INT) && /* Inverted */
101 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
102 !(s->opt & OPT_SRESET));
103 }
104
105 static void md_set_irq(void *opaque, int irq, int level)
106 {
107 MicroDriveState *s = opaque;
108
109 if (level) {
110 s->stat |= STAT_INT;
111 } else {
112 s->stat &= ~STAT_INT;
113 }
114
115 md_interrupt_update(s);
116 }
117
118 static void md_reset(DeviceState *dev)
119 {
120 MicroDriveState *s = MICRODRIVE(dev);
121
122 s->opt = OPT_MODE_MMAP;
123 s->stat = 0;
124 s->pins = 0;
125 s->cycle = 0;
126 s->ctrl = 0;
127 ide_bus_reset(&s->bus);
128 }
129
130 static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
131 {
132 MicroDriveState *s = MICRODRIVE(card);
133 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
134
135 if (at < s->attr_base) {
136 if (at < pcc->cis_len) {
137 return pcc->cis[at];
138 } else {
139 return 0x00;
140 }
141 }
142
143 at -= s->attr_base;
144
145 switch (at) {
146 case 0x00: /* Configuration Option Register */
147 return s->opt;
148 case 0x02: /* Card Configuration Status Register */
149 if (s->ctrl & CTRL_IEN) {
150 return s->stat & ~STAT_INT;
151 } else {
152 return s->stat;
153 }
154 case 0x04: /* Pin Replacement Register */
155 return (s->pins & PINS_CRDY) | 0x0c;
156 case 0x06: /* Socket and Copy Register */
157 return 0x00;
158 #ifdef VERBOSE
159 default:
160 printf("%s: Bad attribute space register %02x\n", __func__, at);
161 #endif
162 }
163
164 return 0;
165 }
166
167 static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
168 {
169 MicroDriveState *s = MICRODRIVE(card);
170
171 at -= s->attr_base;
172
173 switch (at) {
174 case 0x00: /* Configuration Option Register */
175 s->opt = value & 0xcf;
176 if (value & OPT_SRESET) {
177 device_legacy_reset(DEVICE(s));
178 }
179 md_interrupt_update(s);
180 break;
181 case 0x02: /* Card Configuration Status Register */
182 if ((s->stat ^ value) & STAT_PWRDWN) {
183 s->pins |= PINS_CRDY;
184 }
185 s->stat &= 0x82;
186 s->stat |= value & 0x74;
187 md_interrupt_update(s);
188 /* Word 170 in Identify Device must be equal to STAT_XE */
189 break;
190 case 0x04: /* Pin Replacement Register */
191 s->pins &= PINS_CRDY;
192 s->pins |= value & PINS_MRDY;
193 break;
194 case 0x06: /* Socket and Copy Register */
195 break;
196 default:
197 printf("%s: Bad attribute space register %02x\n", __func__, at);
198 }
199 }
200
201 static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
202 {
203 MicroDriveState *s = MICRODRIVE(card);
204 IDEState *ifs;
205 uint16_t ret;
206 at -= s->io_base;
207
208 switch (s->opt & OPT_MODE) {
209 case OPT_MODE_MMAP:
210 if ((at & ~0x3ff) == 0x400) {
211 at = 0;
212 }
213 break;
214 case OPT_MODE_IOMAP16:
215 at &= 0xf;
216 break;
217 case OPT_MODE_IOMAP1:
218 if ((at & ~0xf) == 0x3f0) {
219 at -= 0x3e8;
220 } else if ((at & ~0xf) == 0x1f0) {
221 at -= 0x1f0;
222 }
223 break;
224 case OPT_MODE_IOMAP2:
225 if ((at & ~0xf) == 0x370) {
226 at -= 0x368;
227 } else if ((at & ~0xf) == 0x170) {
228 at -= 0x170;
229 }
230 }
231
232 switch (at) {
233 case 0x0: /* Even RD Data */
234 case 0x8:
235 return ide_data_readw(&s->bus, 0);
236
237 /* TODO: 8-bit accesses */
238 if (s->cycle) {
239 ret = s->io >> 8;
240 } else {
241 s->io = ide_data_readw(&s->bus, 0);
242 ret = s->io & 0xff;
243 }
244 s->cycle = !s->cycle;
245 return ret;
246 case 0x9: /* Odd RD Data */
247 return s->io >> 8;
248 case 0xd: /* Error */
249 return ide_ioport_read(&s->bus, 0x1);
250 case 0xe: /* Alternate Status */
251 ifs = idebus_active_if(&s->bus);
252 if (ifs->blk) {
253 return ifs->status;
254 } else {
255 return 0;
256 }
257 case 0xf: /* Device Address */
258 ifs = idebus_active_if(&s->bus);
259 return 0xc2 | ((~ifs->select << 2) & 0x3c);
260 default:
261 return ide_ioport_read(&s->bus, at);
262 }
263
264 return 0;
265 }
266
267 static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
268 {
269 MicroDriveState *s = MICRODRIVE(card);
270 at -= s->io_base;
271
272 switch (s->opt & OPT_MODE) {
273 case OPT_MODE_MMAP:
274 if ((at & ~0x3ff) == 0x400) {
275 at = 0;
276 }
277 break;
278 case OPT_MODE_IOMAP16:
279 at &= 0xf;
280 break;
281 case OPT_MODE_IOMAP1:
282 if ((at & ~0xf) == 0x3f0) {
283 at -= 0x3e8;
284 } else if ((at & ~0xf) == 0x1f0) {
285 at -= 0x1f0;
286 }
287 break;
288 case OPT_MODE_IOMAP2:
289 if ((at & ~0xf) == 0x370) {
290 at -= 0x368;
291 } else if ((at & ~0xf) == 0x170) {
292 at -= 0x170;
293 }
294 }
295
296 switch (at) {
297 case 0x0: /* Even WR Data */
298 case 0x8:
299 ide_data_writew(&s->bus, 0, value);
300 break;
301
302 /* TODO: 8-bit accesses */
303 if (s->cycle) {
304 ide_data_writew(&s->bus, 0, s->io | (value << 8));
305 } else {
306 s->io = value & 0xff;
307 }
308 s->cycle = !s->cycle;
309 break;
310 case 0x9:
311 s->io = value & 0xff;
312 s->cycle = !s->cycle;
313 break;
314 case 0xd: /* Features */
315 ide_ioport_write(&s->bus, 0x1, value);
316 break;
317 case 0xe: /* Device Control */
318 s->ctrl = value;
319 if (value & CTRL_SRST) {
320 device_legacy_reset(DEVICE(s));
321 }
322 md_interrupt_update(s);
323 break;
324 default:
325 if (s->stat & STAT_PWRDWN) {
326 s->pins |= PINS_CRDY;
327 s->stat &= ~STAT_PWRDWN;
328 }
329 ide_ioport_write(&s->bus, at, value);
330 }
331 }
332
333 static const VMStateDescription vmstate_microdrive = {
334 .name = "microdrive",
335 .version_id = 3,
336 .minimum_version_id = 0,
337 .fields = (VMStateField[]) {
338 VMSTATE_UINT8(opt, MicroDriveState),
339 VMSTATE_UINT8(stat, MicroDriveState),
340 VMSTATE_UINT8(pins, MicroDriveState),
341 VMSTATE_UINT8(ctrl, MicroDriveState),
342 VMSTATE_UINT16(io, MicroDriveState),
343 VMSTATE_UINT8(cycle, MicroDriveState),
344 VMSTATE_IDE_BUS(bus, MicroDriveState),
345 VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
346 VMSTATE_END_OF_LIST()
347 }
348 };
349
350 static const uint8_t dscm1xxxx_cis[0x14a] = {
351 [0x000] = CISTPL_DEVICE, /* 5V Device Information */
352 [0x002] = 0x03, /* Tuple length = 4 bytes */
353 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
354 [0x006] = 0x01, /* Size = 2K bytes */
355 [0x008] = CISTPL_ENDMARK,
356
357 [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
358 [0x00c] = 0x04, /* Tuple length = 4 byest */
359 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
360 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
361 [0x012] = 0x01, /* Size = 2K bytes */
362 [0x014] = CISTPL_ENDMARK,
363
364 [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
365 [0x018] = 0x02, /* Tuple length = 2 bytes */
366 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
367 [0x01c] = 0x01,
368
369 [0x01e] = CISTPL_MANFID, /* Manufacture ID */
370 [0x020] = 0x04, /* Tuple length = 4 bytes */
371 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
372 [0x024] = 0x00,
373 [0x026] = 0x00, /* PLMID_CARD = 0000 */
374 [0x028] = 0x00,
375
376 [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
377 [0x02c] = 0x12, /* Tuple length = 23 bytes */
378 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
379 [0x030] = 0x01, /* Minor Version = 1 */
380 [0x032] = 'I',
381 [0x034] = 'B',
382 [0x036] = 'M',
383 [0x038] = 0x00,
384 [0x03a] = 'm',
385 [0x03c] = 'i',
386 [0x03e] = 'c',
387 [0x040] = 'r',
388 [0x042] = 'o',
389 [0x044] = 'd',
390 [0x046] = 'r',
391 [0x048] = 'i',
392 [0x04a] = 'v',
393 [0x04c] = 'e',
394 [0x04e] = 0x00,
395 [0x050] = CISTPL_ENDMARK,
396
397 [0x052] = CISTPL_FUNCID, /* Function ID */
398 [0x054] = 0x02, /* Tuple length = 2 bytes */
399 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
400 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
401
402 [0x05a] = CISTPL_FUNCE, /* Function Extension */
403 [0x05c] = 0x02, /* Tuple length = 2 bytes */
404 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
405 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
406
407 [0x062] = CISTPL_FUNCE, /* Function Extension */
408 [0x064] = 0x03, /* Tuple length = 3 bytes */
409 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
410 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
411 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
412
413 [0x06c] = CISTPL_CONFIG, /* Configuration */
414 [0x06e] = 0x05, /* Tuple length = 5 bytes */
415 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
416 [0x072] = 0x07, /* TPCC_LAST = 7 */
417 [0x074] = 0x00, /* TPCC_RADR = 0200 */
418 [0x076] = 0x02,
419 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
420
421 [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
422 [0x07c] = 0x0b, /* Tuple length = 11 bytes */
423 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
424 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
425 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
426 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
427 [0x086] = 0x55, /* NomV: 5.0 V */
428 [0x088] = 0x4d, /* MinV: 4.5 V */
429 [0x08a] = 0x5d, /* MaxV: 5.5 V */
430 [0x08c] = 0x4e, /* Peakl: 450 mA */
431 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
432 [0x090] = 0x00, /* Window descriptor: Window length = 0 */
433 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
434
435 [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
436 [0x096] = 0x06, /* Tuple length = 6 bytes */
437 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
438 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
439 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
440 [0x09e] = 0xb5, /* NomV: 3.3 V */
441 [0x0a0] = 0x1e,
442 [0x0a2] = 0x3e, /* Peakl: 350 mA */
443
444 [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
445 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
446 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
447 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
448 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
449 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
450 [0x0b0] = 0x55, /* NomV: 5.0 V */
451 [0x0b2] = 0x4d, /* MinV: 4.5 V */
452 [0x0b4] = 0x5d, /* MaxV: 5.5 V */
453 [0x0b6] = 0x4e, /* Peakl: 450 mA */
454 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
455 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
456 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
457 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
458 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
459
460 [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
461 [0x0c4] = 0x06, /* Tuple length = 6 bytes */
462 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
463 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
464 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
465 [0x0cc] = 0xb5, /* NomV: 3.3 V */
466 [0x0ce] = 0x1e,
467 [0x0d0] = 0x3e, /* Peakl: 350 mA */
468
469 [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
470 [0x0d4] = 0x12, /* Tuple length = 18 bytes */
471 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
472 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
473 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
474 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
475 [0x0de] = 0x55, /* NomV: 5.0 V */
476 [0x0e0] = 0x4d, /* MinV: 4.5 V */
477 [0x0e2] = 0x5d, /* MaxV: 5.5 V */
478 [0x0e4] = 0x4e, /* Peakl: 450 mA */
479 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
480 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
481 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
482 [0x0ec] = 0x01,
483 [0x0ee] = 0x07, /* Address block length = 8 */
484 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
485 [0x0f2] = 0x03,
486 [0x0f4] = 0x01, /* Address block length = 2 */
487 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
488 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
489
490 [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
491 [0x0fc] = 0x06, /* Tuple length = 6 bytes */
492 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
493 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
494 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
495 [0x104] = 0xb5, /* NomV: 3.3 V */
496 [0x106] = 0x1e,
497 [0x108] = 0x3e, /* Peakl: 350 mA */
498
499 [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
500 [0x10c] = 0x12, /* Tuple length = 18 bytes */
501 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
502 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
503 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
504 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
505 [0x116] = 0x55, /* NomV: 5.0 V */
506 [0x118] = 0x4d, /* MinV: 4.5 V */
507 [0x11a] = 0x5d, /* MaxV: 5.5 V */
508 [0x11c] = 0x4e, /* Peakl: 450 mA */
509 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
510 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
511 [0x122] = 0x70, /* Field 1 address = 0x0170 */
512 [0x124] = 0x01,
513 [0x126] = 0x07, /* Address block length = 8 */
514 [0x128] = 0x76, /* Field 2 address = 0x0376 */
515 [0x12a] = 0x03,
516 [0x12c] = 0x01, /* Address block length = 2 */
517 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
518 [0x130] = 0x20, /* TPCE_MI = support power down mode */
519
520 [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
521 [0x134] = 0x06, /* Tuple length = 6 bytes */
522 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
523 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
524 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
525 [0x13c] = 0xb5, /* NomV: 3.3 V */
526 [0x13e] = 0x1e,
527 [0x140] = 0x3e, /* Peakl: 350 mA */
528
529 [0x142] = CISTPL_NO_LINK, /* No Link */
530 [0x144] = 0x00, /* Tuple length = 0 bytes */
531
532 [0x146] = CISTPL_END, /* Tuple End */
533 };
534
535 #define TYPE_DSCM1XXXX "dscm1xxxx"
536
537 static int dscm1xxxx_attach(PCMCIACardState *card)
538 {
539 MicroDriveState *md = MICRODRIVE(card);
540 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
541
542 md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
543 md->io_base = 0x0;
544
545 device_legacy_reset(DEVICE(md));
546 md_interrupt_update(md);
547
548 return 0;
549 }
550
551 static int dscm1xxxx_detach(PCMCIACardState *card)
552 {
553 MicroDriveState *md = MICRODRIVE(card);
554
555 device_legacy_reset(DEVICE(md));
556 return 0;
557 }
558
559 PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
560 {
561 MicroDriveState *md;
562
563 md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
564 qdev_realize(DEVICE(md), NULL, &error_fatal);
565
566 if (dinfo != NULL) {
567 ide_create_drive(&md->bus, 0, dinfo);
568 }
569 md->bus.ifs[0].drive_kind = IDE_CFATA;
570 md->bus.ifs[0].mdata_size = METADATA_SIZE;
571 md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE);
572
573 return PCMCIA_CARD(md);
574 }
575
576 static void dscm1xxxx_class_init(ObjectClass *oc, void *data)
577 {
578 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
579 DeviceClass *dc = DEVICE_CLASS(oc);
580
581 pcc->cis = dscm1xxxx_cis;
582 pcc->cis_len = sizeof(dscm1xxxx_cis);
583
584 pcc->attach = dscm1xxxx_attach;
585 pcc->detach = dscm1xxxx_detach;
586 /* Reason: Needs to be wired-up in code, see dscm1xxxx_init() */
587 dc->user_creatable = false;
588 }
589
590 static const TypeInfo dscm1xxxx_type_info = {
591 .name = TYPE_DSCM1XXXX,
592 .parent = TYPE_MICRODRIVE,
593 .class_init = dscm1xxxx_class_init,
594 };
595
596 static void microdrive_realize(DeviceState *dev, Error **errp)
597 {
598 MicroDriveState *md = MICRODRIVE(dev);
599
600 ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
601 }
602
603 static void microdrive_init(Object *obj)
604 {
605 MicroDriveState *md = MICRODRIVE(obj);
606
607 ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
608 }
609
610 static void microdrive_class_init(ObjectClass *oc, void *data)
611 {
612 DeviceClass *dc = DEVICE_CLASS(oc);
613 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
614
615 pcc->attr_read = md_attr_read;
616 pcc->attr_write = md_attr_write;
617 pcc->common_read = md_common_read;
618 pcc->common_write = md_common_write;
619 pcc->io_read = md_common_read;
620 pcc->io_write = md_common_write;
621
622 dc->realize = microdrive_realize;
623 dc->reset = md_reset;
624 dc->vmsd = &vmstate_microdrive;
625 }
626
627 static const TypeInfo microdrive_type_info = {
628 .name = TYPE_MICRODRIVE,
629 .parent = TYPE_PCMCIA_CARD,
630 .instance_size = sizeof(MicroDriveState),
631 .instance_init = microdrive_init,
632 .abstract = true,
633 .class_init = microdrive_class_init,
634 };
635
636 static void microdrive_register_types(void)
637 {
638 type_register_static(&microdrive_type_info);
639 type_register_static(&dscm1xxxx_type_info);
640 }
641
642 type_init(microdrive_register_types)