pcie_aer: support configurable AER capa version
[qemu.git] / hw / ide / microdrive.c
1 /*
2 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pcmcia.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/dma.h"
31
32 #include "hw/ide/internal.h"
33
34 #define TYPE_MICRODRIVE "microdrive"
35 #define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)
36
37 /***********************************************************/
38 /* CF-ATA Microdrive */
39
40 #define METADATA_SIZE 0x20
41
42 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
43
44 typedef struct MicroDriveState {
45 /*< private >*/
46 PCMCIACardState parent_obj;
47 /*< public >*/
48
49 IDEBus bus;
50 uint32_t attr_base;
51 uint32_t io_base;
52
53 /* Card state */
54 uint8_t opt;
55 uint8_t stat;
56 uint8_t pins;
57
58 uint8_t ctrl;
59 uint16_t io;
60 uint8_t cycle;
61 } MicroDriveState;
62
63 /* Register bitfields */
64 enum md_opt {
65 OPT_MODE_MMAP = 0,
66 OPT_MODE_IOMAP16 = 1,
67 OPT_MODE_IOMAP1 = 2,
68 OPT_MODE_IOMAP2 = 3,
69 OPT_MODE = 0x3f,
70 OPT_LEVIREQ = 0x40,
71 OPT_SRESET = 0x80,
72 };
73 enum md_cstat {
74 STAT_INT = 0x02,
75 STAT_PWRDWN = 0x04,
76 STAT_XE = 0x10,
77 STAT_IOIS8 = 0x20,
78 STAT_SIGCHG = 0x40,
79 STAT_CHANGED = 0x80,
80 };
81 enum md_pins {
82 PINS_MRDY = 0x02,
83 PINS_CRDY = 0x20,
84 };
85 enum md_ctrl {
86 CTRL_IEN = 0x02,
87 CTRL_SRST = 0x04,
88 };
89
90 static inline void md_interrupt_update(MicroDriveState *s)
91 {
92 PCMCIACardState *card = PCMCIA_CARD(s);
93
94 if (card->slot == NULL) {
95 return;
96 }
97
98 qemu_set_irq(card->slot->irq,
99 !(s->stat & STAT_INT) && /* Inverted */
100 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
101 !(s->opt & OPT_SRESET));
102 }
103
104 static void md_set_irq(void *opaque, int irq, int level)
105 {
106 MicroDriveState *s = opaque;
107
108 if (level) {
109 s->stat |= STAT_INT;
110 } else {
111 s->stat &= ~STAT_INT;
112 }
113
114 md_interrupt_update(s);
115 }
116
117 static void md_reset(DeviceState *dev)
118 {
119 MicroDriveState *s = MICRODRIVE(dev);
120
121 s->opt = OPT_MODE_MMAP;
122 s->stat = 0;
123 s->pins = 0;
124 s->cycle = 0;
125 s->ctrl = 0;
126 ide_bus_reset(&s->bus);
127 }
128
129 static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
130 {
131 MicroDriveState *s = MICRODRIVE(card);
132 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
133
134 if (at < s->attr_base) {
135 if (at < pcc->cis_len) {
136 return pcc->cis[at];
137 } else {
138 return 0x00;
139 }
140 }
141
142 at -= s->attr_base;
143
144 switch (at) {
145 case 0x00: /* Configuration Option Register */
146 return s->opt;
147 case 0x02: /* Card Configuration Status Register */
148 if (s->ctrl & CTRL_IEN) {
149 return s->stat & ~STAT_INT;
150 } else {
151 return s->stat;
152 }
153 case 0x04: /* Pin Replacement Register */
154 return (s->pins & PINS_CRDY) | 0x0c;
155 case 0x06: /* Socket and Copy Register */
156 return 0x00;
157 #ifdef VERBOSE
158 default:
159 printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
160 #endif
161 }
162
163 return 0;
164 }
165
166 static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
167 {
168 MicroDriveState *s = MICRODRIVE(card);
169
170 at -= s->attr_base;
171
172 switch (at) {
173 case 0x00: /* Configuration Option Register */
174 s->opt = value & 0xcf;
175 if (value & OPT_SRESET) {
176 device_reset(DEVICE(s));
177 }
178 md_interrupt_update(s);
179 break;
180 case 0x02: /* Card Configuration Status Register */
181 if ((s->stat ^ value) & STAT_PWRDWN) {
182 s->pins |= PINS_CRDY;
183 }
184 s->stat &= 0x82;
185 s->stat |= value & 0x74;
186 md_interrupt_update(s);
187 /* Word 170 in Identify Device must be equal to STAT_XE */
188 break;
189 case 0x04: /* Pin Replacement Register */
190 s->pins &= PINS_CRDY;
191 s->pins |= value & PINS_MRDY;
192 break;
193 case 0x06: /* Socket and Copy Register */
194 break;
195 default:
196 printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
197 }
198 }
199
200 static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
201 {
202 MicroDriveState *s = MICRODRIVE(card);
203 IDEState *ifs;
204 uint16_t ret;
205 at -= s->io_base;
206
207 switch (s->opt & OPT_MODE) {
208 case OPT_MODE_MMAP:
209 if ((at & ~0x3ff) == 0x400) {
210 at = 0;
211 }
212 break;
213 case OPT_MODE_IOMAP16:
214 at &= 0xf;
215 break;
216 case OPT_MODE_IOMAP1:
217 if ((at & ~0xf) == 0x3f0) {
218 at -= 0x3e8;
219 } else if ((at & ~0xf) == 0x1f0) {
220 at -= 0x1f0;
221 }
222 break;
223 case OPT_MODE_IOMAP2:
224 if ((at & ~0xf) == 0x370) {
225 at -= 0x368;
226 } else if ((at & ~0xf) == 0x170) {
227 at -= 0x170;
228 }
229 }
230
231 switch (at) {
232 case 0x0: /* Even RD Data */
233 case 0x8:
234 return ide_data_readw(&s->bus, 0);
235
236 /* TODO: 8-bit accesses */
237 if (s->cycle) {
238 ret = s->io >> 8;
239 } else {
240 s->io = ide_data_readw(&s->bus, 0);
241 ret = s->io & 0xff;
242 }
243 s->cycle = !s->cycle;
244 return ret;
245 case 0x9: /* Odd RD Data */
246 return s->io >> 8;
247 case 0xd: /* Error */
248 return ide_ioport_read(&s->bus, 0x1);
249 case 0xe: /* Alternate Status */
250 ifs = idebus_active_if(&s->bus);
251 if (ifs->blk) {
252 return ifs->status;
253 } else {
254 return 0;
255 }
256 case 0xf: /* Device Address */
257 ifs = idebus_active_if(&s->bus);
258 return 0xc2 | ((~ifs->select << 2) & 0x3c);
259 default:
260 return ide_ioport_read(&s->bus, at);
261 }
262
263 return 0;
264 }
265
266 static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
267 {
268 MicroDriveState *s = MICRODRIVE(card);
269 at -= s->io_base;
270
271 switch (s->opt & OPT_MODE) {
272 case OPT_MODE_MMAP:
273 if ((at & ~0x3ff) == 0x400) {
274 at = 0;
275 }
276 break;
277 case OPT_MODE_IOMAP16:
278 at &= 0xf;
279 break;
280 case OPT_MODE_IOMAP1:
281 if ((at & ~0xf) == 0x3f0) {
282 at -= 0x3e8;
283 } else if ((at & ~0xf) == 0x1f0) {
284 at -= 0x1f0;
285 }
286 break;
287 case OPT_MODE_IOMAP2:
288 if ((at & ~0xf) == 0x370) {
289 at -= 0x368;
290 } else if ((at & ~0xf) == 0x170) {
291 at -= 0x170;
292 }
293 }
294
295 switch (at) {
296 case 0x0: /* Even WR Data */
297 case 0x8:
298 ide_data_writew(&s->bus, 0, value);
299 break;
300
301 /* TODO: 8-bit accesses */
302 if (s->cycle) {
303 ide_data_writew(&s->bus, 0, s->io | (value << 8));
304 } else {
305 s->io = value & 0xff;
306 }
307 s->cycle = !s->cycle;
308 break;
309 case 0x9:
310 s->io = value & 0xff;
311 s->cycle = !s->cycle;
312 break;
313 case 0xd: /* Features */
314 ide_ioport_write(&s->bus, 0x1, value);
315 break;
316 case 0xe: /* Device Control */
317 s->ctrl = value;
318 if (value & CTRL_SRST) {
319 device_reset(DEVICE(s));
320 }
321 md_interrupt_update(s);
322 break;
323 default:
324 if (s->stat & STAT_PWRDWN) {
325 s->pins |= PINS_CRDY;
326 s->stat &= ~STAT_PWRDWN;
327 }
328 ide_ioport_write(&s->bus, at, value);
329 }
330 }
331
332 static const VMStateDescription vmstate_microdrive = {
333 .name = "microdrive",
334 .version_id = 3,
335 .minimum_version_id = 0,
336 .fields = (VMStateField[]) {
337 VMSTATE_UINT8(opt, MicroDriveState),
338 VMSTATE_UINT8(stat, MicroDriveState),
339 VMSTATE_UINT8(pins, MicroDriveState),
340 VMSTATE_UINT8(ctrl, MicroDriveState),
341 VMSTATE_UINT16(io, MicroDriveState),
342 VMSTATE_UINT8(cycle, MicroDriveState),
343 VMSTATE_IDE_BUS(bus, MicroDriveState),
344 VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
345 VMSTATE_END_OF_LIST()
346 }
347 };
348
349 static const uint8_t dscm1xxxx_cis[0x14a] = {
350 [0x000] = CISTPL_DEVICE, /* 5V Device Information */
351 [0x002] = 0x03, /* Tuple length = 4 bytes */
352 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
353 [0x006] = 0x01, /* Size = 2K bytes */
354 [0x008] = CISTPL_ENDMARK,
355
356 [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
357 [0x00c] = 0x04, /* Tuple length = 4 byest */
358 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
359 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
360 [0x012] = 0x01, /* Size = 2K bytes */
361 [0x014] = CISTPL_ENDMARK,
362
363 [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
364 [0x018] = 0x02, /* Tuple length = 2 bytes */
365 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
366 [0x01c] = 0x01,
367
368 [0x01e] = CISTPL_MANFID, /* Manufacture ID */
369 [0x020] = 0x04, /* Tuple length = 4 bytes */
370 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
371 [0x024] = 0x00,
372 [0x026] = 0x00, /* PLMID_CARD = 0000 */
373 [0x028] = 0x00,
374
375 [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
376 [0x02c] = 0x12, /* Tuple length = 23 bytes */
377 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
378 [0x030] = 0x01, /* Minor Version = 1 */
379 [0x032] = 'I',
380 [0x034] = 'B',
381 [0x036] = 'M',
382 [0x038] = 0x00,
383 [0x03a] = 'm',
384 [0x03c] = 'i',
385 [0x03e] = 'c',
386 [0x040] = 'r',
387 [0x042] = 'o',
388 [0x044] = 'd',
389 [0x046] = 'r',
390 [0x048] = 'i',
391 [0x04a] = 'v',
392 [0x04c] = 'e',
393 [0x04e] = 0x00,
394 [0x050] = CISTPL_ENDMARK,
395
396 [0x052] = CISTPL_FUNCID, /* Function ID */
397 [0x054] = 0x02, /* Tuple length = 2 bytes */
398 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
399 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
400
401 [0x05a] = CISTPL_FUNCE, /* Function Extension */
402 [0x05c] = 0x02, /* Tuple length = 2 bytes */
403 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
404 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
405
406 [0x062] = CISTPL_FUNCE, /* Function Extension */
407 [0x064] = 0x03, /* Tuple length = 3 bytes */
408 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
409 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
410 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
411
412 [0x06c] = CISTPL_CONFIG, /* Configuration */
413 [0x06e] = 0x05, /* Tuple length = 5 bytes */
414 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
415 [0x072] = 0x07, /* TPCC_LAST = 7 */
416 [0x074] = 0x00, /* TPCC_RADR = 0200 */
417 [0x076] = 0x02,
418 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
419
420 [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
421 [0x07c] = 0x0b, /* Tuple length = 11 bytes */
422 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
423 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
424 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
425 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
426 [0x086] = 0x55, /* NomV: 5.0 V */
427 [0x088] = 0x4d, /* MinV: 4.5 V */
428 [0x08a] = 0x5d, /* MaxV: 5.5 V */
429 [0x08c] = 0x4e, /* Peakl: 450 mA */
430 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
431 [0x090] = 0x00, /* Window descriptor: Window length = 0 */
432 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
433
434 [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
435 [0x096] = 0x06, /* Tuple length = 6 bytes */
436 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
437 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
438 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
439 [0x09e] = 0xb5, /* NomV: 3.3 V */
440 [0x0a0] = 0x1e,
441 [0x0a2] = 0x3e, /* Peakl: 350 mA */
442
443 [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
444 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
445 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
446 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
447 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
448 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
449 [0x0b0] = 0x55, /* NomV: 5.0 V */
450 [0x0b2] = 0x4d, /* MinV: 4.5 V */
451 [0x0b4] = 0x5d, /* MaxV: 5.5 V */
452 [0x0b6] = 0x4e, /* Peakl: 450 mA */
453 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
454 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
455 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
456 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
457 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
458
459 [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
460 [0x0c4] = 0x06, /* Tuple length = 6 bytes */
461 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
462 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
463 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
464 [0x0cc] = 0xb5, /* NomV: 3.3 V */
465 [0x0ce] = 0x1e,
466 [0x0d0] = 0x3e, /* Peakl: 350 mA */
467
468 [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
469 [0x0d4] = 0x12, /* Tuple length = 18 bytes */
470 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
471 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
472 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
473 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
474 [0x0de] = 0x55, /* NomV: 5.0 V */
475 [0x0e0] = 0x4d, /* MinV: 4.5 V */
476 [0x0e2] = 0x5d, /* MaxV: 5.5 V */
477 [0x0e4] = 0x4e, /* Peakl: 450 mA */
478 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
479 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
480 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
481 [0x0ec] = 0x01,
482 [0x0ee] = 0x07, /* Address block length = 8 */
483 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
484 [0x0f2] = 0x03,
485 [0x0f4] = 0x01, /* Address block length = 2 */
486 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
487 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
488
489 [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
490 [0x0fc] = 0x06, /* Tuple length = 6 bytes */
491 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
492 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
493 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
494 [0x104] = 0xb5, /* NomV: 3.3 V */
495 [0x106] = 0x1e,
496 [0x108] = 0x3e, /* Peakl: 350 mA */
497
498 [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
499 [0x10c] = 0x12, /* Tuple length = 18 bytes */
500 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
501 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
502 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
503 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
504 [0x116] = 0x55, /* NomV: 5.0 V */
505 [0x118] = 0x4d, /* MinV: 4.5 V */
506 [0x11a] = 0x5d, /* MaxV: 5.5 V */
507 [0x11c] = 0x4e, /* Peakl: 450 mA */
508 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
509 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
510 [0x122] = 0x70, /* Field 1 address = 0x0170 */
511 [0x124] = 0x01,
512 [0x126] = 0x07, /* Address block length = 8 */
513 [0x128] = 0x76, /* Field 2 address = 0x0376 */
514 [0x12a] = 0x03,
515 [0x12c] = 0x01, /* Address block length = 2 */
516 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
517 [0x130] = 0x20, /* TPCE_MI = support power down mode */
518
519 [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
520 [0x134] = 0x06, /* Tuple length = 6 bytes */
521 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
522 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
523 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
524 [0x13c] = 0xb5, /* NomV: 3.3 V */
525 [0x13e] = 0x1e,
526 [0x140] = 0x3e, /* Peakl: 350 mA */
527
528 [0x142] = CISTPL_NO_LINK, /* No Link */
529 [0x144] = 0x00, /* Tuple length = 0 bytes */
530
531 [0x146] = CISTPL_END, /* Tuple End */
532 };
533
534 #define TYPE_DSCM1XXXX "dscm1xxxx"
535
536 static int dscm1xxxx_attach(PCMCIACardState *card)
537 {
538 MicroDriveState *md = MICRODRIVE(card);
539 PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
540
541 md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
542 md->io_base = 0x0;
543
544 device_reset(DEVICE(md));
545 md_interrupt_update(md);
546
547 return 0;
548 }
549
550 static int dscm1xxxx_detach(PCMCIACardState *card)
551 {
552 MicroDriveState *md = MICRODRIVE(card);
553
554 device_reset(DEVICE(md));
555 return 0;
556 }
557
558 PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
559 {
560 MicroDriveState *md;
561
562 md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
563 qdev_init_nofail(DEVICE(md));
564
565 if (dinfo != NULL) {
566 ide_create_drive(&md->bus, 0, dinfo);
567 }
568 md->bus.ifs[0].drive_kind = IDE_CFATA;
569 md->bus.ifs[0].mdata_size = METADATA_SIZE;
570 md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE);
571
572 return PCMCIA_CARD(md);
573 }
574
575 static void dscm1xxxx_class_init(ObjectClass *oc, void *data)
576 {
577 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
578
579 pcc->cis = dscm1xxxx_cis;
580 pcc->cis_len = sizeof(dscm1xxxx_cis);
581
582 pcc->attach = dscm1xxxx_attach;
583 pcc->detach = dscm1xxxx_detach;
584 }
585
586 static const TypeInfo dscm1xxxx_type_info = {
587 .name = TYPE_DSCM1XXXX,
588 .parent = TYPE_MICRODRIVE,
589 .class_init = dscm1xxxx_class_init,
590 };
591
592 static void microdrive_realize(DeviceState *dev, Error **errp)
593 {
594 MicroDriveState *md = MICRODRIVE(dev);
595
596 ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
597 }
598
599 static void microdrive_init(Object *obj)
600 {
601 MicroDriveState *md = MICRODRIVE(obj);
602
603 ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
604 }
605
606 static void microdrive_class_init(ObjectClass *oc, void *data)
607 {
608 DeviceClass *dc = DEVICE_CLASS(oc);
609 PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
610
611 pcc->attr_read = md_attr_read;
612 pcc->attr_write = md_attr_write;
613 pcc->common_read = md_common_read;
614 pcc->common_write = md_common_write;
615 pcc->io_read = md_common_read;
616 pcc->io_write = md_common_write;
617
618 dc->realize = microdrive_realize;
619 dc->reset = md_reset;
620 dc->vmsd = &vmstate_microdrive;
621 }
622
623 static const TypeInfo microdrive_type_info = {
624 .name = TYPE_MICRODRIVE,
625 .parent = TYPE_PCMCIA_CARD,
626 .instance_size = sizeof(MicroDriveState),
627 .instance_init = microdrive_init,
628 .abstract = true,
629 .class_init = microdrive_class_init,
630 };
631
632 static void microdrive_register_types(void)
633 {
634 type_register_static(&microdrive_type_info);
635 type_register_static(&dscm1xxxx_type_info);
636 }
637
638 type_init(microdrive_register_types)