pcie_aer: support configurable AER capa version
[qemu.git] / hw / ide / piix.c
1 /*
2 * QEMU IDE Emulation: PCI PIIX3/4 support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/hw.h"
28 #include "hw/i386/pc.h"
29 #include "hw/pci/pci.h"
30 #include "hw/isa/isa.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/dma.h"
34
35 #include "hw/ide/pci.h"
36
37 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
38 {
39 BMDMAState *bm = opaque;
40 uint32_t val;
41
42 if (size != 1) {
43 return ((uint64_t)1 << (size * 8)) - 1;
44 }
45
46 switch(addr & 3) {
47 case 0:
48 val = bm->cmd;
49 break;
50 case 2:
51 val = bm->status;
52 break;
53 default:
54 val = 0xff;
55 break;
56 }
57 #ifdef DEBUG_IDE
58 printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
59 #endif
60 return val;
61 }
62
63 static void bmdma_write(void *opaque, hwaddr addr,
64 uint64_t val, unsigned size)
65 {
66 BMDMAState *bm = opaque;
67
68 if (size != 1) {
69 return;
70 }
71
72 #ifdef DEBUG_IDE
73 printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
74 #endif
75 switch(addr & 3) {
76 case 0:
77 bmdma_cmd_writeb(bm, val);
78 break;
79 case 2:
80 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
81 break;
82 }
83 }
84
85 static const MemoryRegionOps piix_bmdma_ops = {
86 .read = bmdma_read,
87 .write = bmdma_write,
88 };
89
90 static void bmdma_setup_bar(PCIIDEState *d)
91 {
92 int i;
93
94 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
95 for(i = 0;i < 2; i++) {
96 BMDMAState *bm = &d->bmdma[i];
97
98 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
99 "piix-bmdma", 4);
100 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
101 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
102 &bmdma_addr_ioport_ops, bm, "bmdma", 4);
103 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
104 }
105 }
106
107 static void piix3_reset(void *opaque)
108 {
109 PCIIDEState *d = opaque;
110 PCIDevice *pd = PCI_DEVICE(d);
111 uint8_t *pci_conf = pd->config;
112 int i;
113
114 for (i = 0; i < 2; i++) {
115 ide_bus_reset(&d->bus[i]);
116 }
117
118 /* TODO: this is the default. do not override. */
119 pci_conf[PCI_COMMAND] = 0x00;
120 /* TODO: this is the default. do not override. */
121 pci_conf[PCI_COMMAND + 1] = 0x00;
122 /* TODO: use pci_set_word */
123 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
124 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
125 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
126 }
127
128 static void pci_piix_init_ports(PCIIDEState *d) {
129 static const struct {
130 int iobase;
131 int iobase2;
132 int isairq;
133 } port_info[] = {
134 {0x1f0, 0x3f6, 14},
135 {0x170, 0x376, 15},
136 };
137 int i;
138
139 for (i = 0; i < 2; i++) {
140 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
141 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
142 port_info[i].iobase2);
143 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
144
145 bmdma_init(&d->bus[i], &d->bmdma[i], d);
146 d->bmdma[i].bus = &d->bus[i];
147 ide_register_restart_cb(&d->bus[i]);
148 }
149 }
150
151 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
152 {
153 PCIIDEState *d = PCI_IDE(dev);
154 uint8_t *pci_conf = dev->config;
155
156 pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
157
158 qemu_register_reset(piix3_reset, d);
159
160 bmdma_setup_bar(d);
161 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
162
163 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
164
165 pci_piix_init_ports(d);
166 }
167
168 int pci_piix3_xen_ide_unplug(DeviceState *dev)
169 {
170 PCIIDEState *pci_ide;
171 DriveInfo *di;
172 int i;
173 IDEDevice *idedev;
174
175 pci_ide = PCI_IDE(dev);
176
177 for (i = 0; i < 4; i++) {
178 di = drive_get_by_index(IF_IDE, i);
179 if (di != NULL && !di->media_cd) {
180 BlockBackend *blk = blk_by_legacy_dinfo(di);
181 DeviceState *ds = blk_get_attached_dev(blk);
182
183 blk_drain(blk);
184 blk_flush(blk);
185
186 if (ds) {
187 blk_detach_dev(blk, ds);
188 }
189 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL;
190 if (!(i % 2)) {
191 idedev = pci_ide->bus[di->bus].master;
192 } else {
193 idedev = pci_ide->bus[di->bus].slave;
194 }
195 idedev->conf.blk = NULL;
196 monitor_remove_blk(blk);
197 blk_unref(blk);
198 }
199 }
200 qdev_reset_all(DEVICE(dev));
201 return 0;
202 }
203
204 PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
205 {
206 PCIDevice *dev;
207
208 dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
209 pci_ide_create_devs(dev, hd_table);
210 return dev;
211 }
212
213 static void pci_piix_ide_exitfn(PCIDevice *dev)
214 {
215 PCIIDEState *d = PCI_IDE(dev);
216 unsigned i;
217
218 for (i = 0; i < 2; ++i) {
219 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
220 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
221 }
222 }
223
224 /* hd_table must contain 4 block drivers */
225 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
226 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
227 {
228 PCIDevice *dev;
229
230 dev = pci_create_simple(bus, devfn, "piix3-ide");
231 pci_ide_create_devs(dev, hd_table);
232 return dev;
233 }
234
235 /* hd_table must contain 4 block drivers */
236 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
237 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
238 {
239 PCIDevice *dev;
240
241 dev = pci_create_simple(bus, devfn, "piix4-ide");
242 pci_ide_create_devs(dev, hd_table);
243 return dev;
244 }
245
246 static void piix3_ide_class_init(ObjectClass *klass, void *data)
247 {
248 DeviceClass *dc = DEVICE_CLASS(klass);
249 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
250
251 k->realize = pci_piix_ide_realize;
252 k->exit = pci_piix_ide_exitfn;
253 k->vendor_id = PCI_VENDOR_ID_INTEL;
254 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
255 k->class_id = PCI_CLASS_STORAGE_IDE;
256 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
257 dc->hotpluggable = false;
258 }
259
260 static const TypeInfo piix3_ide_info = {
261 .name = "piix3-ide",
262 .parent = TYPE_PCI_IDE,
263 .class_init = piix3_ide_class_init,
264 };
265
266 static const TypeInfo piix3_ide_xen_info = {
267 .name = "piix3-ide-xen",
268 .parent = TYPE_PCI_IDE,
269 .class_init = piix3_ide_class_init,
270 };
271
272 static void piix4_ide_class_init(ObjectClass *klass, void *data)
273 {
274 DeviceClass *dc = DEVICE_CLASS(klass);
275 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
276
277 k->realize = pci_piix_ide_realize;
278 k->exit = pci_piix_ide_exitfn;
279 k->vendor_id = PCI_VENDOR_ID_INTEL;
280 k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
281 k->class_id = PCI_CLASS_STORAGE_IDE;
282 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
283 dc->hotpluggable = false;
284 }
285
286 static const TypeInfo piix4_ide_info = {
287 .name = "piix4-ide",
288 .parent = TYPE_PCI_IDE,
289 .class_init = piix4_ide_class_init,
290 };
291
292 static void piix_ide_register_types(void)
293 {
294 type_register_static(&piix3_ide_info);
295 type_register_static(&piix3_ide_xen_info);
296 type_register_static(&piix4_ide_info);
297 }
298
299 type_init(piix_ide_register_types)