misc: Fix typos in comments
[qemu.git] / hw / intc / arm_gic_kvm.c
1 /*
2 * ARM Generic Interrupt Controller using KVM in-kernel support
3 *
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
6 * Save/Restore logic added by Christoffer Dall.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "hw/sysbus.h"
23 #include "sysemu/kvm.h"
24 #include "kvm_arm.h"
25 #include "gic_internal.h"
26
27 //#define DEBUG_GIC_KVM
28
29 #ifdef DEBUG_GIC_KVM
30 static const int debug_gic_kvm = 1;
31 #else
32 static const int debug_gic_kvm = 0;
33 #endif
34
35 #define DPRINTF(fmt, ...) do { \
36 if (debug_gic_kvm) { \
37 printf("arm_gic: " fmt , ## __VA_ARGS__); \
38 } \
39 } while (0)
40
41 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
42 #define KVM_ARM_GIC(obj) \
43 OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
44 #define KVM_ARM_GIC_CLASS(klass) \
45 OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
46 #define KVM_ARM_GIC_GET_CLASS(obj) \
47 OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
48
49 typedef struct KVMARMGICClass {
50 ARMGICCommonClass parent_class;
51 DeviceRealize parent_realize;
52 void (*parent_reset)(DeviceState *dev);
53 } KVMARMGICClass;
54
55 static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
56 {
57 /* Meaning of the 'irq' parameter:
58 * [0..N-1] : external interrupts
59 * [N..N+31] : PPI (internal) interrupts for CPU 0
60 * [N+32..N+63] : PPI (internal interrupts for CPU 1
61 * ...
62 * Convert this to the kernel's desired encoding, which
63 * has separate fields in the irq number for type,
64 * CPU number and interrupt number.
65 */
66 GICState *s = (GICState *)opaque;
67 int kvm_irq, irqtype, cpu;
68
69 if (irq < (s->num_irq - GIC_INTERNAL)) {
70 /* External interrupt. The kernel numbers these like the GIC
71 * hardware, with external interrupt IDs starting after the
72 * internal ones.
73 */
74 irqtype = KVM_ARM_IRQ_TYPE_SPI;
75 cpu = 0;
76 irq += GIC_INTERNAL;
77 } else {
78 /* Internal interrupt: decode into (cpu, interrupt id) */
79 irqtype = KVM_ARM_IRQ_TYPE_PPI;
80 irq -= (s->num_irq - GIC_INTERNAL);
81 cpu = irq / GIC_INTERNAL;
82 irq %= GIC_INTERNAL;
83 }
84 kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
85 | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
86
87 kvm_set_irq(kvm_state, kvm_irq, !!level);
88 }
89
90 static bool kvm_arm_gic_can_save_restore(GICState *s)
91 {
92 return s->dev_fd >= 0;
93 }
94
95 static void kvm_gic_access(GICState *s, int group, int offset,
96 int cpu, uint32_t *val, bool write)
97 {
98 struct kvm_device_attr attr;
99 int type;
100 int err;
101
102 cpu = cpu & 0xff;
103
104 attr.flags = 0;
105 attr.group = group;
106 attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &
107 KVM_DEV_ARM_VGIC_CPUID_MASK) |
108 (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
109 KVM_DEV_ARM_VGIC_OFFSET_MASK);
110 attr.addr = (uintptr_t)val;
111
112 if (write) {
113 type = KVM_SET_DEVICE_ATTR;
114 } else {
115 type = KVM_GET_DEVICE_ATTR;
116 }
117
118 err = kvm_device_ioctl(s->dev_fd, type, &attr);
119 if (err < 0) {
120 fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
121 strerror(-err));
122 abort();
123 }
124 }
125
126 static void kvm_gicd_access(GICState *s, int offset, int cpu,
127 uint32_t *val, bool write)
128 {
129 kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
130 offset, cpu, val, write);
131 }
132
133 static void kvm_gicc_access(GICState *s, int offset, int cpu,
134 uint32_t *val, bool write)
135 {
136 kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
137 offset, cpu, val, write);
138 }
139
140 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
141 for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
142
143 /*
144 * Translate from the in-kernel field for an IRQ value to/from the qemu
145 * representation.
146 */
147 typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
148 uint32_t *field, bool to_kernel);
149
150 /* synthetic translate function used for clear/set registers to completely
151 * clear a setting using a clear-register before setting the remaining bits
152 * using a set-register */
153 static void translate_clear(GICState *s, int irq, int cpu,
154 uint32_t *field, bool to_kernel)
155 {
156 if (to_kernel) {
157 *field = ~0;
158 } else {
159 /* does not make sense: qemu model doesn't use set/clear regs */
160 abort();
161 }
162 }
163
164 static void translate_enabled(GICState *s, int irq, int cpu,
165 uint32_t *field, bool to_kernel)
166 {
167 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
168
169 if (to_kernel) {
170 *field = GIC_TEST_ENABLED(irq, cm);
171 } else {
172 if (*field & 1) {
173 GIC_SET_ENABLED(irq, cm);
174 }
175 }
176 }
177
178 static void translate_pending(GICState *s, int irq, int cpu,
179 uint32_t *field, bool to_kernel)
180 {
181 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
182
183 if (to_kernel) {
184 *field = gic_test_pending(s, irq, cm);
185 } else {
186 if (*field & 1) {
187 GIC_SET_PENDING(irq, cm);
188 /* TODO: Capture is level-line is held high in the kernel */
189 }
190 }
191 }
192
193 static void translate_active(GICState *s, int irq, int cpu,
194 uint32_t *field, bool to_kernel)
195 {
196 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
197
198 if (to_kernel) {
199 *field = GIC_TEST_ACTIVE(irq, cm);
200 } else {
201 if (*field & 1) {
202 GIC_SET_ACTIVE(irq, cm);
203 }
204 }
205 }
206
207 static void translate_trigger(GICState *s, int irq, int cpu,
208 uint32_t *field, bool to_kernel)
209 {
210 if (to_kernel) {
211 *field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
212 } else {
213 if (*field & 0x2) {
214 GIC_SET_EDGE_TRIGGER(irq);
215 }
216 }
217 }
218
219 static void translate_priority(GICState *s, int irq, int cpu,
220 uint32_t *field, bool to_kernel)
221 {
222 if (to_kernel) {
223 *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
224 } else {
225 gic_set_priority(s, cpu, irq, *field & 0xff);
226 }
227 }
228
229 static void translate_targets(GICState *s, int irq, int cpu,
230 uint32_t *field, bool to_kernel)
231 {
232 if (to_kernel) {
233 *field = s->irq_target[irq] & 0xff;
234 } else {
235 s->irq_target[irq] = *field & 0xff;
236 }
237 }
238
239 static void translate_sgisource(GICState *s, int irq, int cpu,
240 uint32_t *field, bool to_kernel)
241 {
242 if (to_kernel) {
243 *field = s->sgi_pending[irq][cpu] & 0xff;
244 } else {
245 s->sgi_pending[irq][cpu] = *field & 0xff;
246 }
247 }
248
249 /* Read a register group from the kernel VGIC */
250 static void kvm_dist_get(GICState *s, uint32_t offset, int width,
251 int maxirq, vgic_translate_fn translate_fn)
252 {
253 uint32_t reg;
254 int i;
255 int j;
256 int irq;
257 int cpu;
258 int regsz = 32 / width; /* irqs per kernel register */
259 uint32_t field;
260
261 for_each_irq_reg(i, maxirq, width) {
262 irq = i * regsz;
263 cpu = 0;
264 while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
265 kvm_gicd_access(s, offset, cpu, &reg, false);
266 for (j = 0; j < regsz; j++) {
267 field = extract32(reg, j * width, width);
268 translate_fn(s, irq + j, cpu, &field, false);
269 }
270
271 cpu++;
272 }
273 offset += 4;
274 }
275 }
276
277 /* Write a register group to the kernel VGIC */
278 static void kvm_dist_put(GICState *s, uint32_t offset, int width,
279 int maxirq, vgic_translate_fn translate_fn)
280 {
281 uint32_t reg;
282 int i;
283 int j;
284 int irq;
285 int cpu;
286 int regsz = 32 / width; /* irqs per kernel register */
287 uint32_t field;
288
289 for_each_irq_reg(i, maxirq, width) {
290 irq = i * regsz;
291 cpu = 0;
292 while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
293 reg = 0;
294 for (j = 0; j < regsz; j++) {
295 translate_fn(s, irq + j, cpu, &field, true);
296 reg = deposit32(reg, j * width, width, field);
297 }
298 kvm_gicd_access(s, offset, cpu, &reg, true);
299
300 cpu++;
301 }
302 offset += 4;
303 }
304 }
305
306 static void kvm_arm_gic_put(GICState *s)
307 {
308 uint32_t reg;
309 int i;
310 int cpu;
311 int num_cpu;
312 int num_irq;
313
314 if (!kvm_arm_gic_can_save_restore(s)) {
315 DPRINTF("Cannot put kernel gic state, no kernel interface");
316 return;
317 }
318
319 /* Note: We do the restore in a slightly different order than the save
320 * (where the order doesn't matter and is simply ordered according to the
321 * register offset values */
322
323 /*****************************************************************
324 * Distributor State
325 */
326
327 /* s->enabled -> GICD_CTLR */
328 reg = s->enabled;
329 kvm_gicd_access(s, 0x0, 0, &reg, true);
330
331 /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
332 kvm_gicd_access(s, 0x4, 0, &reg, false);
333 num_irq = ((reg & 0x1f) + 1) * 32;
334 num_cpu = ((reg & 0xe0) >> 5) + 1;
335
336 if (num_irq < s->num_irq) {
337 fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
338 s->num_irq, num_irq);
339 abort();
340 } else if (num_cpu != s->num_cpu) {
341 fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
342 s->num_cpu, num_cpu);
343 /* Did we not create the VCPUs in the kernel yet? */
344 abort();
345 }
346
347 /* TODO: Consider checking compatibility with the IIDR ? */
348
349 /* irq_state[n].enabled -> GICD_ISENABLERn */
350 kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
351 kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
352
353 /* s->irq_target[irq] -> GICD_ITARGETSRn
354 * (restore targets before pending to ensure the pending state is set on
355 * the appropriate CPU interfaces in the kernel) */
356 kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
357
358 /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
359 kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
360 kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
361
362 /* irq_state[n].active -> GICD_ISACTIVERn */
363 kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
364 kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
365
366 /* irq_state[n].trigger -> GICD_ICFRn */
367 kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
368
369 /* s->priorityX[irq] -> ICD_IPRIORITYRn */
370 kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
371
372 /* s->sgi_pending -> ICD_CPENDSGIRn */
373 kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
374 kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
375
376
377 /*****************************************************************
378 * CPU Interface(s) State
379 */
380
381 for (cpu = 0; cpu < s->num_cpu; cpu++) {
382 /* s->cpu_enabled[cpu] -> GICC_CTLR */
383 reg = s->cpu_enabled[cpu];
384 kvm_gicc_access(s, 0x00, cpu, &reg, true);
385
386 /* s->priority_mask[cpu] -> GICC_PMR */
387 reg = (s->priority_mask[cpu] & 0xff);
388 kvm_gicc_access(s, 0x04, cpu, &reg, true);
389
390 /* s->bpr[cpu] -> GICC_BPR */
391 reg = (s->bpr[cpu] & 0x7);
392 kvm_gicc_access(s, 0x08, cpu, &reg, true);
393
394 /* s->abpr[cpu] -> GICC_ABPR */
395 reg = (s->abpr[cpu] & 0x7);
396 kvm_gicc_access(s, 0x1c, cpu, &reg, true);
397
398 /* s->apr[n][cpu] -> GICC_APRn */
399 for (i = 0; i < 4; i++) {
400 reg = s->apr[i][cpu];
401 kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
402 }
403 }
404 }
405
406 static void kvm_arm_gic_get(GICState *s)
407 {
408 uint32_t reg;
409 int i;
410 int cpu;
411
412 if (!kvm_arm_gic_can_save_restore(s)) {
413 DPRINTF("Cannot get kernel gic state, no kernel interface");
414 return;
415 }
416
417 /*****************************************************************
418 * Distributor State
419 */
420
421 /* GICD_CTLR -> s->enabled */
422 kvm_gicd_access(s, 0x0, 0, &reg, false);
423 s->enabled = reg & 1;
424
425 /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
426 kvm_gicd_access(s, 0x4, 0, &reg, false);
427 s->num_irq = ((reg & 0x1f) + 1) * 32;
428 s->num_cpu = ((reg & 0xe0) >> 5) + 1;
429
430 if (s->num_irq > GIC_MAXIRQ) {
431 fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
432 s->num_irq);
433 abort();
434 }
435
436 /* GICD_IIDR -> ? */
437 kvm_gicd_access(s, 0x8, 0, &reg, false);
438
439 /* Verify no GROUP 1 interrupts configured in the kernel */
440 for_each_irq_reg(i, s->num_irq, 1) {
441 kvm_gicd_access(s, 0x80 + (i * 4), 0, &reg, false);
442 if (reg != 0) {
443 fprintf(stderr, "Unsupported GICD_IGROUPRn value: %08x\n",
444 reg);
445 abort();
446 }
447 }
448
449 /* Clear all the IRQ settings */
450 for (i = 0; i < s->num_irq; i++) {
451 memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
452 }
453
454 /* GICD_ISENABLERn -> irq_state[n].enabled */
455 kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
456
457 /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
458 kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
459
460 /* GICD_ISACTIVERn -> irq_state[n].active */
461 kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
462
463 /* GICD_ICFRn -> irq_state[n].trigger */
464 kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
465
466 /* GICD_IPRIORITYRn -> s->priorityX[irq] */
467 kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
468
469 /* GICD_ITARGETSRn -> s->irq_target[irq] */
470 kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
471
472 /* GICD_CPENDSGIRn -> s->sgi_pending */
473 kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
474
475
476 /*****************************************************************
477 * CPU Interface(s) State
478 */
479
480 for (cpu = 0; cpu < s->num_cpu; cpu++) {
481 /* GICC_CTLR -> s->cpu_enabled[cpu] */
482 kvm_gicc_access(s, 0x00, cpu, &reg, false);
483 s->cpu_enabled[cpu] = (reg & 1);
484
485 /* GICC_PMR -> s->priority_mask[cpu] */
486 kvm_gicc_access(s, 0x04, cpu, &reg, false);
487 s->priority_mask[cpu] = (reg & 0xff);
488
489 /* GICC_BPR -> s->bpr[cpu] */
490 kvm_gicc_access(s, 0x08, cpu, &reg, false);
491 s->bpr[cpu] = (reg & 0x7);
492
493 /* GICC_ABPR -> s->abpr[cpu] */
494 kvm_gicc_access(s, 0x1c, cpu, &reg, false);
495 s->abpr[cpu] = (reg & 0x7);
496
497 /* GICC_APRn -> s->apr[n][cpu] */
498 for (i = 0; i < 4; i++) {
499 kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
500 s->apr[i][cpu] = reg;
501 }
502 }
503 }
504
505 static void kvm_arm_gic_reset(DeviceState *dev)
506 {
507 GICState *s = ARM_GIC_COMMON(dev);
508 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
509
510 kgc->parent_reset(dev);
511 kvm_arm_gic_put(s);
512 }
513
514 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
515 {
516 int i;
517 GICState *s = KVM_ARM_GIC(dev);
518 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
519 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
520 int ret;
521
522 kgc->parent_realize(dev, errp);
523 if (error_is_set(errp)) {
524 return;
525 }
526
527 i = s->num_irq - GIC_INTERNAL;
528 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
529 * GPIO array layout is thus:
530 * [0..N-1] SPIs
531 * [N..N+31] PPIs for CPU 0
532 * [N+32..N+63] PPIs for CPU 1
533 * ...
534 */
535 i += (GIC_INTERNAL * s->num_cpu);
536 qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i);
537 /* We never use our outbound IRQ lines but provide them so that
538 * we maintain the same interface as the non-KVM GIC.
539 */
540 for (i = 0; i < s->num_cpu; i++) {
541 sysbus_init_irq(sbd, &s->parent_irq[i]);
542 }
543
544 /* Try to create the device via the device control API */
545 s->dev_fd = -1;
546 ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
547 if (ret >= 0) {
548 s->dev_fd = ret;
549 } else if (ret != -ENODEV && ret != -ENOTSUP) {
550 error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
551 return;
552 }
553
554 /* Distributor */
555 memory_region_init_reservation(&s->iomem, OBJECT(s),
556 "kvm-gic_dist", 0x1000);
557 sysbus_init_mmio(sbd, &s->iomem);
558 kvm_arm_register_device(&s->iomem,
559 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
560 | KVM_VGIC_V2_ADDR_TYPE_DIST,
561 KVM_DEV_ARM_VGIC_GRP_ADDR,
562 KVM_VGIC_V2_ADDR_TYPE_DIST,
563 s->dev_fd);
564 /* CPU interface for current core. Unlike arm_gic, we don't
565 * provide the "interface for core #N" memory regions, because
566 * cores with a VGIC don't have those.
567 */
568 memory_region_init_reservation(&s->cpuiomem[0], OBJECT(s),
569 "kvm-gic_cpu", 0x1000);
570 sysbus_init_mmio(sbd, &s->cpuiomem[0]);
571 kvm_arm_register_device(&s->cpuiomem[0],
572 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
573 | KVM_VGIC_V2_ADDR_TYPE_CPU,
574 KVM_DEV_ARM_VGIC_GRP_ADDR,
575 KVM_VGIC_V2_ADDR_TYPE_CPU,
576 s->dev_fd);
577 }
578
579 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
580 {
581 DeviceClass *dc = DEVICE_CLASS(klass);
582 ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
583 KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
584
585 agcc->pre_save = kvm_arm_gic_get;
586 agcc->post_load = kvm_arm_gic_put;
587 kgc->parent_realize = dc->realize;
588 kgc->parent_reset = dc->reset;
589 dc->realize = kvm_arm_gic_realize;
590 dc->reset = kvm_arm_gic_reset;
591 }
592
593 static const TypeInfo kvm_arm_gic_info = {
594 .name = TYPE_KVM_ARM_GIC,
595 .parent = TYPE_ARM_GIC_COMMON,
596 .instance_size = sizeof(GICState),
597 .class_init = kvm_arm_gic_class_init,
598 .class_size = sizeof(KVMARMGICClass),
599 };
600
601 static void kvm_arm_gic_register_types(void)
602 {
603 type_register_static(&kvm_arm_gic_info);
604 }
605
606 type_init(kvm_arm_gic_register_types)