ppc/xics: add a realize() handler to ICPStateClass
[qemu.git] / hw / intc / xics.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
31 #include "cpu.h"
32 #include "hw/hw.h"
33 #include "trace.h"
34 #include "qemu/timer.h"
35 #include "hw/ppc/xics.h"
36 #include "qemu/error-report.h"
37 #include "qapi/visitor.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
40
41 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
42 {
43 CPUState *cs = CPU(cpu);
44 ICPState *icp = ICP(cpu->intc);
45
46 assert(icp);
47 assert(cs == icp->cs);
48
49 icp->output = NULL;
50 icp->cs = NULL;
51 }
52
53 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp)
54 {
55 CPUState *cs = CPU(cpu);
56 CPUPPCState *env = &cpu->env;
57 ICPStateClass *icpc;
58
59 assert(icp);
60
61 cpu->intc = OBJECT(icp);
62 icp->cs = cs;
63
64 icpc = ICP_GET_CLASS(icp);
65 if (icpc->cpu_setup) {
66 icpc->cpu_setup(icp, cpu);
67 }
68
69 switch (PPC_INPUT(env)) {
70 case PPC_FLAGS_INPUT_POWER7:
71 icp->output = env->irq_inputs[POWER7_INPUT_INT];
72 break;
73
74 case PPC_FLAGS_INPUT_970:
75 icp->output = env->irq_inputs[PPC970_INPUT_INT];
76 break;
77
78 default:
79 error_report("XICS interrupt controller does not support this CPU "
80 "bus model");
81 abort();
82 }
83 }
84
85 void icp_pic_print_info(ICPState *icp, Monitor *mon)
86 {
87 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
88
89 if (!icp->output) {
90 return;
91 }
92 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
93 cpu_index, icp->xirr, icp->xirr_owner,
94 icp->pending_priority, icp->mfrr);
95 }
96
97 void ics_pic_print_info(ICSState *ics, Monitor *mon)
98 {
99 uint32_t i;
100
101 monitor_printf(mon, "ICS %4x..%4x %p\n",
102 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
103
104 if (!ics->irqs) {
105 return;
106 }
107
108 for (i = 0; i < ics->nr_irqs; i++) {
109 ICSIRQState *irq = ics->irqs + i;
110
111 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
112 continue;
113 }
114 monitor_printf(mon, " %4x %s %02x %02x\n",
115 ics->offset + i,
116 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
117 "LSI" : "MSI",
118 irq->priority, irq->status);
119 }
120 }
121
122 /*
123 * ICP: Presentation layer
124 */
125
126 #define XISR_MASK 0x00ffffff
127 #define CPPR_MASK 0xff000000
128
129 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
130 #define CPPR(icp) (((icp)->xirr) >> 24)
131
132 static void ics_reject(ICSState *ics, uint32_t nr)
133 {
134 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
135
136 if (k->reject) {
137 k->reject(ics, nr);
138 }
139 }
140
141 void ics_resend(ICSState *ics)
142 {
143 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
144
145 if (k->resend) {
146 k->resend(ics);
147 }
148 }
149
150 static void ics_eoi(ICSState *ics, int nr)
151 {
152 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
153
154 if (k->eoi) {
155 k->eoi(ics, nr);
156 }
157 }
158
159 static void icp_check_ipi(ICPState *icp)
160 {
161 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
162 return;
163 }
164
165 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
166
167 if (XISR(icp) && icp->xirr_owner) {
168 ics_reject(icp->xirr_owner, XISR(icp));
169 }
170
171 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
172 icp->pending_priority = icp->mfrr;
173 icp->xirr_owner = NULL;
174 qemu_irq_raise(icp->output);
175 }
176
177 void icp_resend(ICPState *icp)
178 {
179 XICSFabric *xi = icp->xics;
180 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
181
182 if (icp->mfrr < CPPR(icp)) {
183 icp_check_ipi(icp);
184 }
185
186 xic->ics_resend(xi);
187 }
188
189 void icp_set_cppr(ICPState *icp, uint8_t cppr)
190 {
191 uint8_t old_cppr;
192 uint32_t old_xisr;
193
194 old_cppr = CPPR(icp);
195 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
196
197 if (cppr < old_cppr) {
198 if (XISR(icp) && (cppr <= icp->pending_priority)) {
199 old_xisr = XISR(icp);
200 icp->xirr &= ~XISR_MASK; /* Clear XISR */
201 icp->pending_priority = 0xff;
202 qemu_irq_lower(icp->output);
203 if (icp->xirr_owner) {
204 ics_reject(icp->xirr_owner, old_xisr);
205 icp->xirr_owner = NULL;
206 }
207 }
208 } else {
209 if (!XISR(icp)) {
210 icp_resend(icp);
211 }
212 }
213 }
214
215 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
216 {
217 icp->mfrr = mfrr;
218 if (mfrr < CPPR(icp)) {
219 icp_check_ipi(icp);
220 }
221 }
222
223 uint32_t icp_accept(ICPState *icp)
224 {
225 uint32_t xirr = icp->xirr;
226
227 qemu_irq_lower(icp->output);
228 icp->xirr = icp->pending_priority << 24;
229 icp->pending_priority = 0xff;
230 icp->xirr_owner = NULL;
231
232 trace_xics_icp_accept(xirr, icp->xirr);
233
234 return xirr;
235 }
236
237 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
238 {
239 if (mfrr) {
240 *mfrr = icp->mfrr;
241 }
242 return icp->xirr;
243 }
244
245 void icp_eoi(ICPState *icp, uint32_t xirr)
246 {
247 XICSFabric *xi = icp->xics;
248 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
249 ICSState *ics;
250 uint32_t irq;
251
252 /* Send EOI -> ICS */
253 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
254 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
255 irq = xirr & XISR_MASK;
256
257 ics = xic->ics_get(xi, irq);
258 if (ics) {
259 ics_eoi(ics, irq);
260 }
261 if (!XISR(icp)) {
262 icp_resend(icp);
263 }
264 }
265
266 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
267 {
268 ICPState *icp = xics_icp_get(ics->xics, server);
269
270 trace_xics_icp_irq(server, nr, priority);
271
272 if ((priority >= CPPR(icp))
273 || (XISR(icp) && (icp->pending_priority <= priority))) {
274 ics_reject(ics, nr);
275 } else {
276 if (XISR(icp) && icp->xirr_owner) {
277 ics_reject(icp->xirr_owner, XISR(icp));
278 icp->xirr_owner = NULL;
279 }
280 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
281 icp->xirr_owner = ics;
282 icp->pending_priority = priority;
283 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
284 qemu_irq_raise(icp->output);
285 }
286 }
287
288 static void icp_dispatch_pre_save(void *opaque)
289 {
290 ICPState *icp = opaque;
291 ICPStateClass *info = ICP_GET_CLASS(icp);
292
293 if (info->pre_save) {
294 info->pre_save(icp);
295 }
296 }
297
298 static int icp_dispatch_post_load(void *opaque, int version_id)
299 {
300 ICPState *icp = opaque;
301 ICPStateClass *info = ICP_GET_CLASS(icp);
302
303 if (info->post_load) {
304 return info->post_load(icp, version_id);
305 }
306
307 return 0;
308 }
309
310 static const VMStateDescription vmstate_icp_server = {
311 .name = "icp/server",
312 .version_id = 1,
313 .minimum_version_id = 1,
314 .pre_save = icp_dispatch_pre_save,
315 .post_load = icp_dispatch_post_load,
316 .fields = (VMStateField[]) {
317 /* Sanity check */
318 VMSTATE_UINT32(xirr, ICPState),
319 VMSTATE_UINT8(pending_priority, ICPState),
320 VMSTATE_UINT8(mfrr, ICPState),
321 VMSTATE_END_OF_LIST()
322 },
323 };
324
325 static void icp_reset(void *dev)
326 {
327 ICPState *icp = ICP(dev);
328
329 icp->xirr = 0;
330 icp->pending_priority = 0xff;
331 icp->mfrr = 0xff;
332
333 /* Make all outputs are deasserted */
334 qemu_set_irq(icp->output, 0);
335 }
336
337 static void icp_realize(DeviceState *dev, Error **errp)
338 {
339 ICPState *icp = ICP(dev);
340 ICPStateClass *icpc = ICP_GET_CLASS(dev);
341 Object *obj;
342 Error *err = NULL;
343
344 obj = object_property_get_link(OBJECT(dev), "xics", &err);
345 if (!obj) {
346 error_setg(errp, "%s: required link 'xics' not found: %s",
347 __func__, error_get_pretty(err));
348 return;
349 }
350
351 icp->xics = XICS_FABRIC(obj);
352
353 if (icpc->realize) {
354 icpc->realize(dev, errp);
355 }
356
357 qemu_register_reset(icp_reset, dev);
358 }
359
360
361 static void icp_class_init(ObjectClass *klass, void *data)
362 {
363 DeviceClass *dc = DEVICE_CLASS(klass);
364
365 dc->vmsd = &vmstate_icp_server;
366 dc->realize = icp_realize;
367 }
368
369 static const TypeInfo icp_info = {
370 .name = TYPE_ICP,
371 .parent = TYPE_DEVICE,
372 .instance_size = sizeof(ICPState),
373 .class_init = icp_class_init,
374 .class_size = sizeof(ICPStateClass),
375 };
376
377 /*
378 * ICS: Source layer
379 */
380 static void ics_simple_resend_msi(ICSState *ics, int srcno)
381 {
382 ICSIRQState *irq = ics->irqs + srcno;
383
384 /* FIXME: filter by server#? */
385 if (irq->status & XICS_STATUS_REJECTED) {
386 irq->status &= ~XICS_STATUS_REJECTED;
387 if (irq->priority != 0xff) {
388 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
389 }
390 }
391 }
392
393 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
394 {
395 ICSIRQState *irq = ics->irqs + srcno;
396
397 if ((irq->priority != 0xff)
398 && (irq->status & XICS_STATUS_ASSERTED)
399 && !(irq->status & XICS_STATUS_SENT)) {
400 irq->status |= XICS_STATUS_SENT;
401 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
402 }
403 }
404
405 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
406 {
407 ICSIRQState *irq = ics->irqs + srcno;
408
409 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
410
411 if (val) {
412 if (irq->priority == 0xff) {
413 irq->status |= XICS_STATUS_MASKED_PENDING;
414 trace_xics_masked_pending();
415 } else {
416 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
417 }
418 }
419 }
420
421 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
422 {
423 ICSIRQState *irq = ics->irqs + srcno;
424
425 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
426 if (val) {
427 irq->status |= XICS_STATUS_ASSERTED;
428 } else {
429 irq->status &= ~XICS_STATUS_ASSERTED;
430 }
431 ics_simple_resend_lsi(ics, srcno);
432 }
433
434 static void ics_simple_set_irq(void *opaque, int srcno, int val)
435 {
436 ICSState *ics = (ICSState *)opaque;
437
438 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
439 ics_simple_set_irq_lsi(ics, srcno, val);
440 } else {
441 ics_simple_set_irq_msi(ics, srcno, val);
442 }
443 }
444
445 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
446 {
447 ICSIRQState *irq = ics->irqs + srcno;
448
449 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
450 || (irq->priority == 0xff)) {
451 return;
452 }
453
454 irq->status &= ~XICS_STATUS_MASKED_PENDING;
455 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
456 }
457
458 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
459 {
460 ics_simple_resend_lsi(ics, srcno);
461 }
462
463 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
464 uint8_t priority, uint8_t saved_priority)
465 {
466 ICSIRQState *irq = ics->irqs + srcno;
467
468 irq->server = server;
469 irq->priority = priority;
470 irq->saved_priority = saved_priority;
471
472 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
473 priority);
474
475 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
476 ics_simple_write_xive_lsi(ics, srcno);
477 } else {
478 ics_simple_write_xive_msi(ics, srcno);
479 }
480 }
481
482 static void ics_simple_reject(ICSState *ics, uint32_t nr)
483 {
484 ICSIRQState *irq = ics->irqs + nr - ics->offset;
485
486 trace_xics_ics_simple_reject(nr, nr - ics->offset);
487 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
488 irq->status |= XICS_STATUS_REJECTED;
489 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
490 irq->status &= ~XICS_STATUS_SENT;
491 }
492 }
493
494 static void ics_simple_resend(ICSState *ics)
495 {
496 int i;
497
498 for (i = 0; i < ics->nr_irqs; i++) {
499 /* FIXME: filter by server#? */
500 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
501 ics_simple_resend_lsi(ics, i);
502 } else {
503 ics_simple_resend_msi(ics, i);
504 }
505 }
506 }
507
508 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
509 {
510 int srcno = nr - ics->offset;
511 ICSIRQState *irq = ics->irqs + srcno;
512
513 trace_xics_ics_simple_eoi(nr);
514
515 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
516 irq->status &= ~XICS_STATUS_SENT;
517 }
518 }
519
520 static void ics_simple_reset(void *dev)
521 {
522 ICSState *ics = ICS_SIMPLE(dev);
523 int i;
524 uint8_t flags[ics->nr_irqs];
525
526 for (i = 0; i < ics->nr_irqs; i++) {
527 flags[i] = ics->irqs[i].flags;
528 }
529
530 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
531
532 for (i = 0; i < ics->nr_irqs; i++) {
533 ics->irqs[i].priority = 0xff;
534 ics->irqs[i].saved_priority = 0xff;
535 ics->irqs[i].flags = flags[i];
536 }
537 }
538
539 static void ics_simple_dispatch_pre_save(void *opaque)
540 {
541 ICSState *ics = opaque;
542 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
543
544 if (info->pre_save) {
545 info->pre_save(ics);
546 }
547 }
548
549 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
550 {
551 ICSState *ics = opaque;
552 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
553
554 if (info->post_load) {
555 return info->post_load(ics, version_id);
556 }
557
558 return 0;
559 }
560
561 static const VMStateDescription vmstate_ics_simple_irq = {
562 .name = "ics/irq",
563 .version_id = 2,
564 .minimum_version_id = 1,
565 .fields = (VMStateField[]) {
566 VMSTATE_UINT32(server, ICSIRQState),
567 VMSTATE_UINT8(priority, ICSIRQState),
568 VMSTATE_UINT8(saved_priority, ICSIRQState),
569 VMSTATE_UINT8(status, ICSIRQState),
570 VMSTATE_UINT8(flags, ICSIRQState),
571 VMSTATE_END_OF_LIST()
572 },
573 };
574
575 static const VMStateDescription vmstate_ics_simple = {
576 .name = "ics",
577 .version_id = 1,
578 .minimum_version_id = 1,
579 .pre_save = ics_simple_dispatch_pre_save,
580 .post_load = ics_simple_dispatch_post_load,
581 .fields = (VMStateField[]) {
582 /* Sanity check */
583 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
584
585 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
586 vmstate_ics_simple_irq,
587 ICSIRQState),
588 VMSTATE_END_OF_LIST()
589 },
590 };
591
592 static void ics_simple_initfn(Object *obj)
593 {
594 ICSState *ics = ICS_SIMPLE(obj);
595
596 ics->offset = XICS_IRQ_BASE;
597 }
598
599 static void ics_simple_realize(DeviceState *dev, Error **errp)
600 {
601 ICSState *ics = ICS_SIMPLE(dev);
602
603 if (!ics->nr_irqs) {
604 error_setg(errp, "Number of interrupts needs to be greater 0");
605 return;
606 }
607 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
608 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
609
610 qemu_register_reset(ics_simple_reset, dev);
611 }
612
613 static Property ics_simple_properties[] = {
614 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
615 DEFINE_PROP_END_OF_LIST(),
616 };
617
618 static void ics_simple_class_init(ObjectClass *klass, void *data)
619 {
620 DeviceClass *dc = DEVICE_CLASS(klass);
621 ICSStateClass *isc = ICS_BASE_CLASS(klass);
622
623 isc->realize = ics_simple_realize;
624 dc->props = ics_simple_properties;
625 dc->vmsd = &vmstate_ics_simple;
626 isc->reject = ics_simple_reject;
627 isc->resend = ics_simple_resend;
628 isc->eoi = ics_simple_eoi;
629 }
630
631 static const TypeInfo ics_simple_info = {
632 .name = TYPE_ICS_SIMPLE,
633 .parent = TYPE_ICS_BASE,
634 .instance_size = sizeof(ICSState),
635 .class_init = ics_simple_class_init,
636 .class_size = sizeof(ICSStateClass),
637 .instance_init = ics_simple_initfn,
638 };
639
640 static void ics_base_realize(DeviceState *dev, Error **errp)
641 {
642 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
643 ICSState *ics = ICS_BASE(dev);
644 Object *obj;
645 Error *err = NULL;
646
647 obj = object_property_get_link(OBJECT(dev), "xics", &err);
648 if (!obj) {
649 error_setg(errp, "%s: required link 'xics' not found: %s",
650 __func__, error_get_pretty(err));
651 return;
652 }
653 ics->xics = XICS_FABRIC(obj);
654
655
656 if (icsc->realize) {
657 icsc->realize(dev, errp);
658 }
659 }
660
661 static void ics_base_class_init(ObjectClass *klass, void *data)
662 {
663 DeviceClass *dc = DEVICE_CLASS(klass);
664
665 dc->realize = ics_base_realize;
666 }
667
668 static const TypeInfo ics_base_info = {
669 .name = TYPE_ICS_BASE,
670 .parent = TYPE_DEVICE,
671 .abstract = true,
672 .instance_size = sizeof(ICSState),
673 .class_init = ics_base_class_init,
674 .class_size = sizeof(ICSStateClass),
675 };
676
677 static const TypeInfo xics_fabric_info = {
678 .name = TYPE_XICS_FABRIC,
679 .parent = TYPE_INTERFACE,
680 .class_size = sizeof(XICSFabricClass),
681 };
682
683 /*
684 * Exported functions
685 */
686 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
687 {
688 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
689 ICSState *ics = xic->ics_get(xi, irq);
690
691 if (ics) {
692 return ics->qirqs[irq - ics->offset];
693 }
694
695 return NULL;
696 }
697
698 ICPState *xics_icp_get(XICSFabric *xi, int server)
699 {
700 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
701
702 return xic->icp_get(xi, server);
703 }
704
705 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
706 {
707 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
708
709 ics->irqs[srcno].flags |=
710 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
711 }
712
713 static void xics_register_types(void)
714 {
715 type_register_static(&ics_simple_info);
716 type_register_static(&ics_base_info);
717 type_register_static(&icp_info);
718 type_register_static(&xics_fabric_info);
719 }
720
721 type_init(xics_register_types)