error: Eliminate error_propagate() with Coccinelle, part 2
[qemu.git] / hw / intc / xics.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "cpu.h"
31 #include "trace.h"
32 #include "qemu/timer.h"
33 #include "hw/ppc/xics.h"
34 #include "hw/qdev-properties.h"
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qapi/visitor.h"
38 #include "migration/vmstate.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/irq.h"
42 #include "sysemu/kvm.h"
43 #include "sysemu/reset.h"
44
45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
46 {
47 int cpu_index;
48
49 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
50 * are hot plugged or unplugged.
51 */
52 if (!icp) {
53 return;
54 }
55
56 cpu_index = icp->cs ? icp->cs->cpu_index : -1;
57
58 if (!icp->output) {
59 return;
60 }
61
62 if (kvm_irqchip_in_kernel()) {
63 icp_synchronize_state(icp);
64 }
65
66 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
67 cpu_index, icp->xirr, icp->xirr_owner,
68 icp->pending_priority, icp->mfrr);
69 }
70
71 void ics_pic_print_info(ICSState *ics, Monitor *mon)
72 {
73 uint32_t i;
74
75 monitor_printf(mon, "ICS %4x..%4x %p\n",
76 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
77
78 if (!ics->irqs) {
79 return;
80 }
81
82 if (kvm_irqchip_in_kernel()) {
83 ics_synchronize_state(ics);
84 }
85
86 for (i = 0; i < ics->nr_irqs; i++) {
87 ICSIRQState *irq = ics->irqs + i;
88
89 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
90 continue;
91 }
92 monitor_printf(mon, " %4x %s %02x %02x\n",
93 ics->offset + i,
94 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
95 "LSI" : "MSI",
96 irq->priority, irq->status);
97 }
98 }
99
100 /*
101 * ICP: Presentation layer
102 */
103
104 #define XISR_MASK 0x00ffffff
105 #define CPPR_MASK 0xff000000
106
107 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
108 #define CPPR(icp) (((icp)->xirr) >> 24)
109
110 static void ics_reject(ICSState *ics, uint32_t nr);
111 static void ics_eoi(ICSState *ics, uint32_t nr);
112
113 static void icp_check_ipi(ICPState *icp)
114 {
115 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
116 return;
117 }
118
119 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
120
121 if (XISR(icp) && icp->xirr_owner) {
122 ics_reject(icp->xirr_owner, XISR(icp));
123 }
124
125 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
126 icp->pending_priority = icp->mfrr;
127 icp->xirr_owner = NULL;
128 qemu_irq_raise(icp->output);
129 }
130
131 void icp_resend(ICPState *icp)
132 {
133 XICSFabric *xi = icp->xics;
134 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
135
136 if (icp->mfrr < CPPR(icp)) {
137 icp_check_ipi(icp);
138 }
139
140 xic->ics_resend(xi);
141 }
142
143 void icp_set_cppr(ICPState *icp, uint8_t cppr)
144 {
145 uint8_t old_cppr;
146 uint32_t old_xisr;
147
148 old_cppr = CPPR(icp);
149 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
150
151 if (cppr < old_cppr) {
152 if (XISR(icp) && (cppr <= icp->pending_priority)) {
153 old_xisr = XISR(icp);
154 icp->xirr &= ~XISR_MASK; /* Clear XISR */
155 icp->pending_priority = 0xff;
156 qemu_irq_lower(icp->output);
157 if (icp->xirr_owner) {
158 ics_reject(icp->xirr_owner, old_xisr);
159 icp->xirr_owner = NULL;
160 }
161 }
162 } else {
163 if (!XISR(icp)) {
164 icp_resend(icp);
165 }
166 }
167 }
168
169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
170 {
171 icp->mfrr = mfrr;
172 if (mfrr < CPPR(icp)) {
173 icp_check_ipi(icp);
174 }
175 }
176
177 uint32_t icp_accept(ICPState *icp)
178 {
179 uint32_t xirr = icp->xirr;
180
181 qemu_irq_lower(icp->output);
182 icp->xirr = icp->pending_priority << 24;
183 icp->pending_priority = 0xff;
184 icp->xirr_owner = NULL;
185
186 trace_xics_icp_accept(xirr, icp->xirr);
187
188 return xirr;
189 }
190
191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
192 {
193 if (mfrr) {
194 *mfrr = icp->mfrr;
195 }
196 return icp->xirr;
197 }
198
199 void icp_eoi(ICPState *icp, uint32_t xirr)
200 {
201 XICSFabric *xi = icp->xics;
202 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
203 ICSState *ics;
204 uint32_t irq;
205
206 /* Send EOI -> ICS */
207 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
208 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
209 irq = xirr & XISR_MASK;
210
211 ics = xic->ics_get(xi, irq);
212 if (ics) {
213 ics_eoi(ics, irq);
214 }
215 if (!XISR(icp)) {
216 icp_resend(icp);
217 }
218 }
219
220 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
221 {
222 ICPState *icp = xics_icp_get(ics->xics, server);
223
224 trace_xics_icp_irq(server, nr, priority);
225
226 if ((priority >= CPPR(icp))
227 || (XISR(icp) && (icp->pending_priority <= priority))) {
228 ics_reject(ics, nr);
229 } else {
230 if (XISR(icp) && icp->xirr_owner) {
231 ics_reject(icp->xirr_owner, XISR(icp));
232 icp->xirr_owner = NULL;
233 }
234 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
235 icp->xirr_owner = ics;
236 icp->pending_priority = priority;
237 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
238 qemu_irq_raise(icp->output);
239 }
240 }
241
242 static int icp_pre_save(void *opaque)
243 {
244 ICPState *icp = opaque;
245
246 if (kvm_irqchip_in_kernel()) {
247 icp_get_kvm_state(icp);
248 }
249
250 return 0;
251 }
252
253 static int icp_post_load(void *opaque, int version_id)
254 {
255 ICPState *icp = opaque;
256
257 if (kvm_irqchip_in_kernel()) {
258 Error *local_err = NULL;
259 int ret;
260
261 ret = icp_set_kvm_state(icp, &local_err);
262 if (ret < 0) {
263 error_report_err(local_err);
264 return ret;
265 }
266 }
267
268 return 0;
269 }
270
271 static const VMStateDescription vmstate_icp_server = {
272 .name = "icp/server",
273 .version_id = 1,
274 .minimum_version_id = 1,
275 .pre_save = icp_pre_save,
276 .post_load = icp_post_load,
277 .fields = (VMStateField[]) {
278 /* Sanity check */
279 VMSTATE_UINT32(xirr, ICPState),
280 VMSTATE_UINT8(pending_priority, ICPState),
281 VMSTATE_UINT8(mfrr, ICPState),
282 VMSTATE_END_OF_LIST()
283 },
284 };
285
286 void icp_reset(ICPState *icp)
287 {
288 icp->xirr = 0;
289 icp->pending_priority = 0xff;
290 icp->mfrr = 0xff;
291
292 if (kvm_irqchip_in_kernel()) {
293 Error *local_err = NULL;
294
295 icp_set_kvm_state(icp, &local_err);
296 if (local_err) {
297 error_report_err(local_err);
298 }
299 }
300 }
301
302 static void icp_realize(DeviceState *dev, Error **errp)
303 {
304 ICPState *icp = ICP(dev);
305 CPUPPCState *env;
306 Error *err = NULL;
307
308 assert(icp->xics);
309 assert(icp->cs);
310
311 env = &POWERPC_CPU(icp->cs)->env;
312 switch (PPC_INPUT(env)) {
313 case PPC_FLAGS_INPUT_POWER7:
314 icp->output = env->irq_inputs[POWER7_INPUT_INT];
315 break;
316 case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
317 icp->output = env->irq_inputs[POWER9_INPUT_INT];
318 break;
319
320 case PPC_FLAGS_INPUT_970:
321 icp->output = env->irq_inputs[PPC970_INPUT_INT];
322 break;
323
324 default:
325 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
326 return;
327 }
328
329 /* Connect the presenter to the VCPU (required for CPU hotplug) */
330 if (kvm_irqchip_in_kernel()) {
331 icp_kvm_realize(dev, &err);
332 if (err) {
333 error_propagate(errp, err);
334 return;
335 }
336 }
337
338 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
339 }
340
341 static void icp_unrealize(DeviceState *dev)
342 {
343 ICPState *icp = ICP(dev);
344
345 vmstate_unregister(NULL, &vmstate_icp_server, icp);
346 }
347
348 static Property icp_properties[] = {
349 DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
350 XICSFabric *),
351 DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
352 DEFINE_PROP_END_OF_LIST(),
353 };
354
355 static void icp_class_init(ObjectClass *klass, void *data)
356 {
357 DeviceClass *dc = DEVICE_CLASS(klass);
358
359 dc->realize = icp_realize;
360 dc->unrealize = icp_unrealize;
361 device_class_set_props(dc, icp_properties);
362 /*
363 * Reason: part of XICS interrupt controller, needs to be wired up
364 * by icp_create().
365 */
366 dc->user_creatable = false;
367 }
368
369 static const TypeInfo icp_info = {
370 .name = TYPE_ICP,
371 .parent = TYPE_DEVICE,
372 .instance_size = sizeof(ICPState),
373 .class_init = icp_class_init,
374 .class_size = sizeof(ICPStateClass),
375 };
376
377 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
378 {
379 Object *obj;
380
381 obj = object_new(type);
382 object_property_add_child(cpu, type, obj);
383 object_unref(obj);
384 object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort);
385 object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort);
386 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
387 object_unparent(obj);
388 obj = NULL;
389 }
390
391 return obj;
392 }
393
394 void icp_destroy(ICPState *icp)
395 {
396 Object *obj = OBJECT(icp);
397
398 object_unparent(obj);
399 }
400
401 /*
402 * ICS: Source layer
403 */
404 static void ics_resend_msi(ICSState *ics, int srcno)
405 {
406 ICSIRQState *irq = ics->irqs + srcno;
407
408 /* FIXME: filter by server#? */
409 if (irq->status & XICS_STATUS_REJECTED) {
410 irq->status &= ~XICS_STATUS_REJECTED;
411 if (irq->priority != 0xff) {
412 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
413 }
414 }
415 }
416
417 static void ics_resend_lsi(ICSState *ics, int srcno)
418 {
419 ICSIRQState *irq = ics->irqs + srcno;
420
421 if ((irq->priority != 0xff)
422 && (irq->status & XICS_STATUS_ASSERTED)
423 && !(irq->status & XICS_STATUS_SENT)) {
424 irq->status |= XICS_STATUS_SENT;
425 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
426 }
427 }
428
429 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
430 {
431 ICSIRQState *irq = ics->irqs + srcno;
432
433 trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
434
435 if (val) {
436 if (irq->priority == 0xff) {
437 irq->status |= XICS_STATUS_MASKED_PENDING;
438 trace_xics_masked_pending();
439 } else {
440 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
441 }
442 }
443 }
444
445 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
446 {
447 ICSIRQState *irq = ics->irqs + srcno;
448
449 trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
450 if (val) {
451 irq->status |= XICS_STATUS_ASSERTED;
452 } else {
453 irq->status &= ~XICS_STATUS_ASSERTED;
454 }
455 ics_resend_lsi(ics, srcno);
456 }
457
458 void ics_set_irq(void *opaque, int srcno, int val)
459 {
460 ICSState *ics = (ICSState *)opaque;
461
462 if (kvm_irqchip_in_kernel()) {
463 ics_kvm_set_irq(ics, srcno, val);
464 return;
465 }
466
467 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
468 ics_set_irq_lsi(ics, srcno, val);
469 } else {
470 ics_set_irq_msi(ics, srcno, val);
471 }
472 }
473
474 static void ics_write_xive_msi(ICSState *ics, int srcno)
475 {
476 ICSIRQState *irq = ics->irqs + srcno;
477
478 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
479 || (irq->priority == 0xff)) {
480 return;
481 }
482
483 irq->status &= ~XICS_STATUS_MASKED_PENDING;
484 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
485 }
486
487 static void ics_write_xive_lsi(ICSState *ics, int srcno)
488 {
489 ics_resend_lsi(ics, srcno);
490 }
491
492 void ics_write_xive(ICSState *ics, int srcno, int server,
493 uint8_t priority, uint8_t saved_priority)
494 {
495 ICSIRQState *irq = ics->irqs + srcno;
496
497 irq->server = server;
498 irq->priority = priority;
499 irq->saved_priority = saved_priority;
500
501 trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
502
503 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
504 ics_write_xive_lsi(ics, srcno);
505 } else {
506 ics_write_xive_msi(ics, srcno);
507 }
508 }
509
510 static void ics_reject(ICSState *ics, uint32_t nr)
511 {
512 ICSStateClass *isc = ICS_GET_CLASS(ics);
513 ICSIRQState *irq = ics->irqs + nr - ics->offset;
514
515 if (isc->reject) {
516 isc->reject(ics, nr);
517 return;
518 }
519
520 trace_xics_ics_reject(nr, nr - ics->offset);
521 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
522 irq->status |= XICS_STATUS_REJECTED;
523 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
524 irq->status &= ~XICS_STATUS_SENT;
525 }
526 }
527
528 void ics_resend(ICSState *ics)
529 {
530 ICSStateClass *isc = ICS_GET_CLASS(ics);
531 int i;
532
533 if (isc->resend) {
534 isc->resend(ics);
535 return;
536 }
537
538 for (i = 0; i < ics->nr_irqs; i++) {
539 /* FIXME: filter by server#? */
540 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
541 ics_resend_lsi(ics, i);
542 } else {
543 ics_resend_msi(ics, i);
544 }
545 }
546 }
547
548 static void ics_eoi(ICSState *ics, uint32_t nr)
549 {
550 int srcno = nr - ics->offset;
551 ICSIRQState *irq = ics->irqs + srcno;
552
553 trace_xics_ics_eoi(nr);
554
555 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
556 irq->status &= ~XICS_STATUS_SENT;
557 }
558 }
559
560 static void ics_reset_irq(ICSIRQState *irq)
561 {
562 irq->priority = 0xff;
563 irq->saved_priority = 0xff;
564 }
565
566 static void ics_reset(DeviceState *dev)
567 {
568 ICSState *ics = ICS(dev);
569 int i;
570 uint8_t flags[ics->nr_irqs];
571
572 for (i = 0; i < ics->nr_irqs; i++) {
573 flags[i] = ics->irqs[i].flags;
574 }
575
576 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
577
578 for (i = 0; i < ics->nr_irqs; i++) {
579 ics_reset_irq(ics->irqs + i);
580 ics->irqs[i].flags = flags[i];
581 }
582
583 if (kvm_irqchip_in_kernel()) {
584 Error *local_err = NULL;
585
586 ics_set_kvm_state(ICS(dev), &local_err);
587 if (local_err) {
588 error_report_err(local_err);
589 }
590 }
591 }
592
593 static void ics_reset_handler(void *dev)
594 {
595 ics_reset(dev);
596 }
597
598 static void ics_realize(DeviceState *dev, Error **errp)
599 {
600 ICSState *ics = ICS(dev);
601
602 assert(ics->xics);
603
604 if (!ics->nr_irqs) {
605 error_setg(errp, "Number of interrupts needs to be greater 0");
606 return;
607 }
608 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
609
610 qemu_register_reset(ics_reset_handler, ics);
611 }
612
613 static void ics_instance_init(Object *obj)
614 {
615 ICSState *ics = ICS(obj);
616
617 ics->offset = XICS_IRQ_BASE;
618 }
619
620 static int ics_pre_save(void *opaque)
621 {
622 ICSState *ics = opaque;
623
624 if (kvm_irqchip_in_kernel()) {
625 ics_get_kvm_state(ics);
626 }
627
628 return 0;
629 }
630
631 static int ics_post_load(void *opaque, int version_id)
632 {
633 ICSState *ics = opaque;
634
635 if (kvm_irqchip_in_kernel()) {
636 Error *local_err = NULL;
637 int ret;
638
639 ret = ics_set_kvm_state(ics, &local_err);
640 if (ret < 0) {
641 error_report_err(local_err);
642 return ret;
643 }
644 }
645
646 return 0;
647 }
648
649 static const VMStateDescription vmstate_ics_irq = {
650 .name = "ics/irq",
651 .version_id = 2,
652 .minimum_version_id = 1,
653 .fields = (VMStateField[]) {
654 VMSTATE_UINT32(server, ICSIRQState),
655 VMSTATE_UINT8(priority, ICSIRQState),
656 VMSTATE_UINT8(saved_priority, ICSIRQState),
657 VMSTATE_UINT8(status, ICSIRQState),
658 VMSTATE_UINT8(flags, ICSIRQState),
659 VMSTATE_END_OF_LIST()
660 },
661 };
662
663 static const VMStateDescription vmstate_ics = {
664 .name = "ics",
665 .version_id = 1,
666 .minimum_version_id = 1,
667 .pre_save = ics_pre_save,
668 .post_load = ics_post_load,
669 .fields = (VMStateField[]) {
670 /* Sanity check */
671 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
672
673 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
674 vmstate_ics_irq,
675 ICSIRQState),
676 VMSTATE_END_OF_LIST()
677 },
678 };
679
680 static Property ics_properties[] = {
681 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
682 DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
683 XICSFabric *),
684 DEFINE_PROP_END_OF_LIST(),
685 };
686
687 static void ics_class_init(ObjectClass *klass, void *data)
688 {
689 DeviceClass *dc = DEVICE_CLASS(klass);
690
691 dc->realize = ics_realize;
692 device_class_set_props(dc, ics_properties);
693 dc->reset = ics_reset;
694 dc->vmsd = &vmstate_ics;
695 /*
696 * Reason: part of XICS interrupt controller, needs to be wired up,
697 * e.g. by spapr_irq_init().
698 */
699 dc->user_creatable = false;
700 }
701
702 static const TypeInfo ics_info = {
703 .name = TYPE_ICS,
704 .parent = TYPE_DEVICE,
705 .instance_size = sizeof(ICSState),
706 .instance_init = ics_instance_init,
707 .class_init = ics_class_init,
708 .class_size = sizeof(ICSStateClass),
709 };
710
711 static const TypeInfo xics_fabric_info = {
712 .name = TYPE_XICS_FABRIC,
713 .parent = TYPE_INTERFACE,
714 .class_size = sizeof(XICSFabricClass),
715 };
716
717 /*
718 * Exported functions
719 */
720 ICPState *xics_icp_get(XICSFabric *xi, int server)
721 {
722 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
723
724 return xic->icp_get(xi, server);
725 }
726
727 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
728 {
729 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
730
731 ics->irqs[srcno].flags |=
732 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
733
734 if (kvm_irqchip_in_kernel()) {
735 Error *local_err = NULL;
736
737 ics_reset_irq(ics->irqs + srcno);
738 ics_set_kvm_state_one(ics, srcno, &local_err);
739 if (local_err) {
740 error_report_err(local_err);
741 }
742 }
743 }
744
745 static void xics_register_types(void)
746 {
747 type_register_static(&ics_info);
748 type_register_static(&icp_info);
749 type_register_static(&xics_fabric_info);
750 }
751
752 type_init(xics_register_types)