ppc/xics: move the vmstate structures under the ics-base class
[qemu.git] / hw / intc / xics.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
31 #include "cpu.h"
32 #include "hw/hw.h"
33 #include "trace.h"
34 #include "qemu/timer.h"
35 #include "hw/ppc/xics.h"
36 #include "qemu/error-report.h"
37 #include "qapi/visitor.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
40
41 void icp_pic_print_info(ICPState *icp, Monitor *mon)
42 {
43 ICPStateClass *icpc = ICP_GET_CLASS(icp);
44 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
45
46 if (!icp->output) {
47 return;
48 }
49
50 if (icpc->synchronize_state) {
51 icpc->synchronize_state(icp);
52 }
53
54 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
55 cpu_index, icp->xirr, icp->xirr_owner,
56 icp->pending_priority, icp->mfrr);
57 }
58
59 void ics_pic_print_info(ICSState *ics, Monitor *mon)
60 {
61 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
62 uint32_t i;
63
64 monitor_printf(mon, "ICS %4x..%4x %p\n",
65 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
66
67 if (!ics->irqs) {
68 return;
69 }
70
71 if (icsc->synchronize_state) {
72 icsc->synchronize_state(ics);
73 }
74
75 for (i = 0; i < ics->nr_irqs; i++) {
76 ICSIRQState *irq = ics->irqs + i;
77
78 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
79 continue;
80 }
81 monitor_printf(mon, " %4x %s %02x %02x\n",
82 ics->offset + i,
83 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
84 "LSI" : "MSI",
85 irq->priority, irq->status);
86 }
87 }
88
89 /*
90 * ICP: Presentation layer
91 */
92
93 #define XISR_MASK 0x00ffffff
94 #define CPPR_MASK 0xff000000
95
96 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
97 #define CPPR(icp) (((icp)->xirr) >> 24)
98
99 static void ics_reject(ICSState *ics, uint32_t nr)
100 {
101 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
102
103 if (k->reject) {
104 k->reject(ics, nr);
105 }
106 }
107
108 void ics_resend(ICSState *ics)
109 {
110 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
111
112 if (k->resend) {
113 k->resend(ics);
114 }
115 }
116
117 static void ics_eoi(ICSState *ics, int nr)
118 {
119 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
120
121 if (k->eoi) {
122 k->eoi(ics, nr);
123 }
124 }
125
126 static void icp_check_ipi(ICPState *icp)
127 {
128 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
129 return;
130 }
131
132 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
133
134 if (XISR(icp) && icp->xirr_owner) {
135 ics_reject(icp->xirr_owner, XISR(icp));
136 }
137
138 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
139 icp->pending_priority = icp->mfrr;
140 icp->xirr_owner = NULL;
141 qemu_irq_raise(icp->output);
142 }
143
144 void icp_resend(ICPState *icp)
145 {
146 XICSFabric *xi = icp->xics;
147 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
148
149 if (icp->mfrr < CPPR(icp)) {
150 icp_check_ipi(icp);
151 }
152
153 xic->ics_resend(xi);
154 }
155
156 void icp_set_cppr(ICPState *icp, uint8_t cppr)
157 {
158 uint8_t old_cppr;
159 uint32_t old_xisr;
160
161 old_cppr = CPPR(icp);
162 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
163
164 if (cppr < old_cppr) {
165 if (XISR(icp) && (cppr <= icp->pending_priority)) {
166 old_xisr = XISR(icp);
167 icp->xirr &= ~XISR_MASK; /* Clear XISR */
168 icp->pending_priority = 0xff;
169 qemu_irq_lower(icp->output);
170 if (icp->xirr_owner) {
171 ics_reject(icp->xirr_owner, old_xisr);
172 icp->xirr_owner = NULL;
173 }
174 }
175 } else {
176 if (!XISR(icp)) {
177 icp_resend(icp);
178 }
179 }
180 }
181
182 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
183 {
184 icp->mfrr = mfrr;
185 if (mfrr < CPPR(icp)) {
186 icp_check_ipi(icp);
187 }
188 }
189
190 uint32_t icp_accept(ICPState *icp)
191 {
192 uint32_t xirr = icp->xirr;
193
194 qemu_irq_lower(icp->output);
195 icp->xirr = icp->pending_priority << 24;
196 icp->pending_priority = 0xff;
197 icp->xirr_owner = NULL;
198
199 trace_xics_icp_accept(xirr, icp->xirr);
200
201 return xirr;
202 }
203
204 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
205 {
206 if (mfrr) {
207 *mfrr = icp->mfrr;
208 }
209 return icp->xirr;
210 }
211
212 void icp_eoi(ICPState *icp, uint32_t xirr)
213 {
214 XICSFabric *xi = icp->xics;
215 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
216 ICSState *ics;
217 uint32_t irq;
218
219 /* Send EOI -> ICS */
220 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
221 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
222 irq = xirr & XISR_MASK;
223
224 ics = xic->ics_get(xi, irq);
225 if (ics) {
226 ics_eoi(ics, irq);
227 }
228 if (!XISR(icp)) {
229 icp_resend(icp);
230 }
231 }
232
233 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
234 {
235 ICPState *icp = xics_icp_get(ics->xics, server);
236
237 trace_xics_icp_irq(server, nr, priority);
238
239 if ((priority >= CPPR(icp))
240 || (XISR(icp) && (icp->pending_priority <= priority))) {
241 ics_reject(ics, nr);
242 } else {
243 if (XISR(icp) && icp->xirr_owner) {
244 ics_reject(icp->xirr_owner, XISR(icp));
245 icp->xirr_owner = NULL;
246 }
247 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
248 icp->xirr_owner = ics;
249 icp->pending_priority = priority;
250 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
251 qemu_irq_raise(icp->output);
252 }
253 }
254
255 static int icp_dispatch_pre_save(void *opaque)
256 {
257 ICPState *icp = opaque;
258 ICPStateClass *info = ICP_GET_CLASS(icp);
259
260 if (info->pre_save) {
261 info->pre_save(icp);
262 }
263
264 return 0;
265 }
266
267 static int icp_dispatch_post_load(void *opaque, int version_id)
268 {
269 ICPState *icp = opaque;
270 ICPStateClass *info = ICP_GET_CLASS(icp);
271
272 if (info->post_load) {
273 return info->post_load(icp, version_id);
274 }
275
276 return 0;
277 }
278
279 static const VMStateDescription vmstate_icp_server = {
280 .name = "icp/server",
281 .version_id = 1,
282 .minimum_version_id = 1,
283 .pre_save = icp_dispatch_pre_save,
284 .post_load = icp_dispatch_post_load,
285 .fields = (VMStateField[]) {
286 /* Sanity check */
287 VMSTATE_UINT32(xirr, ICPState),
288 VMSTATE_UINT8(pending_priority, ICPState),
289 VMSTATE_UINT8(mfrr, ICPState),
290 VMSTATE_END_OF_LIST()
291 },
292 };
293
294 static void icp_reset(void *dev)
295 {
296 ICPState *icp = ICP(dev);
297
298 icp->xirr = 0;
299 icp->pending_priority = 0xff;
300 icp->mfrr = 0xff;
301
302 /* Make all outputs are deasserted */
303 qemu_set_irq(icp->output, 0);
304 }
305
306 static void icp_realize(DeviceState *dev, Error **errp)
307 {
308 ICPState *icp = ICP(dev);
309 PowerPCCPU *cpu;
310 CPUPPCState *env;
311 Object *obj;
312 Error *err = NULL;
313
314 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
315 if (!obj) {
316 error_propagate(errp, err);
317 error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
318 return;
319 }
320
321 icp->xics = XICS_FABRIC(obj);
322
323 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
324 if (!obj) {
325 error_propagate(errp, err);
326 error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
327 return;
328 }
329
330 cpu = POWERPC_CPU(obj);
331 icp->cs = CPU(obj);
332
333 env = &cpu->env;
334 switch (PPC_INPUT(env)) {
335 case PPC_FLAGS_INPUT_POWER7:
336 icp->output = env->irq_inputs[POWER7_INPUT_INT];
337 break;
338
339 case PPC_FLAGS_INPUT_970:
340 icp->output = env->irq_inputs[PPC970_INPUT_INT];
341 break;
342
343 default:
344 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
345 return;
346 }
347
348 qemu_register_reset(icp_reset, dev);
349 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
350 }
351
352 static void icp_unrealize(DeviceState *dev, Error **errp)
353 {
354 ICPState *icp = ICP(dev);
355
356 vmstate_unregister(NULL, &vmstate_icp_server, icp);
357 qemu_unregister_reset(icp_reset, dev);
358 }
359
360 static void icp_class_init(ObjectClass *klass, void *data)
361 {
362 DeviceClass *dc = DEVICE_CLASS(klass);
363
364 dc->realize = icp_realize;
365 dc->unrealize = icp_unrealize;
366 }
367
368 static const TypeInfo icp_info = {
369 .name = TYPE_ICP,
370 .parent = TYPE_DEVICE,
371 .instance_size = sizeof(ICPState),
372 .class_init = icp_class_init,
373 .class_size = sizeof(ICPStateClass),
374 };
375
376 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
377 {
378 Error *local_err = NULL;
379 Object *obj;
380
381 obj = object_new(type);
382 object_property_add_child(cpu, type, obj, &error_abort);
383 object_unref(obj);
384 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
385 &error_abort);
386 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
387 object_property_set_bool(obj, true, "realized", &local_err);
388 if (local_err) {
389 object_unparent(obj);
390 error_propagate(errp, local_err);
391 obj = NULL;
392 }
393
394 return obj;
395 }
396
397 /*
398 * ICS: Source layer
399 */
400 static void ics_simple_resend_msi(ICSState *ics, int srcno)
401 {
402 ICSIRQState *irq = ics->irqs + srcno;
403
404 /* FIXME: filter by server#? */
405 if (irq->status & XICS_STATUS_REJECTED) {
406 irq->status &= ~XICS_STATUS_REJECTED;
407 if (irq->priority != 0xff) {
408 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
409 }
410 }
411 }
412
413 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
414 {
415 ICSIRQState *irq = ics->irqs + srcno;
416
417 if ((irq->priority != 0xff)
418 && (irq->status & XICS_STATUS_ASSERTED)
419 && !(irq->status & XICS_STATUS_SENT)) {
420 irq->status |= XICS_STATUS_SENT;
421 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
422 }
423 }
424
425 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
426 {
427 ICSIRQState *irq = ics->irqs + srcno;
428
429 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
430
431 if (val) {
432 if (irq->priority == 0xff) {
433 irq->status |= XICS_STATUS_MASKED_PENDING;
434 trace_xics_masked_pending();
435 } else {
436 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
437 }
438 }
439 }
440
441 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
442 {
443 ICSIRQState *irq = ics->irqs + srcno;
444
445 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
446 if (val) {
447 irq->status |= XICS_STATUS_ASSERTED;
448 } else {
449 irq->status &= ~XICS_STATUS_ASSERTED;
450 }
451 ics_simple_resend_lsi(ics, srcno);
452 }
453
454 static void ics_simple_set_irq(void *opaque, int srcno, int val)
455 {
456 ICSState *ics = (ICSState *)opaque;
457
458 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
459 ics_simple_set_irq_lsi(ics, srcno, val);
460 } else {
461 ics_simple_set_irq_msi(ics, srcno, val);
462 }
463 }
464
465 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
466 {
467 ICSIRQState *irq = ics->irqs + srcno;
468
469 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
470 || (irq->priority == 0xff)) {
471 return;
472 }
473
474 irq->status &= ~XICS_STATUS_MASKED_PENDING;
475 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
476 }
477
478 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
479 {
480 ics_simple_resend_lsi(ics, srcno);
481 }
482
483 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
484 uint8_t priority, uint8_t saved_priority)
485 {
486 ICSIRQState *irq = ics->irqs + srcno;
487
488 irq->server = server;
489 irq->priority = priority;
490 irq->saved_priority = saved_priority;
491
492 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
493 priority);
494
495 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
496 ics_simple_write_xive_lsi(ics, srcno);
497 } else {
498 ics_simple_write_xive_msi(ics, srcno);
499 }
500 }
501
502 static void ics_simple_reject(ICSState *ics, uint32_t nr)
503 {
504 ICSIRQState *irq = ics->irqs + nr - ics->offset;
505
506 trace_xics_ics_simple_reject(nr, nr - ics->offset);
507 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
508 irq->status |= XICS_STATUS_REJECTED;
509 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
510 irq->status &= ~XICS_STATUS_SENT;
511 }
512 }
513
514 static void ics_simple_resend(ICSState *ics)
515 {
516 int i;
517
518 for (i = 0; i < ics->nr_irqs; i++) {
519 /* FIXME: filter by server#? */
520 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
521 ics_simple_resend_lsi(ics, i);
522 } else {
523 ics_simple_resend_msi(ics, i);
524 }
525 }
526 }
527
528 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
529 {
530 int srcno = nr - ics->offset;
531 ICSIRQState *irq = ics->irqs + srcno;
532
533 trace_xics_ics_simple_eoi(nr);
534
535 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
536 irq->status &= ~XICS_STATUS_SENT;
537 }
538 }
539
540 static void ics_simple_reset(DeviceState *dev)
541 {
542 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
543
544 icsc->parent_reset(dev);
545 }
546
547 static void ics_simple_reset_handler(void *dev)
548 {
549 ics_simple_reset(dev);
550 }
551
552 static void ics_simple_realize(DeviceState *dev, Error **errp)
553 {
554 ICSState *ics = ICS_SIMPLE(dev);
555 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
556 Error *local_err = NULL;
557
558 icsc->parent_realize(dev, &local_err);
559 if (local_err) {
560 error_propagate(errp, local_err);
561 return;
562 }
563
564 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
565
566 qemu_register_reset(ics_simple_reset_handler, ics);
567 }
568
569 static void ics_simple_class_init(ObjectClass *klass, void *data)
570 {
571 DeviceClass *dc = DEVICE_CLASS(klass);
572 ICSStateClass *isc = ICS_BASE_CLASS(klass);
573
574 device_class_set_parent_realize(dc, ics_simple_realize,
575 &isc->parent_realize);
576 device_class_set_parent_reset(dc, ics_simple_reset,
577 &isc->parent_reset);
578
579 isc->reject = ics_simple_reject;
580 isc->resend = ics_simple_resend;
581 isc->eoi = ics_simple_eoi;
582 }
583
584 static const TypeInfo ics_simple_info = {
585 .name = TYPE_ICS_SIMPLE,
586 .parent = TYPE_ICS_BASE,
587 .instance_size = sizeof(ICSState),
588 .class_init = ics_simple_class_init,
589 .class_size = sizeof(ICSStateClass),
590 };
591
592 static void ics_base_reset(DeviceState *dev)
593 {
594 ICSState *ics = ICS_BASE(dev);
595 int i;
596 uint8_t flags[ics->nr_irqs];
597
598 for (i = 0; i < ics->nr_irqs; i++) {
599 flags[i] = ics->irqs[i].flags;
600 }
601
602 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
603
604 for (i = 0; i < ics->nr_irqs; i++) {
605 ics->irqs[i].priority = 0xff;
606 ics->irqs[i].saved_priority = 0xff;
607 ics->irqs[i].flags = flags[i];
608 }
609 }
610
611 static void ics_base_realize(DeviceState *dev, Error **errp)
612 {
613 ICSState *ics = ICS_BASE(dev);
614 Object *obj;
615 Error *err = NULL;
616
617 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
618 if (!obj) {
619 error_propagate(errp, err);
620 error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
621 return;
622 }
623 ics->xics = XICS_FABRIC(obj);
624
625 if (!ics->nr_irqs) {
626 error_setg(errp, "Number of interrupts needs to be greater 0");
627 return;
628 }
629 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
630 }
631
632 static void ics_base_instance_init(Object *obj)
633 {
634 ICSState *ics = ICS_BASE(obj);
635
636 ics->offset = XICS_IRQ_BASE;
637 }
638
639 static int ics_base_dispatch_pre_save(void *opaque)
640 {
641 ICSState *ics = opaque;
642 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
643
644 if (info->pre_save) {
645 info->pre_save(ics);
646 }
647
648 return 0;
649 }
650
651 static int ics_base_dispatch_post_load(void *opaque, int version_id)
652 {
653 ICSState *ics = opaque;
654 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
655
656 if (info->post_load) {
657 return info->post_load(ics, version_id);
658 }
659
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_ics_base_irq = {
664 .name = "ics/irq",
665 .version_id = 2,
666 .minimum_version_id = 1,
667 .fields = (VMStateField[]) {
668 VMSTATE_UINT32(server, ICSIRQState),
669 VMSTATE_UINT8(priority, ICSIRQState),
670 VMSTATE_UINT8(saved_priority, ICSIRQState),
671 VMSTATE_UINT8(status, ICSIRQState),
672 VMSTATE_UINT8(flags, ICSIRQState),
673 VMSTATE_END_OF_LIST()
674 },
675 };
676
677 static const VMStateDescription vmstate_ics_base = {
678 .name = "ics",
679 .version_id = 1,
680 .minimum_version_id = 1,
681 .pre_save = ics_base_dispatch_pre_save,
682 .post_load = ics_base_dispatch_post_load,
683 .fields = (VMStateField[]) {
684 /* Sanity check */
685 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
686
687 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
688 vmstate_ics_base_irq,
689 ICSIRQState),
690 VMSTATE_END_OF_LIST()
691 },
692 };
693
694 static Property ics_base_properties[] = {
695 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
696 DEFINE_PROP_END_OF_LIST(),
697 };
698
699 static void ics_base_class_init(ObjectClass *klass, void *data)
700 {
701 DeviceClass *dc = DEVICE_CLASS(klass);
702
703 dc->realize = ics_base_realize;
704 dc->props = ics_base_properties;
705 dc->reset = ics_base_reset;
706 dc->vmsd = &vmstate_ics_base;
707 }
708
709 static const TypeInfo ics_base_info = {
710 .name = TYPE_ICS_BASE,
711 .parent = TYPE_DEVICE,
712 .abstract = true,
713 .instance_size = sizeof(ICSState),
714 .instance_init = ics_base_instance_init,
715 .class_init = ics_base_class_init,
716 .class_size = sizeof(ICSStateClass),
717 };
718
719 static const TypeInfo xics_fabric_info = {
720 .name = TYPE_XICS_FABRIC,
721 .parent = TYPE_INTERFACE,
722 .class_size = sizeof(XICSFabricClass),
723 };
724
725 /*
726 * Exported functions
727 */
728 ICPState *xics_icp_get(XICSFabric *xi, int server)
729 {
730 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
731
732 return xic->icp_get(xi, server);
733 }
734
735 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
736 {
737 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
738
739 ics->irqs[srcno].flags |=
740 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
741 }
742
743 static void xics_register_types(void)
744 {
745 type_register_static(&ics_simple_info);
746 type_register_static(&ics_base_info);
747 type_register_static(&icp_info);
748 type_register_static(&xics_fabric_info);
749 }
750
751 type_init(xics_register_types)