PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / intel-hda-defs.h
1 #ifndef HW_INTEL_HDA_DEFS_H
2 #define HW_INTEL_HDA_DEFS_H
3
4 /* qemu */
5 #define HDA_BUFFER_SIZE 256
6
7 /* --------------------------------------------------------------------- */
8 /* from linux/sound/pci/hda/hda_intel.c */
9
10 /*
11 * registers
12 */
13 #define ICH6_REG_GCAP 0x00
14 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
15 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
16 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
17 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
18 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
19 #define ICH6_REG_VMIN 0x02
20 #define ICH6_REG_VMAJ 0x03
21 #define ICH6_REG_OUTPAY 0x04
22 #define ICH6_REG_INPAY 0x06
23 #define ICH6_REG_GCTL 0x08
24 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
25 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
26 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
27 #define ICH6_REG_WAKEEN 0x0c
28 #define ICH6_REG_STATESTS 0x0e
29 #define ICH6_REG_GSTS 0x10
30 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
31 #define ICH6_REG_INTCTL 0x20
32 #define ICH6_REG_INTSTS 0x24
33 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
34 #define ICH6_REG_SYNC 0x34
35 #define ICH6_REG_CORBLBASE 0x40
36 #define ICH6_REG_CORBUBASE 0x44
37 #define ICH6_REG_CORBWP 0x48
38 #define ICH6_REG_CORBRP 0x4a
39 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
40 #define ICH6_REG_CORBCTL 0x4c
41 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
42 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
43 #define ICH6_REG_CORBSTS 0x4d
44 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
45 #define ICH6_REG_CORBSIZE 0x4e
46
47 #define ICH6_REG_RIRBLBASE 0x50
48 #define ICH6_REG_RIRBUBASE 0x54
49 #define ICH6_REG_RIRBWP 0x58
50 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
51 #define ICH6_REG_RINTCNT 0x5a
52 #define ICH6_REG_RIRBCTL 0x5c
53 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
54 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
55 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
56 #define ICH6_REG_RIRBSTS 0x5d
57 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
58 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
59 #define ICH6_REG_RIRBSIZE 0x5e
60
61 #define ICH6_REG_IC 0x60
62 #define ICH6_REG_IR 0x64
63 #define ICH6_REG_IRS 0x68
64 #define ICH6_IRS_VALID (1<<1)
65 #define ICH6_IRS_BUSY (1<<0)
66
67 #define ICH6_REG_DPLBASE 0x70
68 #define ICH6_REG_DPUBASE 0x74
69 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
70
71 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
72 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
73
74 /* stream register offsets from stream base */
75 #define ICH6_REG_SD_CTL 0x00
76 #define ICH6_REG_SD_STS 0x03
77 #define ICH6_REG_SD_LPIB 0x04
78 #define ICH6_REG_SD_CBL 0x08
79 #define ICH6_REG_SD_LVI 0x0c
80 #define ICH6_REG_SD_FIFOW 0x0e
81 #define ICH6_REG_SD_FIFOSIZE 0x10
82 #define ICH6_REG_SD_FORMAT 0x12
83 #define ICH6_REG_SD_BDLPL 0x18
84 #define ICH6_REG_SD_BDLPU 0x1c
85
86 /* PCI space */
87 #define ICH6_PCIREG_TCSEL 0x44
88
89 /*
90 * other constants
91 */
92
93 /* max number of SDs */
94 /* ICH, ATI and VIA have 4 playback and 4 capture */
95 #define ICH6_NUM_CAPTURE 4
96 #define ICH6_NUM_PLAYBACK 4
97
98 /* ULI has 6 playback and 5 capture */
99 #define ULI_NUM_CAPTURE 5
100 #define ULI_NUM_PLAYBACK 6
101
102 /* ATI HDMI has 1 playback and 0 capture */
103 #define ATIHDMI_NUM_CAPTURE 0
104 #define ATIHDMI_NUM_PLAYBACK 1
105
106 /* TERA has 4 playback and 3 capture */
107 #define TERA_NUM_CAPTURE 3
108 #define TERA_NUM_PLAYBACK 4
109
110 /* this number is statically defined for simplicity */
111 #define MAX_AZX_DEV 16
112
113 /* max number of fragments - we may use more if allocating more pages for BDL */
114 #define BDL_SIZE 4096
115 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
116 #define AZX_MAX_FRAG 32
117 /* max buffer size - no h/w limit, you can increase as you like */
118 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
119
120 /* RIRB int mask: overrun[2], response[0] */
121 #define RIRB_INT_RESPONSE 0x01
122 #define RIRB_INT_OVERRUN 0x04
123 #define RIRB_INT_MASK 0x05
124
125 /* STATESTS int mask: S3,SD2,SD1,SD0 */
126 #define AZX_MAX_CODECS 8
127 #define AZX_DEFAULT_CODECS 4
128 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
129
130 /* SD_CTL bits */
131 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
132 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
133 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
134 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
135 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
136 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
137 #define SD_CTL_STREAM_TAG_SHIFT 20
138
139 /* SD_CTL and SD_STS */
140 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
141 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
142 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
143 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
144 SD_INT_COMPLETE)
145
146 /* SD_STS */
147 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
148
149 /* INTCTL and INTSTS */
150 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
151 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
152 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
153
154 /* below are so far hardcoded - should read registers in future */
155 #define ICH6_MAX_CORB_ENTRIES 256
156 #define ICH6_MAX_RIRB_ENTRIES 256
157
158 /* position fix mode */
159 enum {
160 POS_FIX_AUTO,
161 POS_FIX_LPIB,
162 POS_FIX_POSBUF,
163 };
164
165 /* Defines for ATI HD Audio support in SB450 south bridge */
166 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
167 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
168
169 /* Defines for Nvidia HDA support */
170 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
171 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
172 #define NVIDIA_HDA_ISTRM_COH 0x4d
173 #define NVIDIA_HDA_OSTRM_COH 0x4c
174 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
175
176 /* Defines for Intel SCH HDA snoop control */
177 #define INTEL_SCH_HDA_DEVC 0x78
178 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
179
180 /* Define IN stream 0 FIFO size offset in VIA controller */
181 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
182 /* Define VIA HD Audio Device ID*/
183 #define VIA_HDAC_DEVICE_ID 0x3288
184
185 /* HD Audio class code */
186 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
187
188 /* --------------------------------------------------------------------- */
189 /* from linux/sound/pci/hda/hda_codec.h */
190
191 /*
192 * nodes
193 */
194 #define AC_NODE_ROOT 0x00
195
196 /*
197 * function group types
198 */
199 enum {
200 AC_GRP_AUDIO_FUNCTION = 0x01,
201 AC_GRP_MODEM_FUNCTION = 0x02,
202 };
203
204 /*
205 * widget types
206 */
207 enum {
208 AC_WID_AUD_OUT, /* Audio Out */
209 AC_WID_AUD_IN, /* Audio In */
210 AC_WID_AUD_MIX, /* Audio Mixer */
211 AC_WID_AUD_SEL, /* Audio Selector */
212 AC_WID_PIN, /* Pin Complex */
213 AC_WID_POWER, /* Power */
214 AC_WID_VOL_KNB, /* Volume Knob */
215 AC_WID_BEEP, /* Beep Generator */
216 AC_WID_VENDOR = 0x0f /* Vendor specific */
217 };
218
219 /*
220 * GET verbs
221 */
222 #define AC_VERB_GET_STREAM_FORMAT 0x0a00
223 #define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
224 #define AC_VERB_GET_PROC_COEF 0x0c00
225 #define AC_VERB_GET_COEF_INDEX 0x0d00
226 #define AC_VERB_PARAMETERS 0x0f00
227 #define AC_VERB_GET_CONNECT_SEL 0x0f01
228 #define AC_VERB_GET_CONNECT_LIST 0x0f02
229 #define AC_VERB_GET_PROC_STATE 0x0f03
230 #define AC_VERB_GET_SDI_SELECT 0x0f04
231 #define AC_VERB_GET_POWER_STATE 0x0f05
232 #define AC_VERB_GET_CONV 0x0f06
233 #define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
234 #define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
235 #define AC_VERB_GET_PIN_SENSE 0x0f09
236 #define AC_VERB_GET_BEEP_CONTROL 0x0f0a
237 #define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
238 #define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
239 #define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
240 #define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
241 /* f10-f1a: GPIO */
242 #define AC_VERB_GET_GPIO_DATA 0x0f15
243 #define AC_VERB_GET_GPIO_MASK 0x0f16
244 #define AC_VERB_GET_GPIO_DIRECTION 0x0f17
245 #define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
246 #define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
247 #define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
248 #define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
249 /* f20: AFG/MFG */
250 #define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
251 #define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
252 #define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
253 #define AC_VERB_GET_HDMI_ELDD 0x0f2f
254 #define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
255 #define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
256 #define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
257 #define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
258 #define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
259
260 /*
261 * SET verbs
262 */
263 #define AC_VERB_SET_STREAM_FORMAT 0x200
264 #define AC_VERB_SET_AMP_GAIN_MUTE 0x300
265 #define AC_VERB_SET_PROC_COEF 0x400
266 #define AC_VERB_SET_COEF_INDEX 0x500
267 #define AC_VERB_SET_CONNECT_SEL 0x701
268 #define AC_VERB_SET_PROC_STATE 0x703
269 #define AC_VERB_SET_SDI_SELECT 0x704
270 #define AC_VERB_SET_POWER_STATE 0x705
271 #define AC_VERB_SET_CHANNEL_STREAMID 0x706
272 #define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
273 #define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
274 #define AC_VERB_SET_PIN_SENSE 0x709
275 #define AC_VERB_SET_BEEP_CONTROL 0x70a
276 #define AC_VERB_SET_EAPD_BTLENABLE 0x70c
277 #define AC_VERB_SET_DIGI_CONVERT_1 0x70d
278 #define AC_VERB_SET_DIGI_CONVERT_2 0x70e
279 #define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
280 #define AC_VERB_SET_GPIO_DATA 0x715
281 #define AC_VERB_SET_GPIO_MASK 0x716
282 #define AC_VERB_SET_GPIO_DIRECTION 0x717
283 #define AC_VERB_SET_GPIO_WAKE_MASK 0x718
284 #define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
285 #define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
286 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
287 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
288 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
289 #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
290 #define AC_VERB_SET_EAPD 0x788
291 #define AC_VERB_SET_CODEC_RESET 0x7ff
292 #define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
293 #define AC_VERB_SET_HDMI_DIP_INDEX 0x730
294 #define AC_VERB_SET_HDMI_DIP_DATA 0x731
295 #define AC_VERB_SET_HDMI_DIP_XMIT 0x732
296 #define AC_VERB_SET_HDMI_CP_CTRL 0x733
297 #define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
298
299 /*
300 * Parameter IDs
301 */
302 #define AC_PAR_VENDOR_ID 0x00
303 #define AC_PAR_SUBSYSTEM_ID 0x01
304 #define AC_PAR_REV_ID 0x02
305 #define AC_PAR_NODE_COUNT 0x04
306 #define AC_PAR_FUNCTION_TYPE 0x05
307 #define AC_PAR_AUDIO_FG_CAP 0x08
308 #define AC_PAR_AUDIO_WIDGET_CAP 0x09
309 #define AC_PAR_PCM 0x0a
310 #define AC_PAR_STREAM 0x0b
311 #define AC_PAR_PIN_CAP 0x0c
312 #define AC_PAR_AMP_IN_CAP 0x0d
313 #define AC_PAR_CONNLIST_LEN 0x0e
314 #define AC_PAR_POWER_STATE 0x0f
315 #define AC_PAR_PROC_CAP 0x10
316 #define AC_PAR_GPIO_CAP 0x11
317 #define AC_PAR_AMP_OUT_CAP 0x12
318 #define AC_PAR_VOL_KNB_CAP 0x13
319 #define AC_PAR_HDMI_LPCM_CAP 0x20
320
321 /*
322 * AC_VERB_PARAMETERS results (32bit)
323 */
324
325 /* Function Group Type */
326 #define AC_FGT_TYPE (0xff<<0)
327 #define AC_FGT_TYPE_SHIFT 0
328 #define AC_FGT_UNSOL_CAP (1<<8)
329
330 /* Audio Function Group Capabilities */
331 #define AC_AFG_OUT_DELAY (0xf<<0)
332 #define AC_AFG_IN_DELAY (0xf<<8)
333 #define AC_AFG_BEEP_GEN (1<<16)
334
335 /* Audio Widget Capabilities */
336 #define AC_WCAP_STEREO (1<<0) /* stereo I/O */
337 #define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
338 #define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
339 #define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
340 #define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
341 #define AC_WCAP_STRIPE (1<<5) /* stripe */
342 #define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
343 #define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
344 #define AC_WCAP_CONN_LIST (1<<8) /* connection list */
345 #define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
346 #define AC_WCAP_POWER (1<<10) /* power control */
347 #define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
348 #define AC_WCAP_CP_CAPS (1<<12) /* content protection */
349 #define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
350 #define AC_WCAP_DELAY (0xf<<16)
351 #define AC_WCAP_DELAY_SHIFT 16
352 #define AC_WCAP_TYPE (0xf<<20)
353 #define AC_WCAP_TYPE_SHIFT 20
354
355 /* supported PCM rates and bits */
356 #define AC_SUPPCM_RATES (0xfff << 0)
357 #define AC_SUPPCM_BITS_8 (1<<16)
358 #define AC_SUPPCM_BITS_16 (1<<17)
359 #define AC_SUPPCM_BITS_20 (1<<18)
360 #define AC_SUPPCM_BITS_24 (1<<19)
361 #define AC_SUPPCM_BITS_32 (1<<20)
362
363 /* supported PCM stream format */
364 #define AC_SUPFMT_PCM (1<<0)
365 #define AC_SUPFMT_FLOAT32 (1<<1)
366 #define AC_SUPFMT_AC3 (1<<2)
367
368 /* GP I/O count */
369 #define AC_GPIO_IO_COUNT (0xff<<0)
370 #define AC_GPIO_O_COUNT (0xff<<8)
371 #define AC_GPIO_O_COUNT_SHIFT 8
372 #define AC_GPIO_I_COUNT (0xff<<16)
373 #define AC_GPIO_I_COUNT_SHIFT 16
374 #define AC_GPIO_UNSOLICITED (1<<30)
375 #define AC_GPIO_WAKE (1<<31)
376
377 /* Converter stream, channel */
378 #define AC_CONV_CHANNEL (0xf<<0)
379 #define AC_CONV_STREAM (0xf<<4)
380 #define AC_CONV_STREAM_SHIFT 4
381
382 /* Input converter SDI select */
383 #define AC_SDI_SELECT (0xf<<0)
384
385 /* stream format id */
386 #define AC_FMT_CHAN_SHIFT 0
387 #define AC_FMT_CHAN_MASK (0x0f << 0)
388 #define AC_FMT_BITS_SHIFT 4
389 #define AC_FMT_BITS_MASK (7 << 4)
390 #define AC_FMT_BITS_8 (0 << 4)
391 #define AC_FMT_BITS_16 (1 << 4)
392 #define AC_FMT_BITS_20 (2 << 4)
393 #define AC_FMT_BITS_24 (3 << 4)
394 #define AC_FMT_BITS_32 (4 << 4)
395 #define AC_FMT_DIV_SHIFT 8
396 #define AC_FMT_DIV_MASK (7 << 8)
397 #define AC_FMT_MULT_SHIFT 11
398 #define AC_FMT_MULT_MASK (7 << 11)
399 #define AC_FMT_BASE_SHIFT 14
400 #define AC_FMT_BASE_48K (0 << 14)
401 #define AC_FMT_BASE_44K (1 << 14)
402 #define AC_FMT_TYPE_SHIFT 15
403 #define AC_FMT_TYPE_PCM (0 << 15)
404 #define AC_FMT_TYPE_NON_PCM (1 << 15)
405
406 /* Unsolicited response control */
407 #define AC_UNSOL_TAG (0x3f<<0)
408 #define AC_UNSOL_ENABLED (1<<7)
409 #define AC_USRSP_EN AC_UNSOL_ENABLED
410
411 /* Unsolicited responses */
412 #define AC_UNSOL_RES_TAG (0x3f<<26)
413 #define AC_UNSOL_RES_TAG_SHIFT 26
414 #define AC_UNSOL_RES_SUBTAG (0x1f<<21)
415 #define AC_UNSOL_RES_SUBTAG_SHIFT 21
416 #define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
417 #define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
418 #define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
419 #define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
420
421 /* Pin widget capabilies */
422 #define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
423 #define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
424 #define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
425 #define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
426 #define AC_PINCAP_OUT (1<<4) /* output capable */
427 #define AC_PINCAP_IN (1<<5) /* input capable */
428 #define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
429 /* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
430 * but is marked reserved in the Intel HDA specification.
431 */
432 #define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
433 /* Note: The same bit as LR_SWAP is newly defined as HDMI capability
434 * in HD-audio specification
435 */
436 #define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
437 #define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can
438 * coexist with AC_PINCAP_HDMI
439 */
440 #define AC_PINCAP_VREF (0x37<<8)
441 #define AC_PINCAP_VREF_SHIFT 8
442 #define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
443 #define AC_PINCAP_HBR (1<<27) /* High Bit Rate */
444 /* Vref status (used in pin cap) */
445 #define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
446 #define AC_PINCAP_VREF_50 (1<<1) /* 50% */
447 #define AC_PINCAP_VREF_GRD (1<<2) /* ground */
448 #define AC_PINCAP_VREF_80 (1<<4) /* 80% */
449 #define AC_PINCAP_VREF_100 (1<<5) /* 100% */
450
451 /* Amplifier capabilities */
452 #define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
453 #define AC_AMPCAP_OFFSET_SHIFT 0
454 #define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
455 #define AC_AMPCAP_NUM_STEPS_SHIFT 8
456 #define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
457 * in 0.25dB
458 */
459 #define AC_AMPCAP_STEP_SIZE_SHIFT 16
460 #define AC_AMPCAP_MUTE (1<<31) /* mute capable */
461 #define AC_AMPCAP_MUTE_SHIFT 31
462
463 /* Connection list */
464 #define AC_CLIST_LENGTH (0x7f<<0)
465 #define AC_CLIST_LONG (1<<7)
466
467 /* Supported power status */
468 #define AC_PWRST_D0SUP (1<<0)
469 #define AC_PWRST_D1SUP (1<<1)
470 #define AC_PWRST_D2SUP (1<<2)
471 #define AC_PWRST_D3SUP (1<<3)
472 #define AC_PWRST_D3COLDSUP (1<<4)
473 #define AC_PWRST_S3D3COLDSUP (1<<29)
474 #define AC_PWRST_CLKSTOP (1<<30)
475 #define AC_PWRST_EPSS (1U<<31)
476
477 /* Power state values */
478 #define AC_PWRST_SETTING (0xf<<0)
479 #define AC_PWRST_ACTUAL (0xf<<4)
480 #define AC_PWRST_ACTUAL_SHIFT 4
481 #define AC_PWRST_D0 0x00
482 #define AC_PWRST_D1 0x01
483 #define AC_PWRST_D2 0x02
484 #define AC_PWRST_D3 0x03
485
486 /* Processing capabilies */
487 #define AC_PCAP_BENIGN (1<<0)
488 #define AC_PCAP_NUM_COEF (0xff<<8)
489 #define AC_PCAP_NUM_COEF_SHIFT 8
490
491 /* Volume knobs capabilities */
492 #define AC_KNBCAP_NUM_STEPS (0x7f<<0)
493 #define AC_KNBCAP_DELTA (1<<7)
494
495 /* HDMI LPCM capabilities */
496 #define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
497 #define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
498 #define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
499 #define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
500 #define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
501 #define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
502 #define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
503 #define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
504 #define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
505 #define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
506 #define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
507 #define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
508 #define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
509 #define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
510
511 /*
512 * Control Parameters
513 */
514
515 /* Amp gain/mute */
516 #define AC_AMP_MUTE (1<<7)
517 #define AC_AMP_GAIN (0x7f)
518 #define AC_AMP_GET_INDEX (0xf<<0)
519
520 #define AC_AMP_GET_LEFT (1<<13)
521 #define AC_AMP_GET_RIGHT (0<<13)
522 #define AC_AMP_GET_OUTPUT (1<<15)
523 #define AC_AMP_GET_INPUT (0<<15)
524
525 #define AC_AMP_SET_INDEX (0xf<<8)
526 #define AC_AMP_SET_INDEX_SHIFT 8
527 #define AC_AMP_SET_RIGHT (1<<12)
528 #define AC_AMP_SET_LEFT (1<<13)
529 #define AC_AMP_SET_INPUT (1<<14)
530 #define AC_AMP_SET_OUTPUT (1<<15)
531
532 /* DIGITAL1 bits */
533 #define AC_DIG1_ENABLE (1<<0)
534 #define AC_DIG1_V (1<<1)
535 #define AC_DIG1_VCFG (1<<2)
536 #define AC_DIG1_EMPHASIS (1<<3)
537 #define AC_DIG1_COPYRIGHT (1<<4)
538 #define AC_DIG1_NONAUDIO (1<<5)
539 #define AC_DIG1_PROFESSIONAL (1<<6)
540 #define AC_DIG1_LEVEL (1<<7)
541
542 /* DIGITAL2 bits */
543 #define AC_DIG2_CC (0x7f<<0)
544
545 /* Pin widget control - 8bit */
546 #define AC_PINCTL_EPT (0x3<<0)
547 #define AC_PINCTL_EPT_NATIVE 0
548 #define AC_PINCTL_EPT_HBR 3
549 #define AC_PINCTL_VREFEN (0x7<<0)
550 #define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
551 #define AC_PINCTL_VREF_50 1 /* 50% */
552 #define AC_PINCTL_VREF_GRD 2 /* ground */
553 #define AC_PINCTL_VREF_80 4 /* 80% */
554 #define AC_PINCTL_VREF_100 5 /* 100% */
555 #define AC_PINCTL_IN_EN (1<<5)
556 #define AC_PINCTL_OUT_EN (1<<6)
557 #define AC_PINCTL_HP_EN (1<<7)
558
559 /* Pin sense - 32bit */
560 #define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
561 #define AC_PINSENSE_PRESENCE (1<<31)
562 #define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
563
564 /* EAPD/BTL enable - 32bit */
565 #define AC_EAPDBTL_BALANCED (1<<0)
566 #define AC_EAPDBTL_EAPD (1<<1)
567 #define AC_EAPDBTL_LR_SWAP (1<<2)
568
569 /* HDMI ELD data */
570 #define AC_ELDD_ELD_VALID (1<<31)
571 #define AC_ELDD_ELD_DATA 0xff
572
573 /* HDMI DIP size */
574 #define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
575 #define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
576
577 /* HDMI DIP index */
578 #define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
579 #define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
580
581 /* HDMI DIP xmit (transmit) control */
582 #define AC_DIPXMIT_MASK (0x3<<6)
583 #define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
584 #define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
585 #define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
586
587 /* HDMI content protection (CP) control */
588 #define AC_CPCTRL_CES (1<<9) /* current encryption state */
589 #define AC_CPCTRL_READY (1<<8) /* ready bit */
590 #define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
591 #define AC_CPCTRL_STATE (3<<0) /* current CP request state */
592
593 /* Converter channel <-> HDMI slot mapping */
594 #define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
595 #define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
596
597 /* configuration default - 32bit */
598 #define AC_DEFCFG_SEQUENCE (0xf<<0)
599 #define AC_DEFCFG_DEF_ASSOC (0xf<<4)
600 #define AC_DEFCFG_ASSOC_SHIFT 4
601 #define AC_DEFCFG_MISC (0xf<<8)
602 #define AC_DEFCFG_MISC_SHIFT 8
603 #define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
604 #define AC_DEFCFG_COLOR (0xf<<12)
605 #define AC_DEFCFG_COLOR_SHIFT 12
606 #define AC_DEFCFG_CONN_TYPE (0xf<<16)
607 #define AC_DEFCFG_CONN_TYPE_SHIFT 16
608 #define AC_DEFCFG_DEVICE (0xf<<20)
609 #define AC_DEFCFG_DEVICE_SHIFT 20
610 #define AC_DEFCFG_LOCATION (0x3f<<24)
611 #define AC_DEFCFG_LOCATION_SHIFT 24
612 #define AC_DEFCFG_PORT_CONN (0x3<<30)
613 #define AC_DEFCFG_PORT_CONN_SHIFT 30
614
615 /* device device types (0x0-0xf) */
616 enum {
617 AC_JACK_LINE_OUT,
618 AC_JACK_SPEAKER,
619 AC_JACK_HP_OUT,
620 AC_JACK_CD,
621 AC_JACK_SPDIF_OUT,
622 AC_JACK_DIG_OTHER_OUT,
623 AC_JACK_MODEM_LINE_SIDE,
624 AC_JACK_MODEM_HAND_SIDE,
625 AC_JACK_LINE_IN,
626 AC_JACK_AUX,
627 AC_JACK_MIC_IN,
628 AC_JACK_TELEPHONY,
629 AC_JACK_SPDIF_IN,
630 AC_JACK_DIG_OTHER_IN,
631 AC_JACK_OTHER = 0xf,
632 };
633
634 /* jack connection types (0x0-0xf) */
635 enum {
636 AC_JACK_CONN_UNKNOWN,
637 AC_JACK_CONN_1_8,
638 AC_JACK_CONN_1_4,
639 AC_JACK_CONN_ATAPI,
640 AC_JACK_CONN_RCA,
641 AC_JACK_CONN_OPTICAL,
642 AC_JACK_CONN_OTHER_DIGITAL,
643 AC_JACK_CONN_OTHER_ANALOG,
644 AC_JACK_CONN_DIN,
645 AC_JACK_CONN_XLR,
646 AC_JACK_CONN_RJ11,
647 AC_JACK_CONN_COMB,
648 AC_JACK_CONN_OTHER = 0xf,
649 };
650
651 /* jack colors (0x0-0xf) */
652 enum {
653 AC_JACK_COLOR_UNKNOWN,
654 AC_JACK_COLOR_BLACK,
655 AC_JACK_COLOR_GREY,
656 AC_JACK_COLOR_BLUE,
657 AC_JACK_COLOR_GREEN,
658 AC_JACK_COLOR_RED,
659 AC_JACK_COLOR_ORANGE,
660 AC_JACK_COLOR_YELLOW,
661 AC_JACK_COLOR_PURPLE,
662 AC_JACK_COLOR_PINK,
663 AC_JACK_COLOR_WHITE = 0xe,
664 AC_JACK_COLOR_OTHER,
665 };
666
667 /* Jack location (0x0-0x3f) */
668 /* common case */
669 enum {
670 AC_JACK_LOC_NONE,
671 AC_JACK_LOC_REAR,
672 AC_JACK_LOC_FRONT,
673 AC_JACK_LOC_LEFT,
674 AC_JACK_LOC_RIGHT,
675 AC_JACK_LOC_TOP,
676 AC_JACK_LOC_BOTTOM,
677 };
678 /* bits 4-5 */
679 enum {
680 AC_JACK_LOC_EXTERNAL = 0x00,
681 AC_JACK_LOC_INTERNAL = 0x10,
682 AC_JACK_LOC_SEPARATE = 0x20,
683 AC_JACK_LOC_OTHER = 0x30,
684 };
685 enum {
686 /* external on primary chasis */
687 AC_JACK_LOC_REAR_PANEL = 0x07,
688 AC_JACK_LOC_DRIVE_BAY,
689 /* internal */
690 AC_JACK_LOC_RISER = 0x17,
691 AC_JACK_LOC_HDMI,
692 AC_JACK_LOC_ATAPI,
693 /* others */
694 AC_JACK_LOC_MOBILE_IN = 0x37,
695 AC_JACK_LOC_MOBILE_OUT,
696 };
697
698 /* Port connectivity (0-3) */
699 enum {
700 AC_JACK_PORT_COMPLEX,
701 AC_JACK_PORT_NONE,
702 AC_JACK_PORT_FIXED,
703 AC_JACK_PORT_BOTH,
704 };
705
706 /* max. connections to a widget */
707 #define HDA_MAX_CONNECTIONS 32
708
709 /* max. codec address */
710 #define HDA_MAX_CODEC_ADDRESS 0x0f
711
712 /* max number of PCM devics per card */
713 #define HDA_MAX_PCMS 10
714
715 /* --------------------------------------------------------------------- */
716
717 #endif