hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / isa / piix3.c
1 /*
2 * QEMU PIIX PCI ISA Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/range.h"
27 #include "hw/southbridge/piix.h"
28 #include "hw/irq.h"
29 #include "hw/isa/isa.h"
30 #include "hw/xen/xen.h"
31 #include "sysemu/xen.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/reset.h"
34 #include "sysemu/runstate.h"
35 #include "migration/vmstate.h"
36
37 #define XEN_PIIX_NUM_PIRQS 128ULL
38
39 #define TYPE_PIIX3_DEVICE "PIIX3"
40 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
41
42 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
43 {
44 qemu_set_irq(piix3->pic[pic_irq],
45 !!(piix3->pic_levels &
46 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
47 (pic_irq * PIIX_NUM_PIRQS))));
48 }
49
50 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
51 {
52 int pic_irq;
53 uint64_t mask;
54
55 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
56 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
57 return;
58 }
59
60 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
61 piix3->pic_levels &= ~mask;
62 piix3->pic_levels |= mask * !!level;
63 }
64
65 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
66 {
67 int pic_irq;
68
69 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
70 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
71 return;
72 }
73
74 piix3_set_irq_level_internal(piix3, pirq, level);
75
76 piix3_set_irq_pic(piix3, pic_irq);
77 }
78
79 static void piix3_set_irq(void *opaque, int pirq, int level)
80 {
81 PIIX3State *piix3 = opaque;
82 piix3_set_irq_level(piix3, pirq, level);
83 }
84
85 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
86 {
87 PIIX3State *piix3 = opaque;
88 int irq = piix3->dev.config[PIIX_PIRQCA + pin];
89 PCIINTxRoute route;
90
91 if (irq < PIIX_NUM_PIC_IRQS) {
92 route.mode = PCI_INTX_ENABLED;
93 route.irq = irq;
94 } else {
95 route.mode = PCI_INTX_DISABLED;
96 route.irq = -1;
97 }
98 return route;
99 }
100
101 /* irq routing is changed. so rebuild bitmap */
102 static void piix3_update_irq_levels(PIIX3State *piix3)
103 {
104 PCIBus *bus = pci_get_bus(&piix3->dev);
105 int pirq;
106
107 piix3->pic_levels = 0;
108 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
109 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
110 }
111 }
112
113 static void piix3_write_config(PCIDevice *dev,
114 uint32_t address, uint32_t val, int len)
115 {
116 pci_default_write_config(dev, address, val, len);
117 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
118 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
119 int pic_irq;
120
121 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
122 piix3_update_irq_levels(piix3);
123 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
124 piix3_set_irq_pic(piix3, pic_irq);
125 }
126 }
127 }
128
129 static void piix3_write_config_xen(PCIDevice *dev,
130 uint32_t address, uint32_t val, int len)
131 {
132 xen_piix_pci_write_config_client(address, val, len);
133 piix3_write_config(dev, address, val, len);
134 }
135
136 static void piix3_reset(void *opaque)
137 {
138 PIIX3State *d = opaque;
139 uint8_t *pci_conf = d->dev.config;
140
141 pci_conf[0x04] = 0x07; /* master, memory and I/O */
142 pci_conf[0x05] = 0x00;
143 pci_conf[0x06] = 0x00;
144 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
145 pci_conf[0x4c] = 0x4d;
146 pci_conf[0x4e] = 0x03;
147 pci_conf[0x4f] = 0x00;
148 pci_conf[0x60] = 0x80;
149 pci_conf[0x61] = 0x80;
150 pci_conf[0x62] = 0x80;
151 pci_conf[0x63] = 0x80;
152 pci_conf[0x69] = 0x02;
153 pci_conf[0x70] = 0x80;
154 pci_conf[0x76] = 0x0c;
155 pci_conf[0x77] = 0x0c;
156 pci_conf[0x78] = 0x02;
157 pci_conf[0x79] = 0x00;
158 pci_conf[0x80] = 0x00;
159 pci_conf[0x82] = 0x00;
160 pci_conf[0xa0] = 0x08;
161 pci_conf[0xa2] = 0x00;
162 pci_conf[0xa3] = 0x00;
163 pci_conf[0xa4] = 0x00;
164 pci_conf[0xa5] = 0x00;
165 pci_conf[0xa6] = 0x00;
166 pci_conf[0xa7] = 0x00;
167 pci_conf[0xa8] = 0x0f;
168 pci_conf[0xaa] = 0x00;
169 pci_conf[0xab] = 0x00;
170 pci_conf[0xac] = 0x00;
171 pci_conf[0xae] = 0x00;
172
173 d->pic_levels = 0;
174 d->rcr = 0;
175 }
176
177 static int piix3_post_load(void *opaque, int version_id)
178 {
179 PIIX3State *piix3 = opaque;
180 int pirq;
181
182 /*
183 * Because the i8259 has not been deserialized yet, qemu_irq_raise
184 * might bring the system to a different state than the saved one;
185 * for example, the interrupt could be masked but the i8259 would
186 * not know that yet and would trigger an interrupt in the CPU.
187 *
188 * Here, we update irq levels without raising the interrupt.
189 * Interrupt state will be deserialized separately through the i8259.
190 */
191 piix3->pic_levels = 0;
192 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
193 piix3_set_irq_level_internal(piix3, pirq,
194 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
195 }
196 return 0;
197 }
198
199 static int piix3_pre_save(void *opaque)
200 {
201 int i;
202 PIIX3State *piix3 = opaque;
203
204 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
205 piix3->pci_irq_levels_vmstate[i] =
206 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
207 }
208
209 return 0;
210 }
211
212 static bool piix3_rcr_needed(void *opaque)
213 {
214 PIIX3State *piix3 = opaque;
215
216 return (piix3->rcr != 0);
217 }
218
219 static const VMStateDescription vmstate_piix3_rcr = {
220 .name = "PIIX3/rcr",
221 .version_id = 1,
222 .minimum_version_id = 1,
223 .needed = piix3_rcr_needed,
224 .fields = (VMStateField[]) {
225 VMSTATE_UINT8(rcr, PIIX3State),
226 VMSTATE_END_OF_LIST()
227 }
228 };
229
230 static const VMStateDescription vmstate_piix3 = {
231 .name = "PIIX3",
232 .version_id = 3,
233 .minimum_version_id = 2,
234 .post_load = piix3_post_load,
235 .pre_save = piix3_pre_save,
236 .fields = (VMStateField[]) {
237 VMSTATE_PCI_DEVICE(dev, PIIX3State),
238 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
239 PIIX_NUM_PIRQS, 3),
240 VMSTATE_END_OF_LIST()
241 },
242 .subsections = (const VMStateDescription*[]) {
243 &vmstate_piix3_rcr,
244 NULL
245 }
246 };
247
248
249 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
250 {
251 PIIX3State *d = opaque;
252
253 if (val & 4) {
254 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
255 return;
256 }
257 d->rcr = val & 2; /* keep System Reset type only */
258 }
259
260 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
261 {
262 PIIX3State *d = opaque;
263
264 return d->rcr;
265 }
266
267 static const MemoryRegionOps rcr_ops = {
268 .read = rcr_read,
269 .write = rcr_write,
270 .endianness = DEVICE_LITTLE_ENDIAN
271 };
272
273 static void piix3_realize(PCIDevice *dev, Error **errp)
274 {
275 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
276
277 if (!isa_bus_new(DEVICE(d), get_system_memory(),
278 pci_address_space_io(dev), errp)) {
279 return;
280 }
281
282 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
283 "piix3-reset-control", 1);
284 memory_region_add_subregion_overlap(pci_address_space_io(dev),
285 PIIX_RCR_IOPORT, &d->rcr_mem, 1);
286
287 qemu_register_reset(piix3_reset, d);
288 }
289
290 static void pci_piix3_class_init(ObjectClass *klass, void *data)
291 {
292 DeviceClass *dc = DEVICE_CLASS(klass);
293 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
294
295 dc->desc = "ISA bridge";
296 dc->vmsd = &vmstate_piix3;
297 dc->hotpluggable = false;
298 k->realize = piix3_realize;
299 k->vendor_id = PCI_VENDOR_ID_INTEL;
300 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
301 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
302 k->class_id = PCI_CLASS_BRIDGE_ISA;
303 /*
304 * Reason: part of PIIX3 southbridge, needs to be wired up by
305 * pc_piix.c's pc_init1()
306 */
307 dc->user_creatable = false;
308 }
309
310 static const TypeInfo piix3_pci_type_info = {
311 .name = TYPE_PIIX3_PCI_DEVICE,
312 .parent = TYPE_PCI_DEVICE,
313 .instance_size = sizeof(PIIX3State),
314 .abstract = true,
315 .class_init = pci_piix3_class_init,
316 .interfaces = (InterfaceInfo[]) {
317 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
318 { },
319 },
320 };
321
322 static void piix3_class_init(ObjectClass *klass, void *data)
323 {
324 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
325
326 k->config_write = piix3_write_config;
327 }
328
329 static const TypeInfo piix3_info = {
330 .name = TYPE_PIIX3_DEVICE,
331 .parent = TYPE_PIIX3_PCI_DEVICE,
332 .class_init = piix3_class_init,
333 };
334
335 static void piix3_xen_class_init(ObjectClass *klass, void *data)
336 {
337 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
338
339 k->config_write = piix3_write_config_xen;
340 };
341
342 static const TypeInfo piix3_xen_info = {
343 .name = TYPE_PIIX3_XEN_DEVICE,
344 .parent = TYPE_PIIX3_PCI_DEVICE,
345 .class_init = piix3_xen_class_init,
346 };
347
348 static void piix3_register_types(void)
349 {
350 type_register_static(&piix3_pci_type_info);
351 type_register_static(&piix3_info);
352 type_register_static(&piix3_xen_info);
353 }
354
355 type_init(piix3_register_types)
356
357 /*
358 * Return the global irq number corresponding to a given device irq
359 * pin. We could also use the bus number to have a more precise mapping.
360 */
361 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
362 {
363 int slot_addend;
364 slot_addend = (pci_dev->devfn >> 3) - 1;
365 return (pci_intx + slot_addend) & 3;
366 }
367
368 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
369 {
370 PIIX3State *piix3;
371 PCIDevice *pci_dev;
372
373 /*
374 * Xen supports additional interrupt routes from the PCI devices to
375 * the IOAPIC: the four pins of each PCI device on the bus are also
376 * connected to the IOAPIC directly.
377 * These additional routes can be discovered through ACPI.
378 */
379 if (xen_enabled()) {
380 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
381 TYPE_PIIX3_XEN_DEVICE);
382 piix3 = PIIX3_PCI_DEVICE(pci_dev);
383 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
384 piix3, XEN_PIIX_NUM_PIRQS);
385 } else {
386 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
387 TYPE_PIIX3_DEVICE);
388 piix3 = PIIX3_PCI_DEVICE(pci_dev);
389 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
390 piix3, PIIX_NUM_PIRQS);
391 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
392 }
393 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
394
395 return piix3;
396 }