target/ppc: Fix slbia TLB invalidation gap
[qemu.git] / hw / isa / piix3.c
1 /*
2 * QEMU PIIX PCI ISA Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/range.h"
27 #include "hw/southbridge/piix.h"
28 #include "hw/irq.h"
29 #include "hw/isa/isa.h"
30 #include "hw/xen/xen.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/reset.h"
33 #include "sysemu/runstate.h"
34 #include "migration/vmstate.h"
35
36 #define XEN_PIIX_NUM_PIRQS 128ULL
37
38 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
39 #define PIIX3_PCI_DEVICE(obj) \
40 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
41
42 #define TYPE_PIIX3_DEVICE "PIIX3"
43 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
44
45 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
46 {
47 qemu_set_irq(piix3->pic[pic_irq],
48 !!(piix3->pic_levels &
49 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
50 (pic_irq * PIIX_NUM_PIRQS))));
51 }
52
53 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
54 {
55 int pic_irq;
56 uint64_t mask;
57
58 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
59 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
60 return;
61 }
62
63 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
64 piix3->pic_levels &= ~mask;
65 piix3->pic_levels |= mask * !!level;
66 }
67
68 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
69 {
70 int pic_irq;
71
72 pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
73 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
74 return;
75 }
76
77 piix3_set_irq_level_internal(piix3, pirq, level);
78
79 piix3_set_irq_pic(piix3, pic_irq);
80 }
81
82 static void piix3_set_irq(void *opaque, int pirq, int level)
83 {
84 PIIX3State *piix3 = opaque;
85 piix3_set_irq_level(piix3, pirq, level);
86 }
87
88 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
89 {
90 PIIX3State *piix3 = opaque;
91 int irq = piix3->dev.config[PIIX_PIRQCA + pin];
92 PCIINTxRoute route;
93
94 if (irq < PIIX_NUM_PIC_IRQS) {
95 route.mode = PCI_INTX_ENABLED;
96 route.irq = irq;
97 } else {
98 route.mode = PCI_INTX_DISABLED;
99 route.irq = -1;
100 }
101 return route;
102 }
103
104 /* irq routing is changed. so rebuild bitmap */
105 static void piix3_update_irq_levels(PIIX3State *piix3)
106 {
107 PCIBus *bus = pci_get_bus(&piix3->dev);
108 int pirq;
109
110 piix3->pic_levels = 0;
111 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
112 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
113 }
114 }
115
116 static void piix3_write_config(PCIDevice *dev,
117 uint32_t address, uint32_t val, int len)
118 {
119 pci_default_write_config(dev, address, val, len);
120 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
121 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
122 int pic_irq;
123
124 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
125 piix3_update_irq_levels(piix3);
126 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
127 piix3_set_irq_pic(piix3, pic_irq);
128 }
129 }
130 }
131
132 static void piix3_write_config_xen(PCIDevice *dev,
133 uint32_t address, uint32_t val, int len)
134 {
135 xen_piix_pci_write_config_client(address, val, len);
136 piix3_write_config(dev, address, val, len);
137 }
138
139 static void piix3_reset(void *opaque)
140 {
141 PIIX3State *d = opaque;
142 uint8_t *pci_conf = d->dev.config;
143
144 pci_conf[0x04] = 0x07; /* master, memory and I/O */
145 pci_conf[0x05] = 0x00;
146 pci_conf[0x06] = 0x00;
147 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
148 pci_conf[0x4c] = 0x4d;
149 pci_conf[0x4e] = 0x03;
150 pci_conf[0x4f] = 0x00;
151 pci_conf[0x60] = 0x80;
152 pci_conf[0x61] = 0x80;
153 pci_conf[0x62] = 0x80;
154 pci_conf[0x63] = 0x80;
155 pci_conf[0x69] = 0x02;
156 pci_conf[0x70] = 0x80;
157 pci_conf[0x76] = 0x0c;
158 pci_conf[0x77] = 0x0c;
159 pci_conf[0x78] = 0x02;
160 pci_conf[0x79] = 0x00;
161 pci_conf[0x80] = 0x00;
162 pci_conf[0x82] = 0x00;
163 pci_conf[0xa0] = 0x08;
164 pci_conf[0xa2] = 0x00;
165 pci_conf[0xa3] = 0x00;
166 pci_conf[0xa4] = 0x00;
167 pci_conf[0xa5] = 0x00;
168 pci_conf[0xa6] = 0x00;
169 pci_conf[0xa7] = 0x00;
170 pci_conf[0xa8] = 0x0f;
171 pci_conf[0xaa] = 0x00;
172 pci_conf[0xab] = 0x00;
173 pci_conf[0xac] = 0x00;
174 pci_conf[0xae] = 0x00;
175
176 d->pic_levels = 0;
177 d->rcr = 0;
178 }
179
180 static int piix3_post_load(void *opaque, int version_id)
181 {
182 PIIX3State *piix3 = opaque;
183 int pirq;
184
185 /*
186 * Because the i8259 has not been deserialized yet, qemu_irq_raise
187 * might bring the system to a different state than the saved one;
188 * for example, the interrupt could be masked but the i8259 would
189 * not know that yet and would trigger an interrupt in the CPU.
190 *
191 * Here, we update irq levels without raising the interrupt.
192 * Interrupt state will be deserialized separately through the i8259.
193 */
194 piix3->pic_levels = 0;
195 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
196 piix3_set_irq_level_internal(piix3, pirq,
197 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
198 }
199 return 0;
200 }
201
202 static int piix3_pre_save(void *opaque)
203 {
204 int i;
205 PIIX3State *piix3 = opaque;
206
207 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
208 piix3->pci_irq_levels_vmstate[i] =
209 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
210 }
211
212 return 0;
213 }
214
215 static bool piix3_rcr_needed(void *opaque)
216 {
217 PIIX3State *piix3 = opaque;
218
219 return (piix3->rcr != 0);
220 }
221
222 static const VMStateDescription vmstate_piix3_rcr = {
223 .name = "PIIX3/rcr",
224 .version_id = 1,
225 .minimum_version_id = 1,
226 .needed = piix3_rcr_needed,
227 .fields = (VMStateField[]) {
228 VMSTATE_UINT8(rcr, PIIX3State),
229 VMSTATE_END_OF_LIST()
230 }
231 };
232
233 static const VMStateDescription vmstate_piix3 = {
234 .name = "PIIX3",
235 .version_id = 3,
236 .minimum_version_id = 2,
237 .post_load = piix3_post_load,
238 .pre_save = piix3_pre_save,
239 .fields = (VMStateField[]) {
240 VMSTATE_PCI_DEVICE(dev, PIIX3State),
241 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
242 PIIX_NUM_PIRQS, 3),
243 VMSTATE_END_OF_LIST()
244 },
245 .subsections = (const VMStateDescription*[]) {
246 &vmstate_piix3_rcr,
247 NULL
248 }
249 };
250
251
252 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
253 {
254 PIIX3State *d = opaque;
255
256 if (val & 4) {
257 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
258 return;
259 }
260 d->rcr = val & 2; /* keep System Reset type only */
261 }
262
263 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
264 {
265 PIIX3State *d = opaque;
266
267 return d->rcr;
268 }
269
270 static const MemoryRegionOps rcr_ops = {
271 .read = rcr_read,
272 .write = rcr_write,
273 .endianness = DEVICE_LITTLE_ENDIAN
274 };
275
276 static void piix3_realize(PCIDevice *dev, Error **errp)
277 {
278 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
279
280 if (!isa_bus_new(DEVICE(d), get_system_memory(),
281 pci_address_space_io(dev), errp)) {
282 return;
283 }
284
285 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
286 "piix3-reset-control", 1);
287 memory_region_add_subregion_overlap(pci_address_space_io(dev),
288 PIIX_RCR_IOPORT, &d->rcr_mem, 1);
289
290 qemu_register_reset(piix3_reset, d);
291 }
292
293 static void pci_piix3_class_init(ObjectClass *klass, void *data)
294 {
295 DeviceClass *dc = DEVICE_CLASS(klass);
296 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
297
298 dc->desc = "ISA bridge";
299 dc->vmsd = &vmstate_piix3;
300 dc->hotpluggable = false;
301 k->realize = piix3_realize;
302 k->vendor_id = PCI_VENDOR_ID_INTEL;
303 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
304 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
305 k->class_id = PCI_CLASS_BRIDGE_ISA;
306 /*
307 * Reason: part of PIIX3 southbridge, needs to be wired up by
308 * pc_piix.c's pc_init1()
309 */
310 dc->user_creatable = false;
311 }
312
313 static const TypeInfo piix3_pci_type_info = {
314 .name = TYPE_PIIX3_PCI_DEVICE,
315 .parent = TYPE_PCI_DEVICE,
316 .instance_size = sizeof(PIIX3State),
317 .abstract = true,
318 .class_init = pci_piix3_class_init,
319 .interfaces = (InterfaceInfo[]) {
320 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
321 { },
322 },
323 };
324
325 static void piix3_class_init(ObjectClass *klass, void *data)
326 {
327 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
328
329 k->config_write = piix3_write_config;
330 }
331
332 static const TypeInfo piix3_info = {
333 .name = TYPE_PIIX3_DEVICE,
334 .parent = TYPE_PIIX3_PCI_DEVICE,
335 .class_init = piix3_class_init,
336 };
337
338 static void piix3_xen_class_init(ObjectClass *klass, void *data)
339 {
340 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
341
342 k->config_write = piix3_write_config_xen;
343 };
344
345 static const TypeInfo piix3_xen_info = {
346 .name = TYPE_PIIX3_XEN_DEVICE,
347 .parent = TYPE_PIIX3_PCI_DEVICE,
348 .class_init = piix3_xen_class_init,
349 };
350
351 static void piix3_register_types(void)
352 {
353 type_register_static(&piix3_pci_type_info);
354 type_register_static(&piix3_info);
355 type_register_static(&piix3_xen_info);
356 }
357
358 type_init(piix3_register_types)
359
360 /*
361 * Return the global irq number corresponding to a given device irq
362 * pin. We could also use the bus number to have a more precise mapping.
363 */
364 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
365 {
366 int slot_addend;
367 slot_addend = (pci_dev->devfn >> 3) - 1;
368 return (pci_intx + slot_addend) & 3;
369 }
370
371 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
372 {
373 PIIX3State *piix3;
374 PCIDevice *pci_dev;
375
376 /*
377 * Xen supports additional interrupt routes from the PCI devices to
378 * the IOAPIC: the four pins of each PCI device on the bus are also
379 * connected to the IOAPIC directly.
380 * These additional routes can be discovered through ACPI.
381 */
382 if (xen_enabled()) {
383 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
384 TYPE_PIIX3_XEN_DEVICE);
385 piix3 = PIIX3_PCI_DEVICE(pci_dev);
386 pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
387 piix3, XEN_PIIX_NUM_PIRQS);
388 } else {
389 pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
390 TYPE_PIIX3_DEVICE);
391 piix3 = PIIX3_PCI_DEVICE(pci_dev);
392 pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
393 piix3, PIIX_NUM_PIRQS);
394 pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
395 }
396 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
397
398 return piix3;
399 }