hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / isa / piix4.c
1 /*
2 * QEMU PIIX4 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2018 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/irq.h"
29 #include "hw/southbridge/piix.h"
30 #include "hw/pci/pci.h"
31 #include "hw/isa/isa.h"
32 #include "hw/sysbus.h"
33 #include "hw/intc/i8259.h"
34 #include "hw/dma/i8257.h"
35 #include "hw/timer/i8254.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "hw/ide/pci.h"
38 #include "migration/vmstate.h"
39 #include "sysemu/reset.h"
40 #include "sysemu/runstate.h"
41 #include "qom/object.h"
42
43 PCIDevice *piix4_dev;
44
45 struct PIIX4State {
46 PCIDevice dev;
47 qemu_irq cpu_intr;
48 qemu_irq *isa;
49
50 RTCState rtc;
51 /* Reset Control Register */
52 MemoryRegion rcr_mem;
53 uint8_t rcr;
54 };
55
56 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
57
58 static void piix4_isa_reset(DeviceState *dev)
59 {
60 PIIX4State *d = PIIX4_PCI_DEVICE(dev);
61 uint8_t *pci_conf = d->dev.config;
62
63 pci_conf[0x04] = 0x07; // master, memory and I/O
64 pci_conf[0x05] = 0x00;
65 pci_conf[0x06] = 0x00;
66 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
67 pci_conf[0x4c] = 0x4d;
68 pci_conf[0x4e] = 0x03;
69 pci_conf[0x4f] = 0x00;
70 pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
71 pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
72 pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
73 pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
74 pci_conf[0x69] = 0x02;
75 pci_conf[0x70] = 0x80;
76 pci_conf[0x76] = 0x0c;
77 pci_conf[0x77] = 0x0c;
78 pci_conf[0x78] = 0x02;
79 pci_conf[0x79] = 0x00;
80 pci_conf[0x80] = 0x00;
81 pci_conf[0x82] = 0x00;
82 pci_conf[0xa0] = 0x08;
83 pci_conf[0xa2] = 0x00;
84 pci_conf[0xa3] = 0x00;
85 pci_conf[0xa4] = 0x00;
86 pci_conf[0xa5] = 0x00;
87 pci_conf[0xa6] = 0x00;
88 pci_conf[0xa7] = 0x00;
89 pci_conf[0xa8] = 0x0f;
90 pci_conf[0xaa] = 0x00;
91 pci_conf[0xab] = 0x00;
92 pci_conf[0xac] = 0x00;
93 pci_conf[0xae] = 0x00;
94 }
95
96 static const VMStateDescription vmstate_piix4 = {
97 .name = "PIIX4",
98 .version_id = 2,
99 .minimum_version_id = 2,
100 .fields = (VMStateField[]) {
101 VMSTATE_PCI_DEVICE(dev, PIIX4State),
102 VMSTATE_END_OF_LIST()
103 }
104 };
105
106 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
107 {
108 PIIX4State *s = opaque;
109 qemu_set_irq(s->cpu_intr, level);
110 }
111
112 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
113 {
114 PIIX4State *s = opaque;
115 qemu_set_irq(s->isa[irq], level);
116 }
117
118 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
119 unsigned int len)
120 {
121 PIIX4State *s = opaque;
122
123 if (val & 4) {
124 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
125 return;
126 }
127
128 s->rcr = val & 2; /* keep System Reset type only */
129 }
130
131 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
132 {
133 PIIX4State *s = opaque;
134
135 return s->rcr;
136 }
137
138 static const MemoryRegionOps piix4_rcr_ops = {
139 .read = piix4_rcr_read,
140 .write = piix4_rcr_write,
141 .endianness = DEVICE_LITTLE_ENDIAN,
142 .impl = {
143 .min_access_size = 1,
144 .max_access_size = 1,
145 },
146 };
147
148 static void piix4_realize(PCIDevice *dev, Error **errp)
149 {
150 PIIX4State *s = PIIX4_PCI_DEVICE(dev);
151 ISABus *isa_bus;
152 qemu_irq *i8259_out_irq;
153
154 isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
155 pci_address_space_io(dev), errp);
156 if (!isa_bus) {
157 return;
158 }
159
160 qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
161 "isa", ISA_NUM_IRQS);
162 qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
163 "intr", 1);
164
165 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
166 "reset-control", 1);
167 memory_region_add_subregion_overlap(pci_address_space_io(dev),
168 PIIX_RCR_IOPORT, &s->rcr_mem, 1);
169
170 /* initialize i8259 pic */
171 i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
172 s->isa = i8259_init(isa_bus, *i8259_out_irq);
173
174 /* initialize ISA irqs */
175 isa_bus_irqs(isa_bus, s->isa);
176
177 /* initialize pit */
178 i8254_pit_init(isa_bus, 0x40, 0, NULL);
179
180 /* DMA */
181 i8257_dma_init(isa_bus, 0);
182
183 /* RTC */
184 qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
185 if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
186 return;
187 }
188 isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
189
190 piix4_dev = dev;
191 }
192
193 static void piix4_init(Object *obj)
194 {
195 PIIX4State *s = PIIX4_PCI_DEVICE(obj);
196
197 object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
198 }
199
200 static void piix4_class_init(ObjectClass *klass, void *data)
201 {
202 DeviceClass *dc = DEVICE_CLASS(klass);
203 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
204
205 k->realize = piix4_realize;
206 k->vendor_id = PCI_VENDOR_ID_INTEL;
207 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
208 k->class_id = PCI_CLASS_BRIDGE_ISA;
209 dc->reset = piix4_isa_reset;
210 dc->desc = "ISA bridge";
211 dc->vmsd = &vmstate_piix4;
212 /*
213 * Reason: part of PIIX4 southbridge, needs to be wired up,
214 * e.g. by mips_malta_init()
215 */
216 dc->user_creatable = false;
217 dc->hotpluggable = false;
218 }
219
220 static const TypeInfo piix4_info = {
221 .name = TYPE_PIIX4_PCI_DEVICE,
222 .parent = TYPE_PCI_DEVICE,
223 .instance_size = sizeof(PIIX4State),
224 .instance_init = piix4_init,
225 .class_init = piix4_class_init,
226 .interfaces = (InterfaceInfo[]) {
227 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
228 { },
229 },
230 };
231
232 static void piix4_register_types(void)
233 {
234 type_register_static(&piix4_info);
235 }
236
237 type_init(piix4_register_types)
238
239 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
240 {
241 PCIDevice *pci;
242 DeviceState *dev;
243 int devfn = PCI_DEVFN(10, 0);
244
245 pci = pci_create_simple_multifunction(pci_bus, devfn, true,
246 TYPE_PIIX4_PCI_DEVICE);
247 dev = DEVICE(pci);
248 if (isa_bus) {
249 *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
250 }
251
252 pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
253 pci_ide_create_devs(pci);
254
255 pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
256 if (smbus) {
257 *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
258 isa_get_irq(NULL, 9), NULL, 0, NULL);
259 }
260
261 return dev;
262 }