sm501: Add missing arbitration control register
[qemu.git] / hw / isa / vt82c686.c
1 /*
2 * VT82C686B south bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "qemu/osdep.h"
14 #include "hw/hw.h"
15 #include "hw/i386/pc.h"
16 #include "hw/isa/vt82c686.h"
17 #include "hw/i2c/i2c.h"
18 #include "hw/i2c/smbus.h"
19 #include "hw/pci/pci.h"
20 #include "hw/isa/isa.h"
21 #include "hw/sysbus.h"
22 #include "hw/mips/mips.h"
23 #include "hw/isa/apm.h"
24 #include "hw/acpi/acpi.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/timer.h"
28 #include "exec/address-spaces.h"
29
30 //#define DEBUG_VT82C686B
31
32 #ifdef DEBUG_VT82C686B
33 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
34 #else
35 #define DPRINTF(fmt, ...)
36 #endif
37
38 typedef struct SuperIOConfig
39 {
40 uint8_t config[0x100];
41 uint8_t index;
42 uint8_t data;
43 } SuperIOConfig;
44
45 typedef struct VT82C686BState {
46 PCIDevice dev;
47 MemoryRegion superio;
48 SuperIOConfig superio_conf;
49 } VT82C686BState;
50
51 #define TYPE_VT82C686B_DEVICE "VT82C686B"
52 #define VT82C686B_DEVICE(obj) \
53 OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE)
54
55 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
56 unsigned size)
57 {
58 SuperIOConfig *superio_conf = opaque;
59
60 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
61 if (addr == 0x3f0) {
62 superio_conf->index = data & 0xff;
63 } else {
64 bool can_write = true;
65 /* 0x3f1 */
66 switch (superio_conf->index) {
67 case 0x00 ... 0xdf:
68 case 0xe4:
69 case 0xe5:
70 case 0xe9 ... 0xed:
71 case 0xf3:
72 case 0xf5:
73 case 0xf7:
74 case 0xf9 ... 0xfb:
75 case 0xfd ... 0xff:
76 can_write = false;
77 break;
78 case 0xe7:
79 if ((data & 0xff) != 0xfe) {
80 DPRINTF("change uart 1 base. unsupported yet\n");
81 can_write = false;
82 }
83 break;
84 case 0xe8:
85 if ((data & 0xff) != 0xbe) {
86 DPRINTF("change uart 2 base. unsupported yet\n");
87 can_write = false;
88 }
89 break;
90 default:
91 break;
92
93 }
94 if (can_write) {
95 superio_conf->config[superio_conf->index] = data & 0xff;
96 }
97 }
98 }
99
100 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
101 {
102 SuperIOConfig *superio_conf = opaque;
103
104 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
105 return (superio_conf->config[superio_conf->index]);
106 }
107
108 static const MemoryRegionOps superio_ops = {
109 .read = superio_ioport_readb,
110 .write = superio_ioport_writeb,
111 .endianness = DEVICE_NATIVE_ENDIAN,
112 .impl = {
113 .min_access_size = 1,
114 .max_access_size = 1,
115 },
116 };
117
118 static void vt82c686b_reset(void * opaque)
119 {
120 PCIDevice *d = opaque;
121 uint8_t *pci_conf = d->config;
122 VT82C686BState *vt82c = VT82C686B_DEVICE(d);
123
124 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
125 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
126 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
127 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
128
129 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
130 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
131 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
132 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
133 pci_conf[0x59] = 0x04;
134 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
135 pci_conf[0x5f] = 0x04;
136 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
137
138 vt82c->superio_conf.config[0xe0] = 0x3c;
139 vt82c->superio_conf.config[0xe2] = 0x03;
140 vt82c->superio_conf.config[0xe3] = 0xfc;
141 vt82c->superio_conf.config[0xe6] = 0xde;
142 vt82c->superio_conf.config[0xe7] = 0xfe;
143 vt82c->superio_conf.config[0xe8] = 0xbe;
144 }
145
146 /* write config pci function0 registers. PCI-ISA bridge */
147 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
148 uint32_t val, int len)
149 {
150 VT82C686BState *vt686 = VT82C686B_DEVICE(d);
151
152 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
153 address, val, len);
154
155 pci_default_write_config(d, address, val, len);
156 if (address == 0x85) { /* enable or disable super IO configure */
157 memory_region_set_enabled(&vt686->superio, val & 0x2);
158 }
159 }
160
161 #define ACPI_DBG_IO_ADDR 0xb044
162
163 typedef struct VT686PMState {
164 PCIDevice dev;
165 MemoryRegion io;
166 ACPIREGS ar;
167 APMState apm;
168 PMSMBus smb;
169 uint32_t smb_io_base;
170 } VT686PMState;
171
172 typedef struct VT686AC97State {
173 PCIDevice dev;
174 } VT686AC97State;
175
176 typedef struct VT686MC97State {
177 PCIDevice dev;
178 } VT686MC97State;
179
180 #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM"
181 #define VT82C686B_PM_DEVICE(obj) \
182 OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE)
183
184 #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97"
185 #define VT82C686B_MC97_DEVICE(obj) \
186 OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE)
187
188 #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97"
189 #define VT82C686B_AC97_DEVICE(obj) \
190 OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE)
191
192 static void pm_update_sci(VT686PMState *s)
193 {
194 int sci_level, pmsts;
195
196 pmsts = acpi_pm1_evt_get_sts(&s->ar);
197 sci_level = (((pmsts & s->ar.pm1.evt.en) &
198 (ACPI_BITMASK_RT_CLOCK_ENABLE |
199 ACPI_BITMASK_POWER_BUTTON_ENABLE |
200 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
201 ACPI_BITMASK_TIMER_ENABLE)) != 0);
202 pci_set_irq(&s->dev, sci_level);
203 /* schedule a timer interruption if needed */
204 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
205 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
206 }
207
208 static void pm_tmr_timer(ACPIREGS *ar)
209 {
210 VT686PMState *s = container_of(ar, VT686PMState, ar);
211 pm_update_sci(s);
212 }
213
214 static void pm_io_space_update(VT686PMState *s)
215 {
216 uint32_t pm_io_base;
217
218 pm_io_base = pci_get_long(s->dev.config + 0x40);
219 pm_io_base &= 0xffc0;
220
221 memory_region_transaction_begin();
222 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
223 memory_region_set_address(&s->io, pm_io_base);
224 memory_region_transaction_commit();
225 }
226
227 static void pm_write_config(PCIDevice *d,
228 uint32_t address, uint32_t val, int len)
229 {
230 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
231 address, val, len);
232 pci_default_write_config(d, address, val, len);
233 }
234
235 static int vmstate_acpi_post_load(void *opaque, int version_id)
236 {
237 VT686PMState *s = opaque;
238
239 pm_io_space_update(s);
240 return 0;
241 }
242
243 static const VMStateDescription vmstate_acpi = {
244 .name = "vt82c686b_pm",
245 .version_id = 1,
246 .minimum_version_id = 1,
247 .post_load = vmstate_acpi_post_load,
248 .fields = (VMStateField[]) {
249 VMSTATE_PCI_DEVICE(dev, VT686PMState),
250 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
251 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
252 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
253 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
254 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
255 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
256 VMSTATE_END_OF_LIST()
257 }
258 };
259
260 /*
261 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
262 * just register a PCI device now, functionalities will be implemented later.
263 */
264
265 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
266 {
267 VT686AC97State *s = VT82C686B_AC97_DEVICE(dev);
268 uint8_t *pci_conf = s->dev.config;
269
270 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
271 PCI_COMMAND_PARITY);
272 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
273 PCI_STATUS_DEVSEL_MEDIUM);
274 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
275 }
276
277 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
278 {
279 PCIDevice *dev;
280
281 dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE);
282 qdev_init_nofail(&dev->qdev);
283 }
284
285 static void via_ac97_class_init(ObjectClass *klass, void *data)
286 {
287 DeviceClass *dc = DEVICE_CLASS(klass);
288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
289
290 k->realize = vt82c686b_ac97_realize;
291 k->vendor_id = PCI_VENDOR_ID_VIA;
292 k->device_id = PCI_DEVICE_ID_VIA_AC97;
293 k->revision = 0x50;
294 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
295 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
296 dc->desc = "AC97";
297 }
298
299 static const TypeInfo via_ac97_info = {
300 .name = TYPE_VT82C686B_AC97_DEVICE,
301 .parent = TYPE_PCI_DEVICE,
302 .instance_size = sizeof(VT686AC97State),
303 .class_init = via_ac97_class_init,
304 };
305
306 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
307 {
308 VT686MC97State *s = VT82C686B_MC97_DEVICE(dev);
309 uint8_t *pci_conf = s->dev.config;
310
311 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
312 PCI_COMMAND_VGA_PALETTE);
313 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
314 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
315 }
316
317 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
318 {
319 PCIDevice *dev;
320
321 dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE);
322 qdev_init_nofail(&dev->qdev);
323 }
324
325 static void via_mc97_class_init(ObjectClass *klass, void *data)
326 {
327 DeviceClass *dc = DEVICE_CLASS(klass);
328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
329
330 k->realize = vt82c686b_mc97_realize;
331 k->vendor_id = PCI_VENDOR_ID_VIA;
332 k->device_id = PCI_DEVICE_ID_VIA_MC97;
333 k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
334 k->revision = 0x30;
335 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
336 dc->desc = "MC97";
337 }
338
339 static const TypeInfo via_mc97_info = {
340 .name = TYPE_VT82C686B_MC97_DEVICE,
341 .parent = TYPE_PCI_DEVICE,
342 .instance_size = sizeof(VT686MC97State),
343 .class_init = via_mc97_class_init,
344 };
345
346 /* vt82c686 pm init */
347 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
348 {
349 VT686PMState *s = VT82C686B_PM_DEVICE(dev);
350 uint8_t *pci_conf;
351
352 pci_conf = s->dev.config;
353 pci_set_word(pci_conf + PCI_COMMAND, 0);
354 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
355 PCI_STATUS_DEVSEL_MEDIUM);
356
357 /* 0x48-0x4B is Power Management I/O Base */
358 pci_set_long(pci_conf + 0x48, 0x00000001);
359
360 /* SMB ports:0xeee0~0xeeef */
361 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
362 pci_conf[0x90] = s->smb_io_base | 1;
363 pci_conf[0x91] = s->smb_io_base >> 8;
364 pci_conf[0xd2] = 0x90;
365 pm_smbus_init(&s->dev.qdev, &s->smb);
366 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
367
368 apm_init(dev, &s->apm, NULL, s);
369
370 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
371 memory_region_set_enabled(&s->io, false);
372 memory_region_add_subregion(get_system_io(), 0, &s->io);
373
374 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
375 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
376 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
377 }
378
379 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
380 qemu_irq sci_irq)
381 {
382 PCIDevice *dev;
383 VT686PMState *s;
384
385 dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE);
386 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
387
388 s = VT82C686B_PM_DEVICE(dev);
389
390 qdev_init_nofail(&dev->qdev);
391
392 return s->smb.smbus;
393 }
394
395 static Property via_pm_properties[] = {
396 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
397 DEFINE_PROP_END_OF_LIST(),
398 };
399
400 static void via_pm_class_init(ObjectClass *klass, void *data)
401 {
402 DeviceClass *dc = DEVICE_CLASS(klass);
403 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
404
405 k->realize = vt82c686b_pm_realize;
406 k->config_write = pm_write_config;
407 k->vendor_id = PCI_VENDOR_ID_VIA;
408 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
409 k->class_id = PCI_CLASS_BRIDGE_OTHER;
410 k->revision = 0x40;
411 dc->desc = "PM";
412 dc->vmsd = &vmstate_acpi;
413 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
414 dc->props = via_pm_properties;
415 }
416
417 static const TypeInfo via_pm_info = {
418 .name = TYPE_VT82C686B_PM_DEVICE,
419 .parent = TYPE_PCI_DEVICE,
420 .instance_size = sizeof(VT686PMState),
421 .class_init = via_pm_class_init,
422 };
423
424 static const VMStateDescription vmstate_via = {
425 .name = "vt82c686b",
426 .version_id = 1,
427 .minimum_version_id = 1,
428 .fields = (VMStateField[]) {
429 VMSTATE_PCI_DEVICE(dev, VT82C686BState),
430 VMSTATE_END_OF_LIST()
431 }
432 };
433
434 /* init the PCI-to-ISA bridge */
435 static void vt82c686b_realize(PCIDevice *d, Error **errp)
436 {
437 VT82C686BState *vt82c = VT82C686B_DEVICE(d);
438 uint8_t *pci_conf;
439 ISABus *isa_bus;
440 uint8_t *wmask;
441 int i;
442
443 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
444 pci_address_space_io(d), errp);
445 if (!isa_bus) {
446 return;
447 }
448
449 pci_conf = d->config;
450 pci_config_set_prog_interface(pci_conf, 0x0);
451
452 wmask = d->wmask;
453 for (i = 0x00; i < 0xff; i++) {
454 if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
455 wmask[i] = 0x00;
456 }
457 }
458
459 memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
460 &vt82c->superio_conf, "superio", 2);
461 memory_region_set_enabled(&vt82c->superio, false);
462 /* The floppy also uses 0x3f0 and 0x3f1.
463 * But we do not emulate a floppy, so just set it here. */
464 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
465 &vt82c->superio);
466
467 qemu_register_reset(vt82c686b_reset, d);
468 }
469
470 ISABus *vt82c686b_init(PCIBus *bus, int devfn)
471 {
472 PCIDevice *d;
473
474 d = pci_create_simple_multifunction(bus, devfn, true,
475 TYPE_VT82C686B_DEVICE);
476
477 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
478 }
479
480 static void via_class_init(ObjectClass *klass, void *data)
481 {
482 DeviceClass *dc = DEVICE_CLASS(klass);
483 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
484
485 k->realize = vt82c686b_realize;
486 k->config_write = vt82c686b_write_config;
487 k->vendor_id = PCI_VENDOR_ID_VIA;
488 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
489 k->class_id = PCI_CLASS_BRIDGE_ISA;
490 k->revision = 0x40;
491 dc->desc = "ISA bridge";
492 dc->vmsd = &vmstate_via;
493 /*
494 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
495 * e.g. by mips_fulong2e_init()
496 */
497 dc->cannot_instantiate_with_device_add_yet = true;
498 }
499
500 static const TypeInfo via_info = {
501 .name = TYPE_VT82C686B_DEVICE,
502 .parent = TYPE_PCI_DEVICE,
503 .instance_size = sizeof(VT82C686BState),
504 .class_init = via_class_init,
505 };
506
507 static void vt82c686b_register_types(void)
508 {
509 type_register_static(&via_ac97_info);
510 type_register_static(&via_mc97_info);
511 type_register_static(&via_pm_info);
512 type_register_static(&via_info);
513 }
514
515 type_init(vt82c686b_register_types)