hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / isa / vt82c686.c
1 /*
2 * VT82C686B south bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "qemu/osdep.h"
14 #include "hw/isa/vt82c686.h"
15 #include "hw/i2c/i2c.h"
16 #include "hw/pci/pci.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/isa/isa.h"
19 #include "hw/isa/superio.h"
20 #include "hw/sysbus.h"
21 #include "migration/vmstate.h"
22 #include "hw/mips/mips.h"
23 #include "hw/isa/apm.h"
24 #include "hw/acpi/acpi.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include "exec/address-spaces.h"
30 #include "qom/object.h"
31
32 /* #define DEBUG_VT82C686B */
33
34 #ifdef DEBUG_VT82C686B
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
36 #else
37 #define DPRINTF(fmt, ...)
38 #endif
39
40 typedef struct SuperIOConfig {
41 uint8_t config[0x100];
42 uint8_t index;
43 uint8_t data;
44 } SuperIOConfig;
45
46 struct VT82C686BState {
47 PCIDevice dev;
48 MemoryRegion superio;
49 SuperIOConfig superio_conf;
50 };
51
52 #define TYPE_VT82C686B_DEVICE "VT82C686B"
53 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BState, VT82C686B_DEVICE)
54
55 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
56 unsigned size)
57 {
58 SuperIOConfig *superio_conf = opaque;
59
60 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
61 if (addr == 0x3f0) {
62 superio_conf->index = data & 0xff;
63 } else {
64 bool can_write = true;
65 /* 0x3f1 */
66 switch (superio_conf->index) {
67 case 0x00 ... 0xdf:
68 case 0xe4:
69 case 0xe5:
70 case 0xe9 ... 0xed:
71 case 0xf3:
72 case 0xf5:
73 case 0xf7:
74 case 0xf9 ... 0xfb:
75 case 0xfd ... 0xff:
76 can_write = false;
77 break;
78 case 0xe7:
79 if ((data & 0xff) != 0xfe) {
80 DPRINTF("change uart 1 base. unsupported yet\n");
81 can_write = false;
82 }
83 break;
84 case 0xe8:
85 if ((data & 0xff) != 0xbe) {
86 DPRINTF("change uart 2 base. unsupported yet\n");
87 can_write = false;
88 }
89 break;
90 default:
91 break;
92
93 }
94 if (can_write) {
95 superio_conf->config[superio_conf->index] = data & 0xff;
96 }
97 }
98 }
99
100 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
101 {
102 SuperIOConfig *superio_conf = opaque;
103
104 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
105 return superio_conf->config[superio_conf->index];
106 }
107
108 static const MemoryRegionOps superio_ops = {
109 .read = superio_ioport_readb,
110 .write = superio_ioport_writeb,
111 .endianness = DEVICE_NATIVE_ENDIAN,
112 .impl = {
113 .min_access_size = 1,
114 .max_access_size = 1,
115 },
116 };
117
118 static void vt82c686b_isa_reset(DeviceState *dev)
119 {
120 VT82C686BState *vt82c = VT82C686B_DEVICE(dev);
121 uint8_t *pci_conf = vt82c->dev.config;
122
123 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
124 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
125 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
126 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
127
128 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
129 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
130 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
131 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
132 pci_conf[0x59] = 0x04;
133 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
134 pci_conf[0x5f] = 0x04;
135 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
136
137 vt82c->superio_conf.config[0xe0] = 0x3c;
138 vt82c->superio_conf.config[0xe2] = 0x03;
139 vt82c->superio_conf.config[0xe3] = 0xfc;
140 vt82c->superio_conf.config[0xe6] = 0xde;
141 vt82c->superio_conf.config[0xe7] = 0xfe;
142 vt82c->superio_conf.config[0xe8] = 0xbe;
143 }
144
145 /* write config pci function0 registers. PCI-ISA bridge */
146 static void vt82c686b_write_config(PCIDevice *d, uint32_t address,
147 uint32_t val, int len)
148 {
149 VT82C686BState *vt686 = VT82C686B_DEVICE(d);
150
151 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
152 address, val, len);
153
154 pci_default_write_config(d, address, val, len);
155 if (address == 0x85) { /* enable or disable super IO configure */
156 memory_region_set_enabled(&vt686->superio, val & 0x2);
157 }
158 }
159
160 #define ACPI_DBG_IO_ADDR 0xb044
161
162 struct VT686PMState {
163 PCIDevice dev;
164 MemoryRegion io;
165 ACPIREGS ar;
166 APMState apm;
167 PMSMBus smb;
168 uint32_t smb_io_base;
169 };
170
171 struct VT686AC97State {
172 PCIDevice dev;
173 };
174
175 struct VT686MC97State {
176 PCIDevice dev;
177 };
178
179 #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM"
180 OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM_DEVICE)
181
182 #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97"
183 OBJECT_DECLARE_SIMPLE_TYPE(VT686MC97State, VT82C686B_MC97_DEVICE)
184
185 #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97"
186 OBJECT_DECLARE_SIMPLE_TYPE(VT686AC97State, VT82C686B_AC97_DEVICE)
187
188 static void pm_update_sci(VT686PMState *s)
189 {
190 int sci_level, pmsts;
191
192 pmsts = acpi_pm1_evt_get_sts(&s->ar);
193 sci_level = (((pmsts & s->ar.pm1.evt.en) &
194 (ACPI_BITMASK_RT_CLOCK_ENABLE |
195 ACPI_BITMASK_POWER_BUTTON_ENABLE |
196 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
197 ACPI_BITMASK_TIMER_ENABLE)) != 0);
198 pci_set_irq(&s->dev, sci_level);
199 /* schedule a timer interruption if needed */
200 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
201 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
202 }
203
204 static void pm_tmr_timer(ACPIREGS *ar)
205 {
206 VT686PMState *s = container_of(ar, VT686PMState, ar);
207 pm_update_sci(s);
208 }
209
210 static void pm_io_space_update(VT686PMState *s)
211 {
212 uint32_t pm_io_base;
213
214 pm_io_base = pci_get_long(s->dev.config + 0x40);
215 pm_io_base &= 0xffc0;
216
217 memory_region_transaction_begin();
218 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
219 memory_region_set_address(&s->io, pm_io_base);
220 memory_region_transaction_commit();
221 }
222
223 static void pm_write_config(PCIDevice *d,
224 uint32_t address, uint32_t val, int len)
225 {
226 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
227 address, val, len);
228 pci_default_write_config(d, address, val, len);
229 }
230
231 static int vmstate_acpi_post_load(void *opaque, int version_id)
232 {
233 VT686PMState *s = opaque;
234
235 pm_io_space_update(s);
236 return 0;
237 }
238
239 static const VMStateDescription vmstate_acpi = {
240 .name = "vt82c686b_pm",
241 .version_id = 1,
242 .minimum_version_id = 1,
243 .post_load = vmstate_acpi_post_load,
244 .fields = (VMStateField[]) {
245 VMSTATE_PCI_DEVICE(dev, VT686PMState),
246 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
247 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
248 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
249 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
250 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
251 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
252 VMSTATE_END_OF_LIST()
253 }
254 };
255
256 /*
257 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
258 * just register a PCI device now, functionalities will be implemented later.
259 */
260
261 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
262 {
263 VT686AC97State *s = VT82C686B_AC97_DEVICE(dev);
264 uint8_t *pci_conf = s->dev.config;
265
266 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
267 PCI_COMMAND_PARITY);
268 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
269 PCI_STATUS_DEVSEL_MEDIUM);
270 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
271 }
272
273 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
274 {
275 PCIDevice *dev;
276
277 dev = pci_new(devfn, TYPE_VT82C686B_AC97_DEVICE);
278 pci_realize_and_unref(dev, bus, &error_fatal);
279 }
280
281 static void via_ac97_class_init(ObjectClass *klass, void *data)
282 {
283 DeviceClass *dc = DEVICE_CLASS(klass);
284 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
285
286 k->realize = vt82c686b_ac97_realize;
287 k->vendor_id = PCI_VENDOR_ID_VIA;
288 k->device_id = PCI_DEVICE_ID_VIA_AC97;
289 k->revision = 0x50;
290 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
291 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
292 dc->desc = "AC97";
293 }
294
295 static const TypeInfo via_ac97_info = {
296 .name = TYPE_VT82C686B_AC97_DEVICE,
297 .parent = TYPE_PCI_DEVICE,
298 .instance_size = sizeof(VT686AC97State),
299 .class_init = via_ac97_class_init,
300 .interfaces = (InterfaceInfo[]) {
301 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
302 { },
303 },
304 };
305
306 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
307 {
308 VT686MC97State *s = VT82C686B_MC97_DEVICE(dev);
309 uint8_t *pci_conf = s->dev.config;
310
311 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
312 PCI_COMMAND_VGA_PALETTE);
313 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
314 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
315 }
316
317 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
318 {
319 PCIDevice *dev;
320
321 dev = pci_new(devfn, TYPE_VT82C686B_MC97_DEVICE);
322 pci_realize_and_unref(dev, bus, &error_fatal);
323 }
324
325 static void via_mc97_class_init(ObjectClass *klass, void *data)
326 {
327 DeviceClass *dc = DEVICE_CLASS(klass);
328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
329
330 k->realize = vt82c686b_mc97_realize;
331 k->vendor_id = PCI_VENDOR_ID_VIA;
332 k->device_id = PCI_DEVICE_ID_VIA_MC97;
333 k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
334 k->revision = 0x30;
335 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
336 dc->desc = "MC97";
337 }
338
339 static const TypeInfo via_mc97_info = {
340 .name = TYPE_VT82C686B_MC97_DEVICE,
341 .parent = TYPE_PCI_DEVICE,
342 .instance_size = sizeof(VT686MC97State),
343 .class_init = via_mc97_class_init,
344 .interfaces = (InterfaceInfo[]) {
345 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
346 { },
347 },
348 };
349
350 /* vt82c686 pm init */
351 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
352 {
353 VT686PMState *s = VT82C686B_PM_DEVICE(dev);
354 uint8_t *pci_conf;
355
356 pci_conf = s->dev.config;
357 pci_set_word(pci_conf + PCI_COMMAND, 0);
358 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
359 PCI_STATUS_DEVSEL_MEDIUM);
360
361 /* 0x48-0x4B is Power Management I/O Base */
362 pci_set_long(pci_conf + 0x48, 0x00000001);
363
364 /* SMB ports:0xeee0~0xeeef */
365 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
366 pci_conf[0x90] = s->smb_io_base | 1;
367 pci_conf[0x91] = s->smb_io_base >> 8;
368 pci_conf[0xd2] = 0x90;
369 pm_smbus_init(DEVICE(s), &s->smb, false);
370 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
371
372 apm_init(dev, &s->apm, NULL, s);
373
374 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
375 memory_region_set_enabled(&s->io, false);
376 memory_region_add_subregion(get_system_io(), 0, &s->io);
377
378 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
379 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
380 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
381 }
382
383 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
384 qemu_irq sci_irq)
385 {
386 PCIDevice *dev;
387 VT686PMState *s;
388
389 dev = pci_new(devfn, TYPE_VT82C686B_PM_DEVICE);
390 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
391
392 s = VT82C686B_PM_DEVICE(dev);
393
394 pci_realize_and_unref(dev, bus, &error_fatal);
395
396 return s->smb.smbus;
397 }
398
399 static Property via_pm_properties[] = {
400 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
401 DEFINE_PROP_END_OF_LIST(),
402 };
403
404 static void via_pm_class_init(ObjectClass *klass, void *data)
405 {
406 DeviceClass *dc = DEVICE_CLASS(klass);
407 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
408
409 k->realize = vt82c686b_pm_realize;
410 k->config_write = pm_write_config;
411 k->vendor_id = PCI_VENDOR_ID_VIA;
412 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
413 k->class_id = PCI_CLASS_BRIDGE_OTHER;
414 k->revision = 0x40;
415 dc->desc = "PM";
416 dc->vmsd = &vmstate_acpi;
417 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
418 device_class_set_props(dc, via_pm_properties);
419 }
420
421 static const TypeInfo via_pm_info = {
422 .name = TYPE_VT82C686B_PM_DEVICE,
423 .parent = TYPE_PCI_DEVICE,
424 .instance_size = sizeof(VT686PMState),
425 .class_init = via_pm_class_init,
426 .interfaces = (InterfaceInfo[]) {
427 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
428 { },
429 },
430 };
431
432 static const VMStateDescription vmstate_via = {
433 .name = "vt82c686b",
434 .version_id = 1,
435 .minimum_version_id = 1,
436 .fields = (VMStateField[]) {
437 VMSTATE_PCI_DEVICE(dev, VT82C686BState),
438 VMSTATE_END_OF_LIST()
439 }
440 };
441
442 /* init the PCI-to-ISA bridge */
443 static void vt82c686b_realize(PCIDevice *d, Error **errp)
444 {
445 VT82C686BState *vt82c = VT82C686B_DEVICE(d);
446 uint8_t *pci_conf;
447 ISABus *isa_bus;
448 uint8_t *wmask;
449 int i;
450
451 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
452 pci_address_space_io(d), errp);
453 if (!isa_bus) {
454 return;
455 }
456
457 pci_conf = d->config;
458 pci_config_set_prog_interface(pci_conf, 0x0);
459
460 wmask = d->wmask;
461 for (i = 0x00; i < 0xff; i++) {
462 if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
463 wmask[i] = 0x00;
464 }
465 }
466
467 memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
468 &vt82c->superio_conf, "superio", 2);
469 memory_region_set_enabled(&vt82c->superio, false);
470 /*
471 * The floppy also uses 0x3f0 and 0x3f1.
472 * But we do not emulate a floppy, so just set it here.
473 */
474 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
475 &vt82c->superio);
476 }
477
478 ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn)
479 {
480 PCIDevice *d;
481
482 d = pci_create_simple_multifunction(bus, devfn, true,
483 TYPE_VT82C686B_DEVICE);
484
485 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
486 }
487
488 static void via_class_init(ObjectClass *klass, void *data)
489 {
490 DeviceClass *dc = DEVICE_CLASS(klass);
491 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
492
493 k->realize = vt82c686b_realize;
494 k->config_write = vt82c686b_write_config;
495 k->vendor_id = PCI_VENDOR_ID_VIA;
496 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
497 k->class_id = PCI_CLASS_BRIDGE_ISA;
498 k->revision = 0x40;
499 dc->reset = vt82c686b_isa_reset;
500 dc->desc = "ISA bridge";
501 dc->vmsd = &vmstate_via;
502 /*
503 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
504 * e.g. by mips_fuloong2e_init()
505 */
506 dc->user_creatable = false;
507 }
508
509 static const TypeInfo via_info = {
510 .name = TYPE_VT82C686B_DEVICE,
511 .parent = TYPE_PCI_DEVICE,
512 .instance_size = sizeof(VT82C686BState),
513 .class_init = via_class_init,
514 .interfaces = (InterfaceInfo[]) {
515 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
516 { },
517 },
518 };
519
520 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
521 {
522 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
523
524 sc->serial.count = 2;
525 sc->parallel.count = 1;
526 sc->ide.count = 0;
527 sc->floppy.count = 1;
528 }
529
530 static const TypeInfo via_superio_info = {
531 .name = TYPE_VT82C686B_SUPERIO,
532 .parent = TYPE_ISA_SUPERIO,
533 .instance_size = sizeof(ISASuperIODevice),
534 .class_size = sizeof(ISASuperIOClass),
535 .class_init = vt82c686b_superio_class_init,
536 };
537
538 static void vt82c686b_register_types(void)
539 {
540 type_register_static(&via_ac97_info);
541 type_register_static(&via_mc97_info);
542 type_register_static(&via_pm_info);
543 type_register_static(&via_superio_info);
544 type_register_static(&via_info);
545 }
546
547 type_init(vt82c686b_register_types)