PPC: e500mc: add missing IVORs to bitmap
[qemu.git] / hw / lan9118.c
1 /*
2 * SMSC LAN9118 Ethernet interface emulation
3 *
4 * Copyright (c) 2009 CodeSourcery, LLC.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GNU GPL v2
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "sysbus.h"
14 #include "net.h"
15 #include "devices.h"
16 #include "sysemu.h"
17 #include "ptimer.h"
18 /* For crc32 */
19 #include <zlib.h>
20
21 //#define DEBUG_LAN9118
22
23 #ifdef DEBUG_LAN9118
24 #define DPRINTF(fmt, ...) \
25 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
26 #define BADF(fmt, ...) \
27 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
28 #else
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #define BADF(fmt, ...) \
31 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
32 #endif
33
34 #define CSR_ID_REV 0x50
35 #define CSR_IRQ_CFG 0x54
36 #define CSR_INT_STS 0x58
37 #define CSR_INT_EN 0x5c
38 #define CSR_BYTE_TEST 0x64
39 #define CSR_FIFO_INT 0x68
40 #define CSR_RX_CFG 0x6c
41 #define CSR_TX_CFG 0x70
42 #define CSR_HW_CFG 0x74
43 #define CSR_RX_DP_CTRL 0x78
44 #define CSR_RX_FIFO_INF 0x7c
45 #define CSR_TX_FIFO_INF 0x80
46 #define CSR_PMT_CTRL 0x84
47 #define CSR_GPIO_CFG 0x88
48 #define CSR_GPT_CFG 0x8c
49 #define CSR_GPT_CNT 0x90
50 #define CSR_WORD_SWAP 0x98
51 #define CSR_FREE_RUN 0x9c
52 #define CSR_RX_DROP 0xa0
53 #define CSR_MAC_CSR_CMD 0xa4
54 #define CSR_MAC_CSR_DATA 0xa8
55 #define CSR_AFC_CFG 0xac
56 #define CSR_E2P_CMD 0xb0
57 #define CSR_E2P_DATA 0xb4
58
59 /* IRQ_CFG */
60 #define IRQ_INT 0x00001000
61 #define IRQ_EN 0x00000100
62 #define IRQ_POL 0x00000010
63 #define IRQ_TYPE 0x00000001
64
65 /* INT_STS/INT_EN */
66 #define SW_INT 0x80000000
67 #define TXSTOP_INT 0x02000000
68 #define RXSTOP_INT 0x01000000
69 #define RXDFH_INT 0x00800000
70 #define TX_IOC_INT 0x00200000
71 #define RXD_INT 0x00100000
72 #define GPT_INT 0x00080000
73 #define PHY_INT 0x00040000
74 #define PME_INT 0x00020000
75 #define TXSO_INT 0x00010000
76 #define RWT_INT 0x00008000
77 #define RXE_INT 0x00004000
78 #define TXE_INT 0x00002000
79 #define TDFU_INT 0x00000800
80 #define TDFO_INT 0x00000400
81 #define TDFA_INT 0x00000200
82 #define TSFF_INT 0x00000100
83 #define TSFL_INT 0x00000080
84 #define RXDF_INT 0x00000040
85 #define RDFL_INT 0x00000020
86 #define RSFF_INT 0x00000010
87 #define RSFL_INT 0x00000008
88 #define GPIO2_INT 0x00000004
89 #define GPIO1_INT 0x00000002
90 #define GPIO0_INT 0x00000001
91 #define RESERVED_INT 0x7c001000
92
93 #define MAC_CR 1
94 #define MAC_ADDRH 2
95 #define MAC_ADDRL 3
96 #define MAC_HASHH 4
97 #define MAC_HASHL 5
98 #define MAC_MII_ACC 6
99 #define MAC_MII_DATA 7
100 #define MAC_FLOW 8
101 #define MAC_VLAN1 9 /* TODO */
102 #define MAC_VLAN2 10 /* TODO */
103 #define MAC_WUFF 11 /* TODO */
104 #define MAC_WUCSR 12 /* TODO */
105
106 #define MAC_CR_RXALL 0x80000000
107 #define MAC_CR_RCVOWN 0x00800000
108 #define MAC_CR_LOOPBK 0x00200000
109 #define MAC_CR_FDPX 0x00100000
110 #define MAC_CR_MCPAS 0x00080000
111 #define MAC_CR_PRMS 0x00040000
112 #define MAC_CR_INVFILT 0x00020000
113 #define MAC_CR_PASSBAD 0x00010000
114 #define MAC_CR_HO 0x00008000
115 #define MAC_CR_HPFILT 0x00002000
116 #define MAC_CR_LCOLL 0x00001000
117 #define MAC_CR_BCAST 0x00000800
118 #define MAC_CR_DISRTY 0x00000400
119 #define MAC_CR_PADSTR 0x00000100
120 #define MAC_CR_BOLMT 0x000000c0
121 #define MAC_CR_DFCHK 0x00000020
122 #define MAC_CR_TXEN 0x00000008
123 #define MAC_CR_RXEN 0x00000004
124 #define MAC_CR_RESERVED 0x7f404213
125
126 #define PHY_INT_ENERGYON 0x80
127 #define PHY_INT_AUTONEG_COMPLETE 0x40
128 #define PHY_INT_FAULT 0x20
129 #define PHY_INT_DOWN 0x10
130 #define PHY_INT_AUTONEG_LP 0x08
131 #define PHY_INT_PARFAULT 0x04
132 #define PHY_INT_AUTONEG_PAGE 0x02
133
134 #define GPT_TIMER_EN 0x20000000
135
136 enum tx_state {
137 TX_IDLE,
138 TX_B,
139 TX_DATA
140 };
141
142 typedef struct {
143 /* state is a tx_state but we can't put enums in VMStateDescriptions. */
144 uint32_t state;
145 uint32_t cmd_a;
146 uint32_t cmd_b;
147 int32_t buffer_size;
148 int32_t offset;
149 int32_t pad;
150 int32_t fifo_used;
151 int32_t len;
152 uint8_t data[2048];
153 } LAN9118Packet;
154
155 static const VMStateDescription vmstate_lan9118_packet = {
156 .name = "lan9118_packet",
157 .version_id = 1,
158 .minimum_version_id = 1,
159 .fields = (VMStateField[]) {
160 VMSTATE_UINT32(state, LAN9118Packet),
161 VMSTATE_UINT32(cmd_a, LAN9118Packet),
162 VMSTATE_UINT32(cmd_b, LAN9118Packet),
163 VMSTATE_INT32(buffer_size, LAN9118Packet),
164 VMSTATE_INT32(offset, LAN9118Packet),
165 VMSTATE_INT32(pad, LAN9118Packet),
166 VMSTATE_INT32(fifo_used, LAN9118Packet),
167 VMSTATE_INT32(len, LAN9118Packet),
168 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
169 VMSTATE_END_OF_LIST()
170 }
171 };
172
173 typedef struct {
174 SysBusDevice busdev;
175 NICState *nic;
176 NICConf conf;
177 qemu_irq irq;
178 MemoryRegion mmio;
179 ptimer_state *timer;
180
181 uint32_t irq_cfg;
182 uint32_t int_sts;
183 uint32_t int_en;
184 uint32_t fifo_int;
185 uint32_t rx_cfg;
186 uint32_t tx_cfg;
187 uint32_t hw_cfg;
188 uint32_t pmt_ctrl;
189 uint32_t gpio_cfg;
190 uint32_t gpt_cfg;
191 uint32_t word_swap;
192 uint32_t free_timer_start;
193 uint32_t mac_cmd;
194 uint32_t mac_data;
195 uint32_t afc_cfg;
196 uint32_t e2p_cmd;
197 uint32_t e2p_data;
198
199 uint32_t mac_cr;
200 uint32_t mac_hashh;
201 uint32_t mac_hashl;
202 uint32_t mac_mii_acc;
203 uint32_t mac_mii_data;
204 uint32_t mac_flow;
205
206 uint32_t phy_status;
207 uint32_t phy_control;
208 uint32_t phy_advertise;
209 uint32_t phy_int;
210 uint32_t phy_int_mask;
211
212 int32_t eeprom_writable;
213 uint8_t eeprom[128];
214
215 int32_t tx_fifo_size;
216 LAN9118Packet *txp;
217 LAN9118Packet tx_packet;
218
219 int32_t tx_status_fifo_used;
220 int32_t tx_status_fifo_head;
221 uint32_t tx_status_fifo[512];
222
223 int32_t rx_status_fifo_size;
224 int32_t rx_status_fifo_used;
225 int32_t rx_status_fifo_head;
226 uint32_t rx_status_fifo[896];
227 int32_t rx_fifo_size;
228 int32_t rx_fifo_used;
229 int32_t rx_fifo_head;
230 uint32_t rx_fifo[3360];
231 int32_t rx_packet_size_head;
232 int32_t rx_packet_size_tail;
233 int32_t rx_packet_size[1024];
234
235 int32_t rxp_offset;
236 int32_t rxp_size;
237 int32_t rxp_pad;
238 } lan9118_state;
239
240 static const VMStateDescription vmstate_lan9118 = {
241 .name = "lan9118",
242 .version_id = 1,
243 .minimum_version_id = 1,
244 .fields = (VMStateField[]) {
245 VMSTATE_PTIMER(timer, lan9118_state),
246 VMSTATE_UINT32(irq_cfg, lan9118_state),
247 VMSTATE_UINT32(int_sts, lan9118_state),
248 VMSTATE_UINT32(int_en, lan9118_state),
249 VMSTATE_UINT32(fifo_int, lan9118_state),
250 VMSTATE_UINT32(rx_cfg, lan9118_state),
251 VMSTATE_UINT32(tx_cfg, lan9118_state),
252 VMSTATE_UINT32(hw_cfg, lan9118_state),
253 VMSTATE_UINT32(pmt_ctrl, lan9118_state),
254 VMSTATE_UINT32(gpio_cfg, lan9118_state),
255 VMSTATE_UINT32(gpt_cfg, lan9118_state),
256 VMSTATE_UINT32(word_swap, lan9118_state),
257 VMSTATE_UINT32(free_timer_start, lan9118_state),
258 VMSTATE_UINT32(mac_cmd, lan9118_state),
259 VMSTATE_UINT32(mac_data, lan9118_state),
260 VMSTATE_UINT32(afc_cfg, lan9118_state),
261 VMSTATE_UINT32(e2p_cmd, lan9118_state),
262 VMSTATE_UINT32(e2p_data, lan9118_state),
263 VMSTATE_UINT32(mac_cr, lan9118_state),
264 VMSTATE_UINT32(mac_hashh, lan9118_state),
265 VMSTATE_UINT32(mac_hashl, lan9118_state),
266 VMSTATE_UINT32(mac_mii_acc, lan9118_state),
267 VMSTATE_UINT32(mac_mii_data, lan9118_state),
268 VMSTATE_UINT32(mac_flow, lan9118_state),
269 VMSTATE_UINT32(phy_status, lan9118_state),
270 VMSTATE_UINT32(phy_control, lan9118_state),
271 VMSTATE_UINT32(phy_advertise, lan9118_state),
272 VMSTATE_UINT32(phy_int, lan9118_state),
273 VMSTATE_UINT32(phy_int_mask, lan9118_state),
274 VMSTATE_INT32(eeprom_writable, lan9118_state),
275 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
276 VMSTATE_INT32(tx_fifo_size, lan9118_state),
277 /* txp always points at tx_packet so need not be saved */
278 VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
279 vmstate_lan9118_packet, LAN9118Packet),
280 VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
281 VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
282 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
283 VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
284 VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
285 VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
286 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
287 VMSTATE_INT32(rx_fifo_size, lan9118_state),
288 VMSTATE_INT32(rx_fifo_used, lan9118_state),
289 VMSTATE_INT32(rx_fifo_head, lan9118_state),
290 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
291 VMSTATE_INT32(rx_packet_size_head, lan9118_state),
292 VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
293 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
294 VMSTATE_INT32(rxp_offset, lan9118_state),
295 VMSTATE_INT32(rxp_size, lan9118_state),
296 VMSTATE_INT32(rxp_pad, lan9118_state),
297 VMSTATE_END_OF_LIST()
298 }
299 };
300
301 static void lan9118_update(lan9118_state *s)
302 {
303 int level;
304
305 /* TODO: Implement FIFO level IRQs. */
306 level = (s->int_sts & s->int_en) != 0;
307 if (level) {
308 s->irq_cfg |= IRQ_INT;
309 } else {
310 s->irq_cfg &= ~IRQ_INT;
311 }
312 if ((s->irq_cfg & IRQ_EN) == 0) {
313 level = 0;
314 }
315 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
316 /* Interrupt is active low unless we're configured as
317 * active-high polarity, push-pull type.
318 */
319 level = !level;
320 }
321 qemu_set_irq(s->irq, level);
322 }
323
324 static void lan9118_mac_changed(lan9118_state *s)
325 {
326 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
327 }
328
329 static void lan9118_reload_eeprom(lan9118_state *s)
330 {
331 int i;
332 if (s->eeprom[0] != 0xa5) {
333 s->e2p_cmd &= ~0x10;
334 DPRINTF("MACADDR load failed\n");
335 return;
336 }
337 for (i = 0; i < 6; i++) {
338 s->conf.macaddr.a[i] = s->eeprom[i + 1];
339 }
340 s->e2p_cmd |= 0x10;
341 DPRINTF("MACADDR loaded from eeprom\n");
342 lan9118_mac_changed(s);
343 }
344
345 static void phy_update_irq(lan9118_state *s)
346 {
347 if (s->phy_int & s->phy_int_mask) {
348 s->int_sts |= PHY_INT;
349 } else {
350 s->int_sts &= ~PHY_INT;
351 }
352 lan9118_update(s);
353 }
354
355 static void phy_update_link(lan9118_state *s)
356 {
357 /* Autonegotiation status mirrors link status. */
358 if (s->nic->nc.link_down) {
359 s->phy_status &= ~0x0024;
360 s->phy_int |= PHY_INT_DOWN;
361 } else {
362 s->phy_status |= 0x0024;
363 s->phy_int |= PHY_INT_ENERGYON;
364 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
365 }
366 phy_update_irq(s);
367 }
368
369 static void lan9118_set_link(VLANClientState *nc)
370 {
371 phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque);
372 }
373
374 static void phy_reset(lan9118_state *s)
375 {
376 s->phy_status = 0x7809;
377 s->phy_control = 0x3000;
378 s->phy_advertise = 0x01e1;
379 s->phy_int_mask = 0;
380 s->phy_int = 0;
381 phy_update_link(s);
382 }
383
384 static void lan9118_reset(DeviceState *d)
385 {
386 lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d));
387 s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
388 s->int_sts = 0;
389 s->int_en = 0;
390 s->fifo_int = 0x48000000;
391 s->rx_cfg = 0;
392 s->tx_cfg = 0;
393 s->hw_cfg = 0x00050000;
394 s->pmt_ctrl &= 0x45;
395 s->gpio_cfg = 0;
396 s->txp->fifo_used = 0;
397 s->txp->state = TX_IDLE;
398 s->txp->cmd_a = 0xffffffffu;
399 s->txp->cmd_b = 0xffffffffu;
400 s->txp->len = 0;
401 s->txp->fifo_used = 0;
402 s->tx_fifo_size = 4608;
403 s->tx_status_fifo_used = 0;
404 s->rx_status_fifo_size = 704;
405 s->rx_fifo_size = 2640;
406 s->rx_fifo_used = 0;
407 s->rx_status_fifo_size = 176;
408 s->rx_status_fifo_used = 0;
409 s->rxp_offset = 0;
410 s->rxp_size = 0;
411 s->rxp_pad = 0;
412 s->rx_packet_size_tail = s->rx_packet_size_head;
413 s->rx_packet_size[s->rx_packet_size_head] = 0;
414 s->mac_cmd = 0;
415 s->mac_data = 0;
416 s->afc_cfg = 0;
417 s->e2p_cmd = 0;
418 s->e2p_data = 0;
419 s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
420
421 ptimer_stop(s->timer);
422 ptimer_set_count(s->timer, 0xffff);
423 s->gpt_cfg = 0xffff;
424
425 s->mac_cr = MAC_CR_PRMS;
426 s->mac_hashh = 0;
427 s->mac_hashl = 0;
428 s->mac_mii_acc = 0;
429 s->mac_mii_data = 0;
430 s->mac_flow = 0;
431
432 phy_reset(s);
433
434 s->eeprom_writable = 0;
435 lan9118_reload_eeprom(s);
436 }
437
438 static int lan9118_can_receive(VLANClientState *nc)
439 {
440 return 1;
441 }
442
443 static void rx_fifo_push(lan9118_state *s, uint32_t val)
444 {
445 int fifo_pos;
446 fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
447 if (fifo_pos >= s->rx_fifo_size)
448 fifo_pos -= s->rx_fifo_size;
449 s->rx_fifo[fifo_pos] = val;
450 s->rx_fifo_used++;
451 }
452
453 /* Return nonzero if the packet is accepted by the filter. */
454 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
455 {
456 int multicast;
457 uint32_t hash;
458
459 if (s->mac_cr & MAC_CR_PRMS) {
460 return 1;
461 }
462 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
463 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
464 return (s->mac_cr & MAC_CR_BCAST) == 0;
465 }
466
467 multicast = addr[0] & 1;
468 if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
469 return 1;
470 }
471 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
472 : (s->mac_cr & MAC_CR_HO) == 0) {
473 /* Exact matching. */
474 hash = memcmp(addr, s->conf.macaddr.a, 6);
475 if (s->mac_cr & MAC_CR_INVFILT) {
476 return hash != 0;
477 } else {
478 return hash == 0;
479 }
480 } else {
481 /* Hash matching */
482 hash = (crc32(~0, addr, 6) >> 26);
483 if (hash & 0x20) {
484 return (s->mac_hashh >> (hash & 0x1f)) & 1;
485 } else {
486 return (s->mac_hashl >> (hash & 0x1f)) & 1;
487 }
488 }
489 }
490
491 static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf,
492 size_t size)
493 {
494 lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
495 int fifo_len;
496 int offset;
497 int src_pos;
498 int n;
499 int filter;
500 uint32_t val;
501 uint32_t crc;
502 uint32_t status;
503
504 if ((s->mac_cr & MAC_CR_RXEN) == 0) {
505 return -1;
506 }
507
508 if (size >= 2048 || size < 14) {
509 return -1;
510 }
511
512 /* TODO: Implement FIFO overflow notification. */
513 if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
514 return -1;
515 }
516
517 filter = lan9118_filter(s, buf);
518 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
519 return size;
520 }
521
522 offset = (s->rx_cfg >> 8) & 0x1f;
523 n = offset & 3;
524 fifo_len = (size + n + 3) >> 2;
525 /* Add a word for the CRC. */
526 fifo_len++;
527 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
528 return -1;
529 }
530
531 DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
532 (int)size, fifo_len, filter ? "pass" : "fail");
533 val = 0;
534 crc = bswap32(crc32(~0, buf, size));
535 for (src_pos = 0; src_pos < size; src_pos++) {
536 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
537 n++;
538 if (n == 4) {
539 n = 0;
540 rx_fifo_push(s, val);
541 val = 0;
542 }
543 }
544 if (n) {
545 val >>= ((4 - n) * 8);
546 val |= crc << (n * 8);
547 rx_fifo_push(s, val);
548 val = crc >> ((4 - n) * 8);
549 rx_fifo_push(s, val);
550 } else {
551 rx_fifo_push(s, crc);
552 }
553 n = s->rx_status_fifo_head + s->rx_status_fifo_used;
554 if (n >= s->rx_status_fifo_size) {
555 n -= s->rx_status_fifo_size;
556 }
557 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
558 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
559 s->rx_status_fifo_used++;
560
561 status = (size + 4) << 16;
562 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
563 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
564 status |= 0x00002000;
565 } else if (buf[0] & 1) {
566 status |= 0x00000400;
567 }
568 if (!filter) {
569 status |= 0x40000000;
570 }
571 s->rx_status_fifo[n] = status;
572
573 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
574 s->int_sts |= RSFL_INT;
575 }
576 lan9118_update(s);
577
578 return size;
579 }
580
581 static uint32_t rx_fifo_pop(lan9118_state *s)
582 {
583 int n;
584 uint32_t val;
585
586 if (s->rxp_size == 0 && s->rxp_pad == 0) {
587 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
588 s->rx_packet_size[s->rx_packet_size_head] = 0;
589 if (s->rxp_size != 0) {
590 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
591 s->rxp_offset = (s->rx_cfg >> 10) & 7;
592 n = s->rxp_offset + s->rxp_size;
593 switch (s->rx_cfg >> 30) {
594 case 1:
595 n = (-n) & 3;
596 break;
597 case 2:
598 n = (-n) & 7;
599 break;
600 default:
601 n = 0;
602 break;
603 }
604 s->rxp_pad = n;
605 DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
606 s->rxp_size, s->rxp_offset, s->rxp_pad);
607 }
608 }
609 if (s->rxp_offset > 0) {
610 s->rxp_offset--;
611 val = 0;
612 } else if (s->rxp_size > 0) {
613 s->rxp_size--;
614 val = s->rx_fifo[s->rx_fifo_head++];
615 if (s->rx_fifo_head >= s->rx_fifo_size) {
616 s->rx_fifo_head -= s->rx_fifo_size;
617 }
618 s->rx_fifo_used--;
619 } else if (s->rxp_pad > 0) {
620 s->rxp_pad--;
621 val = 0;
622 } else {
623 DPRINTF("RX underflow\n");
624 s->int_sts |= RXE_INT;
625 val = 0;
626 }
627 lan9118_update(s);
628 return val;
629 }
630
631 static void do_tx_packet(lan9118_state *s)
632 {
633 int n;
634 uint32_t status;
635
636 /* FIXME: Honor TX disable, and allow queueing of packets. */
637 if (s->phy_control & 0x4000) {
638 /* This assumes the receive routine doesn't touch the VLANClient. */
639 lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len);
640 } else {
641 qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len);
642 }
643 s->txp->fifo_used = 0;
644
645 if (s->tx_status_fifo_used == 512) {
646 /* Status FIFO full */
647 return;
648 }
649 /* Add entry to status FIFO. */
650 status = s->txp->cmd_b & 0xffff0000u;
651 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
652 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
653 s->tx_status_fifo[n] = status;
654 s->tx_status_fifo_used++;
655 if (s->tx_status_fifo_used == 512) {
656 s->int_sts |= TSFF_INT;
657 /* TODO: Stop transmission. */
658 }
659 }
660
661 static uint32_t rx_status_fifo_pop(lan9118_state *s)
662 {
663 uint32_t val;
664
665 val = s->rx_status_fifo[s->rx_status_fifo_head];
666 if (s->rx_status_fifo_used != 0) {
667 s->rx_status_fifo_used--;
668 s->rx_status_fifo_head++;
669 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
670 s->rx_status_fifo_head -= s->rx_status_fifo_size;
671 }
672 /* ??? What value should be returned when the FIFO is empty? */
673 DPRINTF("RX status pop 0x%08x\n", val);
674 }
675 return val;
676 }
677
678 static uint32_t tx_status_fifo_pop(lan9118_state *s)
679 {
680 uint32_t val;
681
682 val = s->tx_status_fifo[s->tx_status_fifo_head];
683 if (s->tx_status_fifo_used != 0) {
684 s->tx_status_fifo_used--;
685 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
686 /* ??? What value should be returned when the FIFO is empty? */
687 }
688 return val;
689 }
690
691 static void tx_fifo_push(lan9118_state *s, uint32_t val)
692 {
693 int n;
694
695 if (s->txp->fifo_used == s->tx_fifo_size) {
696 s->int_sts |= TDFO_INT;
697 return;
698 }
699 switch (s->txp->state) {
700 case TX_IDLE:
701 s->txp->cmd_a = val & 0x831f37ff;
702 s->txp->fifo_used++;
703 s->txp->state = TX_B;
704 break;
705 case TX_B:
706 if (s->txp->cmd_a & 0x2000) {
707 /* First segment */
708 s->txp->cmd_b = val;
709 s->txp->fifo_used++;
710 s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
711 s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f;
712 /* End alignment does not include command words. */
713 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
714 switch ((n >> 24) & 3) {
715 case 1:
716 n = (-n) & 3;
717 break;
718 case 2:
719 n = (-n) & 7;
720 break;
721 default:
722 n = 0;
723 }
724 s->txp->pad = n;
725 s->txp->len = 0;
726 }
727 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
728 s->txp->buffer_size, s->txp->offset, s->txp->pad,
729 s->txp->cmd_a);
730 s->txp->state = TX_DATA;
731 break;
732 case TX_DATA:
733 if (s->txp->offset >= 4) {
734 s->txp->offset -= 4;
735 break;
736 }
737 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
738 s->txp->pad--;
739 } else {
740 n = 4;
741 while (s->txp->offset) {
742 val >>= 8;
743 n--;
744 s->txp->offset--;
745 }
746 /* Documentation is somewhat unclear on the ordering of bytes
747 in FIFO words. Empirical results show it to be little-endian.
748 */
749 /* TODO: FIFO overflow checking. */
750 while (n--) {
751 s->txp->data[s->txp->len] = val & 0xff;
752 s->txp->len++;
753 val >>= 8;
754 s->txp->buffer_size--;
755 }
756 s->txp->fifo_used++;
757 }
758 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
759 if (s->txp->cmd_a & 0x1000) {
760 do_tx_packet(s);
761 }
762 if (s->txp->cmd_a & 0x80000000) {
763 s->int_sts |= TX_IOC_INT;
764 }
765 s->txp->state = TX_IDLE;
766 }
767 break;
768 }
769 }
770
771 static uint32_t do_phy_read(lan9118_state *s, int reg)
772 {
773 uint32_t val;
774
775 switch (reg) {
776 case 0: /* Basic Control */
777 return s->phy_control;
778 case 1: /* Basic Status */
779 return s->phy_status;
780 case 2: /* ID1 */
781 return 0x0007;
782 case 3: /* ID2 */
783 return 0xc0d1;
784 case 4: /* Auto-neg advertisement */
785 return s->phy_advertise;
786 case 5: /* Auto-neg Link Partner Ability */
787 return 0x0f71;
788 case 6: /* Auto-neg Expansion */
789 return 1;
790 /* TODO 17, 18, 27, 29, 30, 31 */
791 case 29: /* Interrupt source. */
792 val = s->phy_int;
793 s->phy_int = 0;
794 phy_update_irq(s);
795 return val;
796 case 30: /* Interrupt mask */
797 return s->phy_int_mask;
798 default:
799 BADF("PHY read reg %d\n", reg);
800 return 0;
801 }
802 }
803
804 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
805 {
806 switch (reg) {
807 case 0: /* Basic Control */
808 if (val & 0x8000) {
809 phy_reset(s);
810 break;
811 }
812 s->phy_control = val & 0x7980;
813 /* Complete autonegotiation immediately. */
814 if (val & 0x1000) {
815 s->phy_status |= 0x0020;
816 }
817 break;
818 case 4: /* Auto-neg advertisement */
819 s->phy_advertise = (val & 0x2d7f) | 0x80;
820 break;
821 /* TODO 17, 18, 27, 31 */
822 case 30: /* Interrupt mask */
823 s->phy_int_mask = val & 0xff;
824 phy_update_irq(s);
825 break;
826 default:
827 BADF("PHY write reg %d = 0x%04x\n", reg, val);
828 }
829 }
830
831 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
832 {
833 switch (reg) {
834 case MAC_CR:
835 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
836 s->int_sts |= RXSTOP_INT;
837 }
838 s->mac_cr = val & ~MAC_CR_RESERVED;
839 DPRINTF("MAC_CR: %08x\n", val);
840 break;
841 case MAC_ADDRH:
842 s->conf.macaddr.a[4] = val & 0xff;
843 s->conf.macaddr.a[5] = (val >> 8) & 0xff;
844 lan9118_mac_changed(s);
845 break;
846 case MAC_ADDRL:
847 s->conf.macaddr.a[0] = val & 0xff;
848 s->conf.macaddr.a[1] = (val >> 8) & 0xff;
849 s->conf.macaddr.a[2] = (val >> 16) & 0xff;
850 s->conf.macaddr.a[3] = (val >> 24) & 0xff;
851 lan9118_mac_changed(s);
852 break;
853 case MAC_HASHH:
854 s->mac_hashh = val;
855 break;
856 case MAC_HASHL:
857 s->mac_hashl = val;
858 break;
859 case MAC_MII_ACC:
860 s->mac_mii_acc = val & 0xffc2;
861 if (val & 2) {
862 DPRINTF("PHY write %d = 0x%04x\n",
863 (val >> 6) & 0x1f, s->mac_mii_data);
864 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
865 } else {
866 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
867 DPRINTF("PHY read %d = 0x%04x\n",
868 (val >> 6) & 0x1f, s->mac_mii_data);
869 }
870 break;
871 case MAC_MII_DATA:
872 s->mac_mii_data = val & 0xffff;
873 break;
874 case MAC_FLOW:
875 s->mac_flow = val & 0xffff0000;
876 break;
877 case MAC_VLAN1:
878 /* Writing to this register changes a condition for
879 * FrameTooLong bit in rx_status. Since we do not set
880 * FrameTooLong anyway, just ignore write to this.
881 */
882 break;
883 default:
884 hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
885 s->mac_cmd & 0xf, val);
886 }
887 }
888
889 static uint32_t do_mac_read(lan9118_state *s, int reg)
890 {
891 switch (reg) {
892 case MAC_CR:
893 return s->mac_cr;
894 case MAC_ADDRH:
895 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
896 case MAC_ADDRL:
897 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
898 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
899 case MAC_HASHH:
900 return s->mac_hashh;
901 break;
902 case MAC_HASHL:
903 return s->mac_hashl;
904 break;
905 case MAC_MII_ACC:
906 return s->mac_mii_acc;
907 case MAC_MII_DATA:
908 return s->mac_mii_data;
909 case MAC_FLOW:
910 return s->mac_flow;
911 default:
912 hw_error("lan9118: Unimplemented MAC register read: %d\n",
913 s->mac_cmd & 0xf);
914 }
915 }
916
917 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
918 {
919 s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr;
920 switch (cmd) {
921 case 0:
922 s->e2p_data = s->eeprom[addr];
923 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
924 break;
925 case 1:
926 s->eeprom_writable = 0;
927 DPRINTF("EEPROM Write Disable\n");
928 break;
929 case 2: /* EWEN */
930 s->eeprom_writable = 1;
931 DPRINTF("EEPROM Write Enable\n");
932 break;
933 case 3: /* WRITE */
934 if (s->eeprom_writable) {
935 s->eeprom[addr] &= s->e2p_data;
936 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
937 } else {
938 DPRINTF("EEPROM Write %d (ignored)\n", addr);
939 }
940 break;
941 case 4: /* WRAL */
942 if (s->eeprom_writable) {
943 for (addr = 0; addr < 128; addr++) {
944 s->eeprom[addr] &= s->e2p_data;
945 }
946 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
947 } else {
948 DPRINTF("EEPROM Write All (ignored)\n");
949 }
950 break;
951 case 5: /* ERASE */
952 if (s->eeprom_writable) {
953 s->eeprom[addr] = 0xff;
954 DPRINTF("EEPROM Erase %d\n", addr);
955 } else {
956 DPRINTF("EEPROM Erase %d (ignored)\n", addr);
957 }
958 break;
959 case 6: /* ERAL */
960 if (s->eeprom_writable) {
961 memset(s->eeprom, 0xff, 128);
962 DPRINTF("EEPROM Erase All\n");
963 } else {
964 DPRINTF("EEPROM Erase All (ignored)\n");
965 }
966 break;
967 case 7: /* RELOAD */
968 lan9118_reload_eeprom(s);
969 break;
970 }
971 }
972
973 static void lan9118_tick(void *opaque)
974 {
975 lan9118_state *s = (lan9118_state *)opaque;
976 if (s->int_en & GPT_INT) {
977 s->int_sts |= GPT_INT;
978 }
979 lan9118_update(s);
980 }
981
982 static void lan9118_writel(void *opaque, target_phys_addr_t offset,
983 uint64_t val, unsigned size)
984 {
985 lan9118_state *s = (lan9118_state *)opaque;
986 offset &= 0xff;
987
988 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
989 if (offset >= 0x20 && offset < 0x40) {
990 /* TX FIFO */
991 tx_fifo_push(s, val);
992 return;
993 }
994 switch (offset) {
995 case CSR_IRQ_CFG:
996 /* TODO: Implement interrupt deassertion intervals. */
997 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
998 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
999 break;
1000 case CSR_INT_STS:
1001 s->int_sts &= ~val;
1002 break;
1003 case CSR_INT_EN:
1004 s->int_en = val & ~RESERVED_INT;
1005 s->int_sts |= val & SW_INT;
1006 break;
1007 case CSR_FIFO_INT:
1008 DPRINTF("FIFO INT levels %08x\n", val);
1009 s->fifo_int = val;
1010 break;
1011 case CSR_RX_CFG:
1012 if (val & 0x8000) {
1013 /* RX_DUMP */
1014 s->rx_fifo_used = 0;
1015 s->rx_status_fifo_used = 0;
1016 s->rx_packet_size_tail = s->rx_packet_size_head;
1017 s->rx_packet_size[s->rx_packet_size_head] = 0;
1018 }
1019 s->rx_cfg = val & 0xcfff1ff0;
1020 break;
1021 case CSR_TX_CFG:
1022 if (val & 0x8000) {
1023 s->tx_status_fifo_used = 0;
1024 }
1025 if (val & 0x4000) {
1026 s->txp->state = TX_IDLE;
1027 s->txp->fifo_used = 0;
1028 s->txp->cmd_a = 0xffffffff;
1029 }
1030 s->tx_cfg = val & 6;
1031 break;
1032 case CSR_HW_CFG:
1033 if (val & 1) {
1034 /* SRST */
1035 lan9118_reset(&s->busdev.qdev);
1036 } else {
1037 s->hw_cfg = val & 0x003f300;
1038 }
1039 break;
1040 case CSR_RX_DP_CTRL:
1041 if (val & 0x80000000) {
1042 /* Skip forward to next packet. */
1043 s->rxp_pad = 0;
1044 s->rxp_offset = 0;
1045 if (s->rxp_size == 0) {
1046 /* Pop a word to start the next packet. */
1047 rx_fifo_pop(s);
1048 s->rxp_pad = 0;
1049 s->rxp_offset = 0;
1050 }
1051 s->rx_fifo_head += s->rxp_size;
1052 if (s->rx_fifo_head >= s->rx_fifo_size) {
1053 s->rx_fifo_head -= s->rx_fifo_size;
1054 }
1055 }
1056 break;
1057 case CSR_PMT_CTRL:
1058 if (val & 0x400) {
1059 phy_reset(s);
1060 }
1061 s->pmt_ctrl &= ~0x34e;
1062 s->pmt_ctrl |= (val & 0x34e);
1063 break;
1064 case CSR_GPIO_CFG:
1065 /* Probably just enabling LEDs. */
1066 s->gpio_cfg = val & 0x7777071f;
1067 break;
1068 case CSR_GPT_CFG:
1069 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
1070 if (val & GPT_TIMER_EN) {
1071 ptimer_set_count(s->timer, val & 0xffff);
1072 ptimer_run(s->timer, 0);
1073 } else {
1074 ptimer_stop(s->timer);
1075 ptimer_set_count(s->timer, 0xffff);
1076 }
1077 }
1078 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1079 break;
1080 case CSR_WORD_SWAP:
1081 /* Ignored because we're in 32-bit mode. */
1082 s->word_swap = val;
1083 break;
1084 case CSR_MAC_CSR_CMD:
1085 s->mac_cmd = val & 0x4000000f;
1086 if (val & 0x80000000) {
1087 if (val & 0x40000000) {
1088 s->mac_data = do_mac_read(s, val & 0xf);
1089 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1090 } else {
1091 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1092 do_mac_write(s, val & 0xf, s->mac_data);
1093 }
1094 }
1095 break;
1096 case CSR_MAC_CSR_DATA:
1097 s->mac_data = val;
1098 break;
1099 case CSR_AFC_CFG:
1100 s->afc_cfg = val & 0x00ffffff;
1101 break;
1102 case CSR_E2P_CMD:
1103 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
1104 break;
1105 case CSR_E2P_DATA:
1106 s->e2p_data = val & 0xff;
1107 break;
1108
1109 default:
1110 hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, (int)val);
1111 break;
1112 }
1113 lan9118_update(s);
1114 }
1115
1116 static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
1117 unsigned size)
1118 {
1119 lan9118_state *s = (lan9118_state *)opaque;
1120
1121 //DPRINTF("Read reg 0x%02x\n", (int)offset);
1122 if (offset < 0x20) {
1123 /* RX FIFO */
1124 return rx_fifo_pop(s);
1125 }
1126 switch (offset) {
1127 case 0x40:
1128 return rx_status_fifo_pop(s);
1129 case 0x44:
1130 return s->rx_status_fifo[s->tx_status_fifo_head];
1131 case 0x48:
1132 return tx_status_fifo_pop(s);
1133 case 0x4c:
1134 return s->tx_status_fifo[s->tx_status_fifo_head];
1135 case CSR_ID_REV:
1136 return 0x01180001;
1137 case CSR_IRQ_CFG:
1138 return s->irq_cfg;
1139 case CSR_INT_STS:
1140 return s->int_sts;
1141 case CSR_INT_EN:
1142 return s->int_en;
1143 case CSR_BYTE_TEST:
1144 return 0x87654321;
1145 case CSR_FIFO_INT:
1146 return s->fifo_int;
1147 case CSR_RX_CFG:
1148 return s->rx_cfg;
1149 case CSR_TX_CFG:
1150 return s->tx_cfg;
1151 case CSR_HW_CFG:
1152 return s->hw_cfg | 0x4;
1153 case CSR_RX_DP_CTRL:
1154 return 0;
1155 case CSR_RX_FIFO_INF:
1156 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1157 case CSR_TX_FIFO_INF:
1158 return (s->tx_status_fifo_used << 16)
1159 | (s->tx_fifo_size - s->txp->fifo_used);
1160 case CSR_PMT_CTRL:
1161 return s->pmt_ctrl;
1162 case CSR_GPIO_CFG:
1163 return s->gpio_cfg;
1164 case CSR_GPT_CFG:
1165 return s->gpt_cfg;
1166 case CSR_GPT_CNT:
1167 return ptimer_get_count(s->timer);
1168 case CSR_WORD_SWAP:
1169 return s->word_swap;
1170 case CSR_FREE_RUN:
1171 return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start;
1172 case CSR_RX_DROP:
1173 /* TODO: Implement dropped frames counter. */
1174 return 0;
1175 case CSR_MAC_CSR_CMD:
1176 return s->mac_cmd;
1177 case CSR_MAC_CSR_DATA:
1178 return s->mac_data;
1179 case CSR_AFC_CFG:
1180 return s->afc_cfg;
1181 case CSR_E2P_CMD:
1182 return s->e2p_cmd;
1183 case CSR_E2P_DATA:
1184 return s->e2p_data;
1185 }
1186 hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset);
1187 return 0;
1188 }
1189
1190 static const MemoryRegionOps lan9118_mem_ops = {
1191 .read = lan9118_readl,
1192 .write = lan9118_writel,
1193 .endianness = DEVICE_NATIVE_ENDIAN,
1194 };
1195
1196 static void lan9118_cleanup(VLANClientState *nc)
1197 {
1198 lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
1199
1200 s->nic = NULL;
1201 }
1202
1203 static NetClientInfo net_lan9118_info = {
1204 .type = NET_CLIENT_TYPE_NIC,
1205 .size = sizeof(NICState),
1206 .can_receive = lan9118_can_receive,
1207 .receive = lan9118_receive,
1208 .cleanup = lan9118_cleanup,
1209 .link_status_changed = lan9118_set_link,
1210 };
1211
1212 static int lan9118_init1(SysBusDevice *dev)
1213 {
1214 lan9118_state *s = FROM_SYSBUS(lan9118_state, dev);
1215 QEMUBH *bh;
1216 int i;
1217
1218 memory_region_init_io(&s->mmio, &lan9118_mem_ops, s, "lan9118-mmio", 0x100);
1219 sysbus_init_mmio(dev, &s->mmio);
1220 sysbus_init_irq(dev, &s->irq);
1221 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1222
1223 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1224 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
1225 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1226 s->eeprom[0] = 0xa5;
1227 for (i = 0; i < 6; i++) {
1228 s->eeprom[i + 1] = s->conf.macaddr.a[i];
1229 }
1230 s->pmt_ctrl = 1;
1231 s->txp = &s->tx_packet;
1232
1233 bh = qemu_bh_new(lan9118_tick, s);
1234 s->timer = ptimer_init(bh);
1235 ptimer_set_freq(s->timer, 10000);
1236 ptimer_set_limit(s->timer, 0xffff, 1);
1237
1238 return 0;
1239 }
1240
1241 static Property lan9118_properties[] = {
1242 DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1243 DEFINE_PROP_END_OF_LIST(),
1244 };
1245
1246 static void lan9118_class_init(ObjectClass *klass, void *data)
1247 {
1248 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1249
1250 k->init = lan9118_init1;
1251 }
1252
1253 static DeviceInfo lan9118_info = {
1254 .name = "lan9118",
1255 .size = sizeof(lan9118_state),
1256 .reset = lan9118_reset,
1257 .vmsd = &vmstate_lan9118,
1258 .props = lan9118_properties,
1259 .class_init = lan9118_class_init,
1260 };
1261
1262 static void lan9118_register_devices(void)
1263 {
1264 sysbus_register_withprop(&lan9118_info);
1265 }
1266
1267 /* Legacy helper function. Should go away when machine config files are
1268 implemented. */
1269 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1270 {
1271 DeviceState *dev;
1272 SysBusDevice *s;
1273
1274 qemu_check_nic_model(nd, "lan9118");
1275 dev = qdev_create(NULL, "lan9118");
1276 qdev_set_nic_properties(dev, nd);
1277 qdev_init_nofail(dev);
1278 s = sysbus_from_qdev(dev);
1279 sysbus_mmio_map(s, 0, base);
1280 sysbus_connect_irq(s, 0, irq);
1281 }
1282
1283 device_init(lan9118_register_devices)