Add access control support to qemu bridge helper
[qemu.git] / hw / lm32_timer.c
1 /*
2 * QEMU model of the LatticeMico32 timer block.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32timer.pdf
22 */
23
24 #include "hw.h"
25 #include "sysbus.h"
26 #include "trace.h"
27 #include "qemu-timer.h"
28 #include "ptimer.h"
29 #include "qemu-error.h"
30
31 #define DEFAULT_FREQUENCY (50*1000000)
32
33 enum {
34 R_SR = 0,
35 R_CR,
36 R_PERIOD,
37 R_SNAPSHOT,
38 R_MAX
39 };
40
41 enum {
42 SR_TO = (1 << 0),
43 SR_RUN = (1 << 1),
44 };
45
46 enum {
47 CR_ITO = (1 << 0),
48 CR_CONT = (1 << 1),
49 CR_START = (1 << 2),
50 CR_STOP = (1 << 3),
51 };
52
53 struct LM32TimerState {
54 SysBusDevice busdev;
55 MemoryRegion iomem;
56
57 QEMUBH *bh;
58 ptimer_state *ptimer;
59
60 qemu_irq irq;
61 uint32_t freq_hz;
62
63 uint32_t regs[R_MAX];
64 };
65 typedef struct LM32TimerState LM32TimerState;
66
67 static void timer_update_irq(LM32TimerState *s)
68 {
69 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
70
71 trace_lm32_timer_irq_state(state);
72 qemu_set_irq(s->irq, state);
73 }
74
75 static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
76 {
77 LM32TimerState *s = opaque;
78 uint32_t r = 0;
79
80 addr >>= 2;
81 switch (addr) {
82 case R_SR:
83 case R_CR:
84 case R_PERIOD:
85 r = s->regs[addr];
86 break;
87 case R_SNAPSHOT:
88 r = (uint32_t)ptimer_get_count(s->ptimer);
89 break;
90 default:
91 error_report("lm32_timer: read access to unknown register 0x"
92 TARGET_FMT_plx, addr << 2);
93 break;
94 }
95
96 trace_lm32_timer_memory_read(addr << 2, r);
97 return r;
98 }
99
100 static void timer_write(void *opaque, target_phys_addr_t addr,
101 uint64_t value, unsigned size)
102 {
103 LM32TimerState *s = opaque;
104
105 trace_lm32_timer_memory_write(addr, value);
106
107 addr >>= 2;
108 switch (addr) {
109 case R_SR:
110 s->regs[R_SR] &= ~SR_TO;
111 break;
112 case R_CR:
113 s->regs[R_CR] = value;
114 if (s->regs[R_CR] & CR_START) {
115 ptimer_run(s->ptimer, 1);
116 }
117 if (s->regs[R_CR] & CR_STOP) {
118 ptimer_stop(s->ptimer);
119 }
120 break;
121 case R_PERIOD:
122 s->regs[R_PERIOD] = value;
123 ptimer_set_count(s->ptimer, value);
124 break;
125 case R_SNAPSHOT:
126 error_report("lm32_timer: write access to read only register 0x"
127 TARGET_FMT_plx, addr << 2);
128 break;
129 default:
130 error_report("lm32_timer: write access to unknown register 0x"
131 TARGET_FMT_plx, addr << 2);
132 break;
133 }
134 timer_update_irq(s);
135 }
136
137 static const MemoryRegionOps timer_ops = {
138 .read = timer_read,
139 .write = timer_write,
140 .endianness = DEVICE_NATIVE_ENDIAN,
141 .valid = {
142 .min_access_size = 4,
143 .max_access_size = 4,
144 },
145 };
146
147 static void timer_hit(void *opaque)
148 {
149 LM32TimerState *s = opaque;
150
151 trace_lm32_timer_hit();
152
153 s->regs[R_SR] |= SR_TO;
154
155 if (s->regs[R_CR] & CR_CONT) {
156 ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
157 ptimer_run(s->ptimer, 1);
158 }
159 timer_update_irq(s);
160 }
161
162 static void timer_reset(DeviceState *d)
163 {
164 LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev);
165 int i;
166
167 for (i = 0; i < R_MAX; i++) {
168 s->regs[i] = 0;
169 }
170 ptimer_stop(s->ptimer);
171 }
172
173 static int lm32_timer_init(SysBusDevice *dev)
174 {
175 LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
176
177 sysbus_init_irq(dev, &s->irq);
178
179 s->bh = qemu_bh_new(timer_hit, s);
180 s->ptimer = ptimer_init(s->bh);
181 ptimer_set_freq(s->ptimer, s->freq_hz);
182
183 memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4);
184 sysbus_init_mmio(dev, &s->iomem);
185
186 return 0;
187 }
188
189 static const VMStateDescription vmstate_lm32_timer = {
190 .name = "lm32-timer",
191 .version_id = 1,
192 .minimum_version_id = 1,
193 .minimum_version_id_old = 1,
194 .fields = (VMStateField[]) {
195 VMSTATE_PTIMER(ptimer, LM32TimerState),
196 VMSTATE_UINT32(freq_hz, LM32TimerState),
197 VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
198 VMSTATE_END_OF_LIST()
199 }
200 };
201
202 static Property lm32_timer_properties[] = {
203 DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
204 DEFINE_PROP_END_OF_LIST(),
205 };
206
207 static void lm32_timer_class_init(ObjectClass *klass, void *data)
208 {
209 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
210
211 k->init = lm32_timer_init;
212 }
213
214 static DeviceInfo lm32_timer_info = {
215 .name = "lm32-timer",
216 .size = sizeof(LM32TimerState),
217 .vmsd = &vmstate_lm32_timer,
218 .reset = timer_reset,
219 .props = lm32_timer_properties,
220 .class_init = lm32_timer_class_init,
221 };
222
223 static void lm32_timer_register(void)
224 {
225 sysbus_register_withprop(&lm32_timer_info);
226 }
227
228 device_init(lm32_timer_register)