linux-user, arm: add syscall table generation support
[qemu.git] / hw / m68k / mcf5208.c
1 /*
2 * Motorola ColdFire MCF5208 SoC emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
6 * This code is licensed under the GPL
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "qemu-common.h"
14 #include "cpu.h"
15 #include "hw/hw.h"
16 #include "hw/irq.h"
17 #include "hw/m68k/mcf.h"
18 #include "hw/m68k/mcf_fec.h"
19 #include "qemu/timer.h"
20 #include "hw/ptimer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/qtest.h"
23 #include "net/net.h"
24 #include "hw/boards.h"
25 #include "hw/loader.h"
26 #include "hw/sysbus.h"
27 #include "elf.h"
28 #include "exec/address-spaces.h"
29
30 #define SYS_FREQ 166666666
31
32 #define ROM_SIZE 0x200000
33
34 #define PCSR_EN 0x0001
35 #define PCSR_RLD 0x0002
36 #define PCSR_PIF 0x0004
37 #define PCSR_PIE 0x0008
38 #define PCSR_OVW 0x0010
39 #define PCSR_DBG 0x0020
40 #define PCSR_DOZE 0x0040
41 #define PCSR_PRE_SHIFT 8
42 #define PCSR_PRE_MASK 0x0f00
43
44 typedef struct {
45 MemoryRegion iomem;
46 qemu_irq irq;
47 ptimer_state *timer;
48 uint16_t pcsr;
49 uint16_t pmr;
50 uint16_t pcntr;
51 } m5208_timer_state;
52
53 static void m5208_timer_update(m5208_timer_state *s)
54 {
55 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
56 qemu_irq_raise(s->irq);
57 else
58 qemu_irq_lower(s->irq);
59 }
60
61 static void m5208_timer_write(void *opaque, hwaddr offset,
62 uint64_t value, unsigned size)
63 {
64 m5208_timer_state *s = (m5208_timer_state *)opaque;
65 int prescale;
66 int limit;
67 switch (offset) {
68 case 0:
69 /* The PIF bit is set-to-clear. */
70 if (value & PCSR_PIF) {
71 s->pcsr &= ~PCSR_PIF;
72 value &= ~PCSR_PIF;
73 }
74 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
75 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
76 s->pcsr = value;
77 m5208_timer_update(s);
78 return;
79 }
80
81 ptimer_transaction_begin(s->timer);
82 if (s->pcsr & PCSR_EN)
83 ptimer_stop(s->timer);
84
85 s->pcsr = value;
86
87 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
88 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
89 if (s->pcsr & PCSR_RLD)
90 limit = s->pmr;
91 else
92 limit = 0xffff;
93 ptimer_set_limit(s->timer, limit, 0);
94
95 if (s->pcsr & PCSR_EN)
96 ptimer_run(s->timer, 0);
97 ptimer_transaction_commit(s->timer);
98 break;
99 case 2:
100 ptimer_transaction_begin(s->timer);
101 s->pmr = value;
102 s->pcsr &= ~PCSR_PIF;
103 if ((s->pcsr & PCSR_RLD) == 0) {
104 if (s->pcsr & PCSR_OVW)
105 ptimer_set_count(s->timer, value);
106 } else {
107 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
108 }
109 ptimer_transaction_commit(s->timer);
110 break;
111 case 4:
112 break;
113 default:
114 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
115 break;
116 }
117 m5208_timer_update(s);
118 }
119
120 static void m5208_timer_trigger(void *opaque)
121 {
122 m5208_timer_state *s = (m5208_timer_state *)opaque;
123 s->pcsr |= PCSR_PIF;
124 m5208_timer_update(s);
125 }
126
127 static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
128 unsigned size)
129 {
130 m5208_timer_state *s = (m5208_timer_state *)opaque;
131 switch (addr) {
132 case 0:
133 return s->pcsr;
134 case 2:
135 return s->pmr;
136 case 4:
137 return ptimer_get_count(s->timer);
138 default:
139 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
140 return 0;
141 }
142 }
143
144 static const MemoryRegionOps m5208_timer_ops = {
145 .read = m5208_timer_read,
146 .write = m5208_timer_write,
147 .endianness = DEVICE_NATIVE_ENDIAN,
148 };
149
150 static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
151 unsigned size)
152 {
153 switch (addr) {
154 case 0x110: /* SDCS0 */
155 {
156 int n;
157 for (n = 0; n < 32; n++) {
158 if (ram_size < (2u << n))
159 break;
160 }
161 return (n - 1) | 0x40000000;
162 }
163 case 0x114: /* SDCS1 */
164 return 0;
165
166 default:
167 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
168 return 0;
169 }
170 }
171
172 static void m5208_sys_write(void *opaque, hwaddr addr,
173 uint64_t value, unsigned size)
174 {
175 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
176 }
177
178 static const MemoryRegionOps m5208_sys_ops = {
179 .read = m5208_sys_read,
180 .write = m5208_sys_write,
181 .endianness = DEVICE_NATIVE_ENDIAN,
182 };
183
184 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
185 {
186 MemoryRegion *iomem = g_new(MemoryRegion, 1);
187 m5208_timer_state *s;
188 int i;
189
190 /* SDRAMC. */
191 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
192 memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
193 /* Timers. */
194 for (i = 0; i < 2; i++) {
195 s = g_new0(m5208_timer_state, 1);
196 s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
197 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
198 "m5208-timer", 0x00004000);
199 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
200 &s->iomem);
201 s->irq = pic[4 + i];
202 }
203 }
204
205 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base,
206 qemu_irq *irqs)
207 {
208 DeviceState *dev;
209 SysBusDevice *s;
210 int i;
211
212 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
213 dev = qdev_create(NULL, TYPE_MCF_FEC_NET);
214 qdev_set_nic_properties(dev, nd);
215 qdev_init_nofail(dev);
216
217 s = SYS_BUS_DEVICE(dev);
218 for (i = 0; i < FEC_NUM_IRQ; i++) {
219 sysbus_connect_irq(s, i, irqs[i]);
220 }
221
222 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0));
223 }
224
225 static void mcf5208evb_init(MachineState *machine)
226 {
227 ram_addr_t ram_size = machine->ram_size;
228 const char *kernel_filename = machine->kernel_filename;
229 M68kCPU *cpu;
230 CPUM68KState *env;
231 int kernel_size;
232 uint64_t elf_entry;
233 hwaddr entry;
234 qemu_irq *pic;
235 MemoryRegion *address_space_mem = get_system_memory();
236 MemoryRegion *rom = g_new(MemoryRegion, 1);
237 MemoryRegion *sram = g_new(MemoryRegion, 1);
238
239 cpu = M68K_CPU(cpu_create(machine->cpu_type));
240 env = &cpu->env;
241
242 /* Initialize CPU registers. */
243 env->vbr = 0;
244 /* TODO: Configure BARs. */
245
246 /* ROM at 0x00000000 */
247 memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal);
248 memory_region_add_subregion(address_space_mem, 0x00000000, rom);
249
250 /* DRAM at 0x40000000 */
251 memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram);
252
253 /* Internal SRAM. */
254 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal);
255 memory_region_add_subregion(address_space_mem, 0x80000000, sram);
256
257 /* Internal peripherals. */
258 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
259
260 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0));
261 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1));
262 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2));
263
264 mcf5208_sys_init(address_space_mem, pic);
265
266 if (nb_nics > 1) {
267 error_report("Too many NICs");
268 exit(1);
269 }
270 if (nd_table[0].used) {
271 mcf_fec_init(address_space_mem, &nd_table[0],
272 0xfc030000, pic + 36);
273 }
274
275 g_free(pic);
276
277 /* 0xfc000000 SCM. */
278 /* 0xfc004000 XBS. */
279 /* 0xfc008000 FlexBus CS. */
280 /* 0xfc030000 FEC. */
281 /* 0xfc040000 SCM + Power management. */
282 /* 0xfc044000 eDMA. */
283 /* 0xfc048000 INTC. */
284 /* 0xfc058000 I2C. */
285 /* 0xfc05c000 QSPI. */
286 /* 0xfc060000 UART0. */
287 /* 0xfc064000 UART0. */
288 /* 0xfc068000 UART0. */
289 /* 0xfc070000 DMA timers. */
290 /* 0xfc080000 PIT0. */
291 /* 0xfc084000 PIT1. */
292 /* 0xfc088000 EPORT. */
293 /* 0xfc08c000 Watchdog. */
294 /* 0xfc090000 clock module. */
295 /* 0xfc0a0000 CCM + reset. */
296 /* 0xfc0a4000 GPIO. */
297 /* 0xfc0a8000 SDRAM controller. */
298
299 /* Load firmware */
300 if (bios_name) {
301 char *fn;
302 uint8_t *ptr;
303
304 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
305 if (!fn) {
306 error_report("Could not find ROM image '%s'", bios_name);
307 exit(1);
308 }
309 if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
310 error_report("Could not load ROM image '%s'", bios_name);
311 exit(1);
312 }
313 g_free(fn);
314 /* Initial PC is always at offset 4 in firmware binaries */
315 ptr = rom_ptr(0x4, 4);
316 assert(ptr != NULL);
317 env->pc = ldl_p(ptr);
318 }
319
320 /* Load kernel. */
321 if (!kernel_filename) {
322 if (qtest_enabled() || bios_name) {
323 return;
324 }
325 error_report("Kernel image must be specified");
326 exit(1);
327 }
328
329 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
330 NULL, NULL, NULL, 1, EM_68K, 0, 0);
331 entry = elf_entry;
332 if (kernel_size < 0) {
333 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
334 NULL, NULL);
335 }
336 if (kernel_size < 0) {
337 kernel_size = load_image_targphys(kernel_filename, 0x40000000,
338 ram_size);
339 entry = 0x40000000;
340 }
341 if (kernel_size < 0) {
342 error_report("Could not load kernel '%s'", kernel_filename);
343 exit(1);
344 }
345
346 env->pc = entry;
347 }
348
349 static void mcf5208evb_machine_init(MachineClass *mc)
350 {
351 mc->desc = "MCF5208EVB";
352 mc->init = mcf5208evb_init;
353 mc->is_default = true;
354 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208");
355 mc->default_ram_id = "mcf5208.ram";
356 }
357
358 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)