capstone: Update to upstream "next" branch
[qemu.git] / hw / m68k / mcf_intc.c
1 /*
2 * ColdFire Interrupt Controller emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
6 * This code is licensed under the GPL
7 */
8
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "qemu/module.h"
12 #include "qemu/log.h"
13 #include "cpu.h"
14 #include "hw/hw.h"
15 #include "hw/irq.h"
16 #include "hw/sysbus.h"
17 #include "hw/m68k/mcf.h"
18 #include "qom/object.h"
19
20 #define TYPE_MCF_INTC "mcf-intc"
21 OBJECT_DECLARE_SIMPLE_TYPE(mcf_intc_state, MCF_INTC)
22
23 struct mcf_intc_state {
24 SysBusDevice parent_obj;
25
26 MemoryRegion iomem;
27 uint64_t ipr;
28 uint64_t imr;
29 uint64_t ifr;
30 uint64_t enabled;
31 uint8_t icr[64];
32 M68kCPU *cpu;
33 int active_vector;
34 };
35
36 static void mcf_intc_update(mcf_intc_state *s)
37 {
38 uint64_t active;
39 int i;
40 int best;
41 int best_level;
42
43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
44 best_level = 0;
45 best = 64;
46 if (active) {
47 for (i = 0; i < 64; i++) {
48 if ((active & 1) != 0 && s->icr[i] >= best_level) {
49 best_level = s->icr[i];
50 best = i;
51 }
52 active >>= 1;
53 }
54 }
55 s->active_vector = ((best == 64) ? 24 : (best + 64));
56 m68k_set_irq_level(s->cpu, best_level, s->active_vector);
57 }
58
59 static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
60 unsigned size)
61 {
62 int offset;
63 mcf_intc_state *s = (mcf_intc_state *)opaque;
64 offset = addr & 0xff;
65 if (offset >= 0x40 && offset < 0x80) {
66 return s->icr[offset - 0x40];
67 }
68 switch (offset) {
69 case 0x00:
70 return (uint32_t)(s->ipr >> 32);
71 case 0x04:
72 return (uint32_t)s->ipr;
73 case 0x08:
74 return (uint32_t)(s->imr >> 32);
75 case 0x0c:
76 return (uint32_t)s->imr;
77 case 0x10:
78 return (uint32_t)(s->ifr >> 32);
79 case 0x14:
80 return (uint32_t)s->ifr;
81 case 0xe0: /* SWIACK. */
82 return s->active_vector;
83 case 0xe1: case 0xe2: case 0xe3: case 0xe4:
84 case 0xe5: case 0xe6: case 0xe7:
85 /* LnIACK */
86 qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
87 __func__, offset);
88 /* fallthru */
89 default:
90 return 0;
91 }
92 }
93
94 static void mcf_intc_write(void *opaque, hwaddr addr,
95 uint64_t val, unsigned size)
96 {
97 int offset;
98 mcf_intc_state *s = (mcf_intc_state *)opaque;
99 offset = addr & 0xff;
100 if (offset >= 0x40 && offset < 0x80) {
101 int n = offset - 0x40;
102 s->icr[n] = val;
103 if (val == 0)
104 s->enabled &= ~(1ull << n);
105 else
106 s->enabled |= (1ull << n);
107 mcf_intc_update(s);
108 return;
109 }
110 switch (offset) {
111 case 0x00: case 0x04:
112 /* Ignore IPR writes. */
113 return;
114 case 0x08:
115 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
116 break;
117 case 0x0c:
118 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
119 break;
120 case 0x1c:
121 if (val & 0x40) {
122 s->imr = ~0ull;
123 } else {
124 s->imr |= (0x1ull << (val & 0x3f));
125 }
126 break;
127 case 0x1d:
128 if (val & 0x40) {
129 s->imr = 0ull;
130 } else {
131 s->imr &= ~(0x1ull << (val & 0x3f));
132 }
133 break;
134 default:
135 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n",
136 __func__, offset);
137 return;
138 }
139 mcf_intc_update(s);
140 }
141
142 static void mcf_intc_set_irq(void *opaque, int irq, int level)
143 {
144 mcf_intc_state *s = (mcf_intc_state *)opaque;
145 if (irq >= 64)
146 return;
147 if (level)
148 s->ipr |= 1ull << irq;
149 else
150 s->ipr &= ~(1ull << irq);
151 mcf_intc_update(s);
152 }
153
154 static void mcf_intc_reset(DeviceState *dev)
155 {
156 mcf_intc_state *s = MCF_INTC(dev);
157
158 s->imr = ~0ull;
159 s->ipr = 0;
160 s->ifr = 0;
161 s->enabled = 0;
162 memset(s->icr, 0, 64);
163 s->active_vector = 24;
164 }
165
166 static const MemoryRegionOps mcf_intc_ops = {
167 .read = mcf_intc_read,
168 .write = mcf_intc_write,
169 .endianness = DEVICE_NATIVE_ENDIAN,
170 };
171
172 static void mcf_intc_instance_init(Object *obj)
173 {
174 mcf_intc_state *s = MCF_INTC(obj);
175
176 memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
177 }
178
179 static void mcf_intc_class_init(ObjectClass *oc, void *data)
180 {
181 DeviceClass *dc = DEVICE_CLASS(oc);
182
183 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
184 dc->reset = mcf_intc_reset;
185 }
186
187 static const TypeInfo mcf_intc_gate_info = {
188 .name = TYPE_MCF_INTC,
189 .parent = TYPE_SYS_BUS_DEVICE,
190 .instance_size = sizeof(mcf_intc_state),
191 .instance_init = mcf_intc_instance_init,
192 .class_init = mcf_intc_class_init,
193 };
194
195 static void mcf_intc_register_types(void)
196 {
197 type_register_static(&mcf_intc_gate_info);
198 }
199
200 type_init(mcf_intc_register_types)
201
202 qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
203 hwaddr base,
204 M68kCPU *cpu)
205 {
206 DeviceState *dev;
207 mcf_intc_state *s;
208
209 dev = qdev_new(TYPE_MCF_INTC);
210 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
211
212 s = MCF_INTC(dev);
213 s->cpu = cpu;
214
215 memory_region_add_subregion(sysmem, base, &s->iomem);
216
217 return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
218 }