Add access control support to qemu bridge helper
[qemu.git] / hw / mc146818rtc.c
1 /*
2 * QEMU MC146818 RTC emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sysemu.h"
27 #include "pc.h"
28 #include "apic.h"
29 #include "isa.h"
30 #include "mc146818rtc.h"
31
32 //#define DEBUG_CMOS
33 //#define DEBUG_COALESCED
34
35 #ifdef DEBUG_CMOS
36 # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
37 #else
38 # define CMOS_DPRINTF(format, ...) do { } while (0)
39 #endif
40
41 #ifdef DEBUG_COALESCED
42 # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
43 #else
44 # define DPRINTF_C(format, ...) do { } while (0)
45 #endif
46
47 #define RTC_REINJECT_ON_ACK_COUNT 20
48
49 #define RTC_SECONDS 0
50 #define RTC_SECONDS_ALARM 1
51 #define RTC_MINUTES 2
52 #define RTC_MINUTES_ALARM 3
53 #define RTC_HOURS 4
54 #define RTC_HOURS_ALARM 5
55 #define RTC_ALARM_DONT_CARE 0xC0
56
57 #define RTC_DAY_OF_WEEK 6
58 #define RTC_DAY_OF_MONTH 7
59 #define RTC_MONTH 8
60 #define RTC_YEAR 9
61
62 #define RTC_REG_A 10
63 #define RTC_REG_B 11
64 #define RTC_REG_C 12
65 #define RTC_REG_D 13
66
67 #define REG_A_UIP 0x80
68
69 #define REG_B_SET 0x80
70 #define REG_B_PIE 0x40
71 #define REG_B_AIE 0x20
72 #define REG_B_UIE 0x10
73 #define REG_B_SQWE 0x08
74 #define REG_B_DM 0x04
75 #define REG_B_24H 0x02
76
77 #define REG_C_UF 0x10
78 #define REG_C_IRQF 0x80
79 #define REG_C_PF 0x40
80 #define REG_C_AF 0x20
81
82 typedef struct RTCState {
83 ISADevice dev;
84 MemoryRegion io;
85 uint8_t cmos_data[128];
86 uint8_t cmos_index;
87 struct tm current_tm;
88 int32_t base_year;
89 qemu_irq irq;
90 qemu_irq sqw_irq;
91 int it_shift;
92 /* periodic timer */
93 QEMUTimer *periodic_timer;
94 int64_t next_periodic_time;
95 /* second update */
96 int64_t next_second_time;
97 uint16_t irq_reinject_on_ack_count;
98 uint32_t irq_coalesced;
99 uint32_t period;
100 QEMUTimer *coalesced_timer;
101 QEMUTimer *second_timer;
102 QEMUTimer *second_timer2;
103 Notifier clock_reset_notifier;
104 LostTickPolicy lost_tick_policy;
105 } RTCState;
106
107 static void rtc_set_time(RTCState *s);
108 static void rtc_copy_date(RTCState *s);
109
110 #ifdef TARGET_I386
111 static void rtc_coalesced_timer_update(RTCState *s)
112 {
113 if (s->irq_coalesced == 0) {
114 qemu_del_timer(s->coalesced_timer);
115 } else {
116 /* divide each RTC interval to 2 - 8 smaller intervals */
117 int c = MIN(s->irq_coalesced, 7) + 1;
118 int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
119 muldiv64(s->period / c, get_ticks_per_sec(), 32768);
120 qemu_mod_timer(s->coalesced_timer, next_clock);
121 }
122 }
123
124 static void rtc_coalesced_timer(void *opaque)
125 {
126 RTCState *s = opaque;
127
128 if (s->irq_coalesced != 0) {
129 apic_reset_irq_delivered();
130 s->cmos_data[RTC_REG_C] |= 0xc0;
131 DPRINTF_C("cmos: injecting from timer\n");
132 qemu_irq_raise(s->irq);
133 if (apic_get_irq_delivered()) {
134 s->irq_coalesced--;
135 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
136 s->irq_coalesced);
137 }
138 }
139
140 rtc_coalesced_timer_update(s);
141 }
142 #endif
143
144 static void rtc_timer_update(RTCState *s, int64_t current_time)
145 {
146 int period_code, period;
147 int64_t cur_clock, next_irq_clock;
148
149 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
150 if (period_code != 0
151 && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
152 || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
153 if (period_code <= 2)
154 period_code += 7;
155 /* period in 32 Khz cycles */
156 period = 1 << (period_code - 1);
157 #ifdef TARGET_I386
158 if (period != s->period) {
159 s->irq_coalesced = (s->irq_coalesced * s->period) / period;
160 DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
161 }
162 s->period = period;
163 #endif
164 /* compute 32 khz clock */
165 cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
166 next_irq_clock = (cur_clock & ~(period - 1)) + period;
167 s->next_periodic_time =
168 muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
169 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
170 } else {
171 #ifdef TARGET_I386
172 s->irq_coalesced = 0;
173 #endif
174 qemu_del_timer(s->periodic_timer);
175 }
176 }
177
178 static void rtc_periodic_timer(void *opaque)
179 {
180 RTCState *s = opaque;
181
182 rtc_timer_update(s, s->next_periodic_time);
183 s->cmos_data[RTC_REG_C] |= REG_C_PF;
184 if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
185 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
186 #ifdef TARGET_I386
187 if (s->lost_tick_policy == LOST_TICK_SLEW) {
188 if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
189 s->irq_reinject_on_ack_count = 0;
190 apic_reset_irq_delivered();
191 qemu_irq_raise(s->irq);
192 if (!apic_get_irq_delivered()) {
193 s->irq_coalesced++;
194 rtc_coalesced_timer_update(s);
195 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
196 s->irq_coalesced);
197 }
198 } else
199 #endif
200 qemu_irq_raise(s->irq);
201 }
202 if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
203 /* Not square wave at all but we don't want 2048Hz interrupts!
204 Must be seen as a pulse. */
205 qemu_irq_raise(s->sqw_irq);
206 }
207 }
208
209 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
210 {
211 RTCState *s = opaque;
212
213 if ((addr & 1) == 0) {
214 s->cmos_index = data & 0x7f;
215 } else {
216 CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
217 s->cmos_index, data);
218 switch(s->cmos_index) {
219 case RTC_SECONDS_ALARM:
220 case RTC_MINUTES_ALARM:
221 case RTC_HOURS_ALARM:
222 s->cmos_data[s->cmos_index] = data;
223 break;
224 case RTC_SECONDS:
225 case RTC_MINUTES:
226 case RTC_HOURS:
227 case RTC_DAY_OF_WEEK:
228 case RTC_DAY_OF_MONTH:
229 case RTC_MONTH:
230 case RTC_YEAR:
231 s->cmos_data[s->cmos_index] = data;
232 /* if in set mode, do not update the time */
233 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
234 rtc_set_time(s);
235 }
236 break;
237 case RTC_REG_A:
238 /* UIP bit is read only */
239 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
240 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
241 rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
242 break;
243 case RTC_REG_B:
244 if (data & REG_B_SET) {
245 /* set mode: reset UIP mode */
246 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
247 data &= ~REG_B_UIE;
248 } else {
249 /* if disabling set mode, update the time */
250 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
251 rtc_set_time(s);
252 }
253 }
254 if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
255 !(data & REG_B_SET)) {
256 /* If the time format has changed and not in set mode,
257 update the registers immediately. */
258 s->cmos_data[RTC_REG_B] = data;
259 rtc_copy_date(s);
260 } else {
261 s->cmos_data[RTC_REG_B] = data;
262 }
263 rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
264 break;
265 case RTC_REG_C:
266 case RTC_REG_D:
267 /* cannot write to them */
268 break;
269 default:
270 s->cmos_data[s->cmos_index] = data;
271 break;
272 }
273 }
274 }
275
276 static inline int rtc_to_bcd(RTCState *s, int a)
277 {
278 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
279 return a;
280 } else {
281 return ((a / 10) << 4) | (a % 10);
282 }
283 }
284
285 static inline int rtc_from_bcd(RTCState *s, int a)
286 {
287 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
288 return a;
289 } else {
290 return ((a >> 4) * 10) + (a & 0x0f);
291 }
292 }
293
294 static void rtc_set_time(RTCState *s)
295 {
296 struct tm *tm = &s->current_tm;
297
298 tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
299 tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
300 tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
301 if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
302 tm->tm_hour %= 12;
303 if (s->cmos_data[RTC_HOURS] & 0x80) {
304 tm->tm_hour += 12;
305 }
306 }
307 tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
308 tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
309 tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
310 tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
311
312 rtc_change_mon_event(tm);
313 }
314
315 static void rtc_copy_date(RTCState *s)
316 {
317 const struct tm *tm = &s->current_tm;
318 int year;
319
320 s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
321 s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
322 if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
323 /* 24 hour format */
324 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
325 } else {
326 /* 12 hour format */
327 int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
328 s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
329 if (tm->tm_hour >= 12)
330 s->cmos_data[RTC_HOURS] |= 0x80;
331 }
332 s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
333 s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
334 s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
335 year = (tm->tm_year - s->base_year) % 100;
336 if (year < 0)
337 year += 100;
338 s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
339 }
340
341 /* month is between 0 and 11. */
342 static int get_days_in_month(int month, int year)
343 {
344 static const int days_tab[12] = {
345 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
346 };
347 int d;
348 if ((unsigned )month >= 12)
349 return 31;
350 d = days_tab[month];
351 if (month == 1) {
352 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
353 d++;
354 }
355 return d;
356 }
357
358 /* update 'tm' to the next second */
359 static void rtc_next_second(struct tm *tm)
360 {
361 int days_in_month;
362
363 tm->tm_sec++;
364 if ((unsigned)tm->tm_sec >= 60) {
365 tm->tm_sec = 0;
366 tm->tm_min++;
367 if ((unsigned)tm->tm_min >= 60) {
368 tm->tm_min = 0;
369 tm->tm_hour++;
370 if ((unsigned)tm->tm_hour >= 24) {
371 tm->tm_hour = 0;
372 /* next day */
373 tm->tm_wday++;
374 if ((unsigned)tm->tm_wday >= 7)
375 tm->tm_wday = 0;
376 days_in_month = get_days_in_month(tm->tm_mon,
377 tm->tm_year + 1900);
378 tm->tm_mday++;
379 if (tm->tm_mday < 1) {
380 tm->tm_mday = 1;
381 } else if (tm->tm_mday > days_in_month) {
382 tm->tm_mday = 1;
383 tm->tm_mon++;
384 if (tm->tm_mon >= 12) {
385 tm->tm_mon = 0;
386 tm->tm_year++;
387 }
388 }
389 }
390 }
391 }
392 }
393
394
395 static void rtc_update_second(void *opaque)
396 {
397 RTCState *s = opaque;
398 int64_t delay;
399
400 /* if the oscillator is not in normal operation, we do not update */
401 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
402 s->next_second_time += get_ticks_per_sec();
403 qemu_mod_timer(s->second_timer, s->next_second_time);
404 } else {
405 rtc_next_second(&s->current_tm);
406
407 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
408 /* update in progress bit */
409 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
410 }
411 /* should be 244 us = 8 / 32768 seconds, but currently the
412 timers do not have the necessary resolution. */
413 delay = (get_ticks_per_sec() * 1) / 100;
414 if (delay < 1)
415 delay = 1;
416 qemu_mod_timer(s->second_timer2,
417 s->next_second_time + delay);
418 }
419 }
420
421 static void rtc_update_second2(void *opaque)
422 {
423 RTCState *s = opaque;
424
425 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
426 rtc_copy_date(s);
427 }
428
429 /* check alarm */
430 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
431 rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
432 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
433 rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
434 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
435 rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
436
437 s->cmos_data[RTC_REG_C] |= REG_C_AF;
438 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
439 qemu_irq_raise(s->irq);
440 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
441 }
442 }
443
444 /* update ended interrupt */
445 s->cmos_data[RTC_REG_C] |= REG_C_UF;
446 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
447 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
448 qemu_irq_raise(s->irq);
449 }
450
451 /* clear update in progress bit */
452 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
453
454 s->next_second_time += get_ticks_per_sec();
455 qemu_mod_timer(s->second_timer, s->next_second_time);
456 }
457
458 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
459 {
460 RTCState *s = opaque;
461 int ret;
462 if ((addr & 1) == 0) {
463 return 0xff;
464 } else {
465 switch(s->cmos_index) {
466 case RTC_SECONDS:
467 case RTC_MINUTES:
468 case RTC_HOURS:
469 case RTC_DAY_OF_WEEK:
470 case RTC_DAY_OF_MONTH:
471 case RTC_MONTH:
472 case RTC_YEAR:
473 ret = s->cmos_data[s->cmos_index];
474 break;
475 case RTC_REG_A:
476 ret = s->cmos_data[s->cmos_index];
477 break;
478 case RTC_REG_C:
479 ret = s->cmos_data[s->cmos_index];
480 qemu_irq_lower(s->irq);
481 s->cmos_data[RTC_REG_C] = 0x00;
482 #ifdef TARGET_I386
483 if(s->irq_coalesced &&
484 (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
485 s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
486 s->irq_reinject_on_ack_count++;
487 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
488 apic_reset_irq_delivered();
489 DPRINTF_C("cmos: injecting on ack\n");
490 qemu_irq_raise(s->irq);
491 if (apic_get_irq_delivered()) {
492 s->irq_coalesced--;
493 DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
494 s->irq_coalesced);
495 }
496 }
497 #endif
498 break;
499 default:
500 ret = s->cmos_data[s->cmos_index];
501 break;
502 }
503 CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
504 s->cmos_index, ret);
505 return ret;
506 }
507 }
508
509 void rtc_set_memory(ISADevice *dev, int addr, int val)
510 {
511 RTCState *s = DO_UPCAST(RTCState, dev, dev);
512 if (addr >= 0 && addr <= 127)
513 s->cmos_data[addr] = val;
514 }
515
516 void rtc_set_date(ISADevice *dev, const struct tm *tm)
517 {
518 RTCState *s = DO_UPCAST(RTCState, dev, dev);
519 s->current_tm = *tm;
520 rtc_copy_date(s);
521 }
522
523 /* PC cmos mappings */
524 #define REG_IBM_CENTURY_BYTE 0x32
525 #define REG_IBM_PS2_CENTURY_BYTE 0x37
526
527 static void rtc_set_date_from_host(ISADevice *dev)
528 {
529 RTCState *s = DO_UPCAST(RTCState, dev, dev);
530 struct tm tm;
531 int val;
532
533 /* set the CMOS date */
534 qemu_get_timedate(&tm, 0);
535 rtc_set_date(dev, &tm);
536
537 val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
538 rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
539 rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
540 }
541
542 static int rtc_post_load(void *opaque, int version_id)
543 {
544 #ifdef TARGET_I386
545 RTCState *s = opaque;
546
547 if (version_id >= 2) {
548 if (s->lost_tick_policy == LOST_TICK_SLEW) {
549 rtc_coalesced_timer_update(s);
550 }
551 }
552 #endif
553 return 0;
554 }
555
556 static const VMStateDescription vmstate_rtc = {
557 .name = "mc146818rtc",
558 .version_id = 2,
559 .minimum_version_id = 1,
560 .minimum_version_id_old = 1,
561 .post_load = rtc_post_load,
562 .fields = (VMStateField []) {
563 VMSTATE_BUFFER(cmos_data, RTCState),
564 VMSTATE_UINT8(cmos_index, RTCState),
565 VMSTATE_INT32(current_tm.tm_sec, RTCState),
566 VMSTATE_INT32(current_tm.tm_min, RTCState),
567 VMSTATE_INT32(current_tm.tm_hour, RTCState),
568 VMSTATE_INT32(current_tm.tm_wday, RTCState),
569 VMSTATE_INT32(current_tm.tm_mday, RTCState),
570 VMSTATE_INT32(current_tm.tm_mon, RTCState),
571 VMSTATE_INT32(current_tm.tm_year, RTCState),
572 VMSTATE_TIMER(periodic_timer, RTCState),
573 VMSTATE_INT64(next_periodic_time, RTCState),
574 VMSTATE_INT64(next_second_time, RTCState),
575 VMSTATE_TIMER(second_timer, RTCState),
576 VMSTATE_TIMER(second_timer2, RTCState),
577 VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
578 VMSTATE_UINT32_V(period, RTCState, 2),
579 VMSTATE_END_OF_LIST()
580 }
581 };
582
583 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
584 {
585 RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
586 int64_t now = *(int64_t *)data;
587
588 rtc_set_date_from_host(&s->dev);
589 s->next_second_time = now + (get_ticks_per_sec() * 99) / 100;
590 qemu_mod_timer(s->second_timer2, s->next_second_time);
591 rtc_timer_update(s, now);
592 #ifdef TARGET_I386
593 if (s->lost_tick_policy == LOST_TICK_SLEW) {
594 rtc_coalesced_timer_update(s);
595 }
596 #endif
597 }
598
599 static void rtc_reset(void *opaque)
600 {
601 RTCState *s = opaque;
602
603 s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
604 s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
605
606 qemu_irq_lower(s->irq);
607
608 #ifdef TARGET_I386
609 if (s->lost_tick_policy == LOST_TICK_SLEW) {
610 s->irq_coalesced = 0;
611 }
612 #endif
613 }
614
615 static const MemoryRegionPortio cmos_portio[] = {
616 {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write },
617 PORTIO_END_OF_LIST(),
618 };
619
620 static const MemoryRegionOps cmos_ops = {
621 .old_portio = cmos_portio
622 };
623
624 // FIXME add int32 visitor
625 static void visit_type_int32(Visitor *v, int *value, const char *name, Error **errp)
626 {
627 int64_t val = *value;
628 visit_type_int(v, &val, name, errp);
629 }
630
631 static void rtc_get_date(DeviceState *dev, Visitor *v, void *opaque,
632 const char *name, Error **errp)
633 {
634 ISADevice *isa = ISA_DEVICE(dev);
635 RTCState *s = DO_UPCAST(RTCState, dev, isa);
636
637 visit_start_struct(v, NULL, "struct tm", name, 0, errp);
638 visit_type_int32(v, &s->current_tm.tm_year, "tm_year", errp);
639 visit_type_int32(v, &s->current_tm.tm_mon, "tm_mon", errp);
640 visit_type_int32(v, &s->current_tm.tm_mday, "tm_mday", errp);
641 visit_type_int32(v, &s->current_tm.tm_hour, "tm_hour", errp);
642 visit_type_int32(v, &s->current_tm.tm_min, "tm_min", errp);
643 visit_type_int32(v, &s->current_tm.tm_sec, "tm_sec", errp);
644 visit_end_struct(v, errp);
645 }
646
647 static int rtc_initfn(ISADevice *dev)
648 {
649 RTCState *s = DO_UPCAST(RTCState, dev, dev);
650 int base = 0x70;
651
652 s->cmos_data[RTC_REG_A] = 0x26;
653 s->cmos_data[RTC_REG_B] = 0x02;
654 s->cmos_data[RTC_REG_C] = 0x00;
655 s->cmos_data[RTC_REG_D] = 0x80;
656
657 rtc_set_date_from_host(dev);
658
659 #ifdef TARGET_I386
660 switch (s->lost_tick_policy) {
661 case LOST_TICK_SLEW:
662 s->coalesced_timer =
663 qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
664 break;
665 case LOST_TICK_DISCARD:
666 break;
667 default:
668 return -EINVAL;
669 }
670 #endif
671
672 s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
673 s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
674 s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
675
676 s->clock_reset_notifier.notify = rtc_notify_clock_reset;
677 qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
678
679 s->next_second_time =
680 qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
681 qemu_mod_timer(s->second_timer2, s->next_second_time);
682
683 memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
684 isa_register_ioport(dev, &s->io, base);
685
686 qdev_set_legacy_instance_id(&dev->qdev, base, 2);
687 qemu_register_reset(rtc_reset, s);
688
689 qdev_property_add(&s->dev.qdev, "date", "struct tm",
690 rtc_get_date, NULL, NULL, s, NULL);
691
692 return 0;
693 }
694
695 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
696 {
697 ISADevice *dev;
698 RTCState *s;
699
700 dev = isa_create(bus, "mc146818rtc");
701 s = DO_UPCAST(RTCState, dev, dev);
702 qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
703 qdev_init_nofail(&dev->qdev);
704 if (intercept_irq) {
705 s->irq = intercept_irq;
706 } else {
707 isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
708 }
709 return dev;
710 }
711
712 static void rtc_class_initfn(ObjectClass *klass, void *data)
713 {
714 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
715 ic->init = rtc_initfn;
716 }
717
718 static DeviceInfo mc146818rtc_info = {
719 .name = "mc146818rtc",
720 .size = sizeof(RTCState),
721 .no_user = 1,
722 .vmsd = &vmstate_rtc,
723 .class_init = rtc_class_initfn,
724 .props = (Property[]) {
725 DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
726 DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
727 lost_tick_policy, LOST_TICK_DISCARD),
728 DEFINE_PROP_END_OF_LIST(),
729 }
730 };
731
732 static void mc146818rtc_register(void)
733 {
734 isa_qdev_register(&mc146818rtc_info);
735 }
736 device_init(mc146818rtc_register)