tests/acpi: add microvm test
[qemu.git] / hw / microblaze / xlnx-zynqmp-pmu.c
1 /*
2 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
3 *
4 * Copyright (C) 2017 Xilinx Inc
5 * Written by Alistair Francis <alistair.francis@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "exec/address-spaces.h"
21 #include "hw/boards.h"
22 #include "cpu.h"
23 #include "boot.h"
24
25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
27 #include "qom/object.h"
28
29 /* Define the PMU device */
30
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
32 typedef struct XlnxZynqMPPMUSoCState XlnxZynqMPPMUSoCState;
33 DECLARE_INSTANCE_CHECKER(XlnxZynqMPPMUSoCState, XLNX_ZYNQMP_PMU_SOC,
34 TYPE_XLNX_ZYNQMP_PMU_SOC)
35
36 #define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
37 #define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
38 #define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
39
40 #define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
41
42 #define XLNX_ZYNQMP_PMU_NUM_IPIS 4
43
44 static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
45 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
46 };
47 static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
48 19, 20, 21, 22,
49 };
50
51 struct XlnxZynqMPPMUSoCState {
52 /*< private >*/
53 DeviceState parent_obj;
54
55 /*< public >*/
56 MicroBlazeCPU cpu;
57 XlnxPMUIOIntc intc;
58 XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
59 };
60
61
62 static void xlnx_zynqmp_pmu_soc_init(Object *obj)
63 {
64 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
65
66 object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU);
67
68 object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC);
69
70 /* Create the IPI device */
71 for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
72 char *name = g_strdup_printf("ipi%d", i);
73 object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI);
74 g_free(name);
75 }
76 }
77
78 static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
79 {
80 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
81
82 object_property_set_uint(OBJECT(&s->cpu), "base-vectors",
83 XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort);
84 object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true,
85 &error_abort);
86 object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort);
87 object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort);
88 object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true,
89 &error_abort);
90 object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true,
91 &error_abort);
92 object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true,
93 &error_abort);
94 object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort);
95 object_property_set_bool(OBJECT(&s->cpu), "endianness", true,
96 &error_abort);
97 object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b",
98 &error_abort);
99 object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort);
100 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
101 return;
102 }
103
104 object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10,
105 &error_abort);
106 object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0,
107 &error_abort);
108 object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff,
109 &error_abort);
110 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
111 return;
112 }
113 sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
114 sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
115 qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
116
117 /* Connect the IPI device */
118 for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
119 sysbus_realize(SYS_BUS_DEVICE(&s->ipi[i]), &error_abort);
120 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
121 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
122 qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
123 }
124 }
125
126 static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
127 {
128 DeviceClass *dc = DEVICE_CLASS(oc);
129
130 dc->realize = xlnx_zynqmp_pmu_soc_realize;
131 }
132
133 static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
134 .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
135 .parent = TYPE_DEVICE,
136 .instance_size = sizeof(XlnxZynqMPPMUSoCState),
137 .instance_init = xlnx_zynqmp_pmu_soc_init,
138 .class_init = xlnx_zynqmp_pmu_soc_class_init,
139 };
140
141 static void xlnx_zynqmp_pmu_soc_register_types(void)
142 {
143 type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
144 }
145
146 type_init(xlnx_zynqmp_pmu_soc_register_types)
147
148 /* Define the PMU Machine */
149
150 static void xlnx_zynqmp_pmu_init(MachineState *machine)
151 {
152 XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
153 MemoryRegion *address_space_mem = get_system_memory();
154 MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
155 MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
156
157 /* Create the ROM */
158 memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
159 XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
160 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
161 pmu_rom);
162
163 /* Create the RAM */
164 memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
165 machine->ram_size, &error_fatal);
166 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
167 pmu_ram);
168
169 /* Create the PMU device */
170 object_initialize_child(OBJECT(machine), "pmu", pmu,
171 TYPE_XLNX_ZYNQMP_PMU_SOC);
172 qdev_realize(DEVICE(pmu), NULL, &error_fatal);
173
174 /* Load the kernel */
175 microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
176 machine->ram_size,
177 machine->initrd_filename,
178 machine->dtb,
179 NULL);
180 }
181
182 static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
183 {
184 mc->desc = "Xilinx ZynqMP PMU machine";
185 mc->init = xlnx_zynqmp_pmu_init;
186 }
187
188 DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
189