linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / milkymist-memcard.c
1 /*
2 * QEMU model of the Milkymist SD Card Controller.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://www.milkymist.org/socdoc/memcard.pdf
22 */
23
24 #include "hw.h"
25 #include "sysbus.h"
26 #include "sysemu.h"
27 #include "trace.h"
28 #include "qemu-error.h"
29 #include "blockdev.h"
30 #include "sd.h"
31
32 enum {
33 ENABLE_CMD_TX = (1<<0),
34 ENABLE_CMD_RX = (1<<1),
35 ENABLE_DAT_TX = (1<<2),
36 ENABLE_DAT_RX = (1<<3),
37 };
38
39 enum {
40 PENDING_CMD_TX = (1<<0),
41 PENDING_CMD_RX = (1<<1),
42 PENDING_DAT_TX = (1<<2),
43 PENDING_DAT_RX = (1<<3),
44 };
45
46 enum {
47 START_CMD_TX = (1<<0),
48 START_DAT_RX = (1<<1),
49 };
50
51 enum {
52 R_CLK2XDIV = 0,
53 R_ENABLE,
54 R_PENDING,
55 R_START,
56 R_CMD,
57 R_DAT,
58 R_MAX
59 };
60
61 struct MilkymistMemcardState {
62 SysBusDevice busdev;
63 MemoryRegion regs_region;
64 SDState *card;
65
66 int command_write_ptr;
67 int response_read_ptr;
68 int response_len;
69 int ignore_next_cmd;
70 int enabled;
71 uint8_t command[6];
72 uint8_t response[17];
73 uint32_t regs[R_MAX];
74 };
75 typedef struct MilkymistMemcardState MilkymistMemcardState;
76
77 static void update_pending_bits(MilkymistMemcardState *s)
78 {
79 /* transmits are instantaneous, thus tx pending bits are never set */
80 s->regs[R_PENDING] = 0;
81 /* if rx is enabled the corresponding pending bits are always set */
82 if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
83 s->regs[R_PENDING] |= PENDING_CMD_RX;
84 }
85 if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
86 s->regs[R_PENDING] |= PENDING_DAT_RX;
87 }
88 }
89
90 static void memcard_sd_command(MilkymistMemcardState *s)
91 {
92 SDRequest req;
93
94 req.cmd = s->command[0] & 0x3f;
95 req.arg = (s->command[1] << 24) | (s->command[2] << 16)
96 | (s->command[3] << 8) | s->command[4];
97 req.crc = s->command[5];
98
99 s->response[0] = req.cmd;
100 s->response_len = sd_do_command(s->card, &req, s->response+1);
101 s->response_read_ptr = 0;
102
103 if (s->response_len == 16) {
104 /* R2 response */
105 s->response[0] = 0x3f;
106 s->response_len += 1;
107 } else if (s->response_len == 4) {
108 /* no crc calculation, insert dummy byte */
109 s->response[5] = 0;
110 s->response_len += 2;
111 }
112
113 if (req.cmd == 0) {
114 /* next write is a dummy byte to clock the initialization of the sd
115 * card */
116 s->ignore_next_cmd = 1;
117 }
118 }
119
120 static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
121 unsigned size)
122 {
123 MilkymistMemcardState *s = opaque;
124 uint32_t r = 0;
125
126 addr >>= 2;
127 switch (addr) {
128 case R_CMD:
129 if (!s->enabled) {
130 r = 0xff;
131 } else {
132 r = s->response[s->response_read_ptr++];
133 if (s->response_read_ptr > s->response_len) {
134 error_report("milkymist_memcard: "
135 "read more cmd bytes than available. Clipping.");
136 s->response_read_ptr = 0;
137 }
138 }
139 break;
140 case R_DAT:
141 if (!s->enabled) {
142 r = 0xffffffff;
143 } else {
144 r = 0;
145 r |= sd_read_data(s->card) << 24;
146 r |= sd_read_data(s->card) << 16;
147 r |= sd_read_data(s->card) << 8;
148 r |= sd_read_data(s->card);
149 }
150 break;
151 case R_CLK2XDIV:
152 case R_ENABLE:
153 case R_PENDING:
154 case R_START:
155 r = s->regs[addr];
156 break;
157
158 default:
159 error_report("milkymist_memcard: read access to unknown register 0x"
160 TARGET_FMT_plx, addr << 2);
161 break;
162 }
163
164 trace_milkymist_memcard_memory_read(addr << 2, r);
165
166 return r;
167 }
168
169 static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
170 unsigned size)
171 {
172 MilkymistMemcardState *s = opaque;
173
174 trace_milkymist_memcard_memory_write(addr, value);
175
176 addr >>= 2;
177 switch (addr) {
178 case R_PENDING:
179 /* clear rx pending bits */
180 s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
181 update_pending_bits(s);
182 break;
183 case R_CMD:
184 if (!s->enabled) {
185 break;
186 }
187 if (s->ignore_next_cmd) {
188 s->ignore_next_cmd = 0;
189 break;
190 }
191 s->command[s->command_write_ptr] = value & 0xff;
192 s->command_write_ptr = (s->command_write_ptr + 1) % 6;
193 if (s->command_write_ptr == 0) {
194 memcard_sd_command(s);
195 }
196 break;
197 case R_DAT:
198 if (!s->enabled) {
199 break;
200 }
201 sd_write_data(s->card, (value >> 24) & 0xff);
202 sd_write_data(s->card, (value >> 16) & 0xff);
203 sd_write_data(s->card, (value >> 8) & 0xff);
204 sd_write_data(s->card, value & 0xff);
205 break;
206 case R_ENABLE:
207 s->regs[addr] = value;
208 update_pending_bits(s);
209 break;
210 case R_CLK2XDIV:
211 case R_START:
212 s->regs[addr] = value;
213 break;
214
215 default:
216 error_report("milkymist_memcard: write access to unknown register 0x"
217 TARGET_FMT_plx, addr << 2);
218 break;
219 }
220 }
221
222 static const MemoryRegionOps memcard_mmio_ops = {
223 .read = memcard_read,
224 .write = memcard_write,
225 .valid = {
226 .min_access_size = 4,
227 .max_access_size = 4,
228 },
229 .endianness = DEVICE_NATIVE_ENDIAN,
230 };
231
232 static void milkymist_memcard_reset(DeviceState *d)
233 {
234 MilkymistMemcardState *s =
235 container_of(d, MilkymistMemcardState, busdev.qdev);
236 int i;
237
238 s->command_write_ptr = 0;
239 s->response_read_ptr = 0;
240 s->response_len = 0;
241
242 for (i = 0; i < R_MAX; i++) {
243 s->regs[i] = 0;
244 }
245 }
246
247 static int milkymist_memcard_init(SysBusDevice *dev)
248 {
249 MilkymistMemcardState *s = FROM_SYSBUS(typeof(*s), dev);
250 DriveInfo *dinfo;
251
252 dinfo = drive_get_next(IF_SD);
253 s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0);
254 s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
255
256 memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s,
257 "milkymist-memcard", R_MAX * 4);
258 sysbus_init_mmio(dev, &s->regs_region);
259
260 return 0;
261 }
262
263 static const VMStateDescription vmstate_milkymist_memcard = {
264 .name = "milkymist-memcard",
265 .version_id = 1,
266 .minimum_version_id = 1,
267 .minimum_version_id_old = 1,
268 .fields = (VMStateField[]) {
269 VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
270 VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
271 VMSTATE_INT32(response_len, MilkymistMemcardState),
272 VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
273 VMSTATE_INT32(enabled, MilkymistMemcardState),
274 VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
275 VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
276 VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
277 VMSTATE_END_OF_LIST()
278 }
279 };
280
281 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
282 {
283 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
284
285 k->init = milkymist_memcard_init;
286 }
287
288 static DeviceInfo milkymist_memcard_info = {
289 .name = "milkymist-memcard",
290 .size = sizeof(MilkymistMemcardState),
291 .vmsd = &vmstate_milkymist_memcard,
292 .reset = milkymist_memcard_reset,
293 .class_init = milkymist_memcard_class_init,
294 };
295
296 static void milkymist_memcard_register(void)
297 {
298 sysbus_register_withprop(&milkymist_memcard_info);
299 }
300
301 device_init(milkymist_memcard_register)