Add access control support to qemu bridge helper
[qemu.git] / hw / milkymist-uart.c
1 /*
2 * QEMU model of the Milkymist UART block.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://www.milkymist.org/socdoc/uart.pdf
22 */
23
24 #include "hw.h"
25 #include "sysbus.h"
26 #include "trace.h"
27 #include "qemu-char.h"
28 #include "qemu-error.h"
29
30 enum {
31 R_RXTX = 0,
32 R_DIV,
33 R_STAT,
34 R_CTRL,
35 R_DBG,
36 R_MAX
37 };
38
39 enum {
40 STAT_THRE = (1<<0),
41 STAT_RX_EVT = (1<<1),
42 STAT_TX_EVT = (1<<2),
43 };
44
45 enum {
46 CTRL_RX_IRQ_EN = (1<<0),
47 CTRL_TX_IRQ_EN = (1<<1),
48 CTRL_THRU_EN = (1<<2),
49 };
50
51 enum {
52 DBG_BREAK_EN = (1<<0),
53 };
54
55 struct MilkymistUartState {
56 SysBusDevice busdev;
57 MemoryRegion regs_region;
58 CharDriverState *chr;
59 qemu_irq irq;
60
61 uint32_t regs[R_MAX];
62 };
63 typedef struct MilkymistUartState MilkymistUartState;
64
65 static void uart_update_irq(MilkymistUartState *s)
66 {
67 int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
68 int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
69 int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
70 int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
71
72 if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
73 trace_milkymist_uart_raise_irq();
74 qemu_irq_raise(s->irq);
75 } else {
76 trace_milkymist_uart_lower_irq();
77 qemu_irq_lower(s->irq);
78 }
79 }
80
81 static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
82 unsigned size)
83 {
84 MilkymistUartState *s = opaque;
85 uint32_t r = 0;
86
87 addr >>= 2;
88 switch (addr) {
89 case R_RXTX:
90 r = s->regs[addr];
91 break;
92 case R_DIV:
93 case R_STAT:
94 case R_CTRL:
95 case R_DBG:
96 r = s->regs[addr];
97 break;
98
99 default:
100 error_report("milkymist_uart: read access to unknown register 0x"
101 TARGET_FMT_plx, addr << 2);
102 break;
103 }
104
105 trace_milkymist_uart_memory_read(addr << 2, r);
106
107 return r;
108 }
109
110 static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
111 unsigned size)
112 {
113 MilkymistUartState *s = opaque;
114 unsigned char ch = value;
115
116 trace_milkymist_uart_memory_write(addr, value);
117
118 addr >>= 2;
119 switch (addr) {
120 case R_RXTX:
121 if (s->chr) {
122 qemu_chr_fe_write(s->chr, &ch, 1);
123 }
124 s->regs[R_STAT] |= STAT_TX_EVT;
125 break;
126 case R_DIV:
127 case R_CTRL:
128 case R_DBG:
129 s->regs[addr] = value;
130 break;
131
132 case R_STAT:
133 /* write one to clear bits */
134 s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
135 break;
136
137 default:
138 error_report("milkymist_uart: write access to unknown register 0x"
139 TARGET_FMT_plx, addr << 2);
140 break;
141 }
142
143 uart_update_irq(s);
144 }
145
146 static const MemoryRegionOps uart_mmio_ops = {
147 .read = uart_read,
148 .write = uart_write,
149 .valid = {
150 .min_access_size = 4,
151 .max_access_size = 4,
152 },
153 .endianness = DEVICE_NATIVE_ENDIAN,
154 };
155
156 static void uart_rx(void *opaque, const uint8_t *buf, int size)
157 {
158 MilkymistUartState *s = opaque;
159
160 assert(!(s->regs[R_STAT] & STAT_RX_EVT));
161
162 s->regs[R_STAT] |= STAT_RX_EVT;
163 s->regs[R_RXTX] = *buf;
164
165 uart_update_irq(s);
166 }
167
168 static int uart_can_rx(void *opaque)
169 {
170 MilkymistUartState *s = opaque;
171
172 return !(s->regs[R_STAT] & STAT_RX_EVT);
173 }
174
175 static void uart_event(void *opaque, int event)
176 {
177 }
178
179 static void milkymist_uart_reset(DeviceState *d)
180 {
181 MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev);
182 int i;
183
184 for (i = 0; i < R_MAX; i++) {
185 s->regs[i] = 0;
186 }
187
188 /* THRE is always set */
189 s->regs[R_STAT] = STAT_THRE;
190 }
191
192 static int milkymist_uart_init(SysBusDevice *dev)
193 {
194 MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
195
196 sysbus_init_irq(dev, &s->irq);
197
198 memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
199 "milkymist-uart", R_MAX * 4);
200 sysbus_init_mmio(dev, &s->regs_region);
201
202 s->chr = qdev_init_chardev(&dev->qdev);
203 if (s->chr) {
204 qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
205 }
206
207 return 0;
208 }
209
210 static const VMStateDescription vmstate_milkymist_uart = {
211 .name = "milkymist-uart",
212 .version_id = 1,
213 .minimum_version_id = 1,
214 .minimum_version_id_old = 1,
215 .fields = (VMStateField[]) {
216 VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
217 VMSTATE_END_OF_LIST()
218 }
219 };
220
221 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
222 {
223 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
224
225 k->init = milkymist_uart_init;
226 }
227
228 static DeviceInfo milkymist_uart_info = {
229 .name = "milkymist-uart",
230 .size = sizeof(MilkymistUartState),
231 .vmsd = &vmstate_milkymist_uart,
232 .reset = milkymist_uart_reset,
233 .class_init = milkymist_uart_class_init,
234 };
235
236 static void milkymist_uart_register(void)
237 {
238 sysbus_register_withprop(&milkymist_uart_info);
239 }
240
241 device_init(milkymist_uart_register)