configure: fix --meson=/path/to/meson
[qemu.git] / hw / mips / cps.c
1 /*
2 * Coherent Processing System emulation.
3 *
4 * Copyright (c) 2016 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/module.h"
23 #include "hw/mips/cps.h"
24 #include "hw/mips/mips.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/mips/cpudevs.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/reset.h"
29
30 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
31 {
32 assert(pin_number < s->num_irq);
33 return s->gic.irq_state[pin_number].irq;
34 }
35
36 static void mips_cps_init(Object *obj)
37 {
38 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
39 MIPSCPSState *s = MIPS_CPS(obj);
40
41 /*
42 * Cover entire address space as there do not seem to be any
43 * constraints for the base address of CPC and GIC.
44 */
45 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
46 sysbus_init_mmio(sbd, &s->container);
47 }
48
49 static void main_cpu_reset(void *opaque)
50 {
51 MIPSCPU *cpu = opaque;
52 CPUState *cs = CPU(cpu);
53
54 cpu_reset(cs);
55 }
56
57 static bool cpu_mips_itu_supported(CPUMIPSState *env)
58 {
59 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
60 (env->CP0_Config3 & (1 << CP0C3_MT));
61
62 return is_mt && !kvm_enabled();
63 }
64
65 static void mips_cps_realize(DeviceState *dev, Error **errp)
66 {
67 MIPSCPSState *s = MIPS_CPS(dev);
68 CPUMIPSState *env;
69 MIPSCPU *cpu;
70 int i;
71 target_ulong gcr_base;
72 bool itu_present = false;
73 bool saar_present = false;
74
75 for (i = 0; i < s->num_vp; i++) {
76 cpu = MIPS_CPU(object_new(s->cpu_type));
77
78 /* All VPs are halted on reset. Leave powering up to CPC. */
79 if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
80 errp)) {
81 return;
82 }
83
84 if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
85 return;
86 }
87
88 /* Init internal devices */
89 cpu_mips_irq_init_cpu(cpu);
90 cpu_mips_clock_init(cpu);
91
92 env = &cpu->env;
93 if (cpu_mips_itu_supported(env)) {
94 itu_present = true;
95 /* Attach ITC Tag to the VP */
96 env->itc_tag = mips_itu_get_tag_region(&s->itu);
97 env->itu = &s->itu;
98 }
99 qemu_register_reset(main_cpu_reset, cpu);
100 }
101
102 cpu = MIPS_CPU(first_cpu);
103 env = &cpu->env;
104 saar_present = (bool)env->saarp;
105
106 /* Inter-Thread Communication Unit */
107 if (itu_present) {
108 object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
109 object_property_set_int(OBJECT(&s->itu), "num-fifo", 16,
110 &error_abort);
111 object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16,
112 &error_abort);
113 object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present,
114 &error_abort);
115 if (saar_present) {
116 s->itu.saar = &env->CP0_SAAR;
117 }
118 if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
119 return;
120 }
121
122 memory_region_add_subregion(&s->container, 0,
123 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
124 }
125
126 /* Cluster Power Controller */
127 object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
128 object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp,
129 &error_abort);
130 object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
131 &error_abort);
132 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
133 return;
134 }
135
136 memory_region_add_subregion(&s->container, 0,
137 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
138
139 /* Global Interrupt Controller */
140 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
141 object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp,
142 &error_abort);
143 object_property_set_int(OBJECT(&s->gic), "num-irq", 128,
144 &error_abort);
145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
146 return;
147 }
148
149 memory_region_add_subregion(&s->container, 0,
150 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
151
152 /* Global Configuration Registers */
153 gcr_base = env->CP0_CMGCRBase << 4;
154
155 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
156 object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
157 &error_abort);
158 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
159 &error_abort);
160 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
161 &error_abort);
162 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
163 &error_abort);
164 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
165 &error_abort);
166 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
167 return;
168 }
169
170 memory_region_add_subregion(&s->container, gcr_base,
171 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
172 }
173
174 static Property mips_cps_properties[] = {
175 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
176 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
177 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
178 DEFINE_PROP_END_OF_LIST()
179 };
180
181 static void mips_cps_class_init(ObjectClass *klass, void *data)
182 {
183 DeviceClass *dc = DEVICE_CLASS(klass);
184
185 dc->realize = mips_cps_realize;
186 device_class_set_props(dc, mips_cps_properties);
187 }
188
189 static const TypeInfo mips_cps_info = {
190 .name = TYPE_MIPS_CPS,
191 .parent = TYPE_SYS_BUS_DEVICE,
192 .instance_size = sizeof(MIPSCPSState),
193 .instance_init = mips_cps_init,
194 .class_init = mips_cps_class_init,
195 };
196
197 static void mips_cps_register_types(void)
198 {
199 type_register_static(&mips_cps_info);
200 }
201
202 type_init(mips_cps_register_types)