pcie_aer: support configurable AER capa version
[qemu.git] / hw / mips / cputimer.c
1 /*
2 * QEMU MIPS timer support
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23 #include "qemu/osdep.h"
24 #include "hw/hw.h"
25 #include "hw/mips/cpudevs.h"
26 #include "qemu/timer.h"
27 #include "sysemu/kvm.h"
28
29 #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
30
31 /* XXX: do not use a global */
32 uint32_t cpu_mips_get_random (CPUMIPSState *env)
33 {
34 static uint32_t seed = 1;
35 static uint32_t prev_idx = 0;
36 uint32_t idx;
37 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
38
39 if (nb_rand_tlb == 1) {
40 return env->tlb->nb_tlb - 1;
41 }
42
43 /* Don't return same value twice, so get another value */
44 do {
45 /* Use a simple algorithm of Linear Congruential Generator
46 * from ISO/IEC 9899 standard. */
47 seed = 1103515245 * seed + 12345;
48 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
49 } while (idx == prev_idx);
50 prev_idx = idx;
51 return idx;
52 }
53
54 /* MIPS R4K timer */
55 static void cpu_mips_timer_update(CPUMIPSState *env)
56 {
57 uint64_t now, next;
58 uint32_t wait;
59
60 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
61 wait = env->CP0_Compare - env->CP0_Count - (uint32_t)(now / TIMER_PERIOD);
62 next = now + (uint64_t)wait * TIMER_PERIOD;
63 timer_mod(env->timer, next);
64 }
65
66 /* Expire the timer. */
67 static void cpu_mips_timer_expire(CPUMIPSState *env)
68 {
69 cpu_mips_timer_update(env);
70 if (env->insn_flags & ISA_MIPS32R2) {
71 env->CP0_Cause |= 1 << CP0Ca_TI;
72 }
73 qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
74 }
75
76 uint32_t cpu_mips_get_count (CPUMIPSState *env)
77 {
78 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
79 return env->CP0_Count;
80 } else {
81 uint64_t now;
82
83 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
84 if (timer_pending(env->timer)
85 && timer_expired(env->timer, now)) {
86 /* The timer has already expired. */
87 cpu_mips_timer_expire(env);
88 }
89
90 return env->CP0_Count + (uint32_t)(now / TIMER_PERIOD);
91 }
92 }
93
94 void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
95 {
96 /*
97 * This gets called from cpu_state_reset(), potentially before timer init.
98 * So env->timer may be NULL, which is also the case with KVM enabled so
99 * treat timer as disabled in that case.
100 */
101 if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
102 env->CP0_Count = count;
103 else {
104 /* Store new count register */
105 env->CP0_Count = count -
106 (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
107 /* Update timer timer */
108 cpu_mips_timer_update(env);
109 }
110 }
111
112 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
113 {
114 env->CP0_Compare = value;
115 if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
116 cpu_mips_timer_update(env);
117 if (env->insn_flags & ISA_MIPS32R2)
118 env->CP0_Cause &= ~(1 << CP0Ca_TI);
119 qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
120 }
121
122 void cpu_mips_start_count(CPUMIPSState *env)
123 {
124 cpu_mips_store_count(env, env->CP0_Count);
125 }
126
127 void cpu_mips_stop_count(CPUMIPSState *env)
128 {
129 /* Store the current value */
130 env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
131 TIMER_PERIOD);
132 }
133
134 static void mips_timer_cb (void *opaque)
135 {
136 CPUMIPSState *env;
137
138 env = opaque;
139 #if 0
140 qemu_log("%s\n", __func__);
141 #endif
142
143 if (env->CP0_Cause & (1 << CP0Ca_DC))
144 return;
145
146 /* ??? This callback should occur when the counter is exactly equal to
147 the comparator value. Offset the count by one to avoid immediately
148 retriggering the callback before any virtual time has passed. */
149 env->CP0_Count++;
150 cpu_mips_timer_expire(env);
151 env->CP0_Count--;
152 }
153
154 void cpu_mips_clock_init (MIPSCPU *cpu)
155 {
156 CPUMIPSState *env = &cpu->env;
157
158 /*
159 * If we're in KVM mode, don't create the periodic timer, that is handled in
160 * kernel.
161 */
162 if (!kvm_enabled()) {
163 env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
164 }
165 }