pcie_aer: support configurable AER capa version
[qemu.git] / hw / mips / mips_mipssim.c
1 /*
2 * QEMU/mipssim emulation
3 *
4 * Emulates a very simple machine model similar to the one used by the
5 * proprietary MIPS emulator.
6 *
7 * Copyright (c) 2007 Thiemo Seufer
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qemu-common.h"
30 #include "cpu.h"
31 #include "hw/hw.h"
32 #include "hw/mips/mips.h"
33 #include "hw/mips/cpudevs.h"
34 #include "hw/char/serial.h"
35 #include "hw/isa/isa.h"
36 #include "net/net.h"
37 #include "sysemu/sysemu.h"
38 #include "hw/boards.h"
39 #include "hw/mips/bios.h"
40 #include "hw/loader.h"
41 #include "elf.h"
42 #include "hw/sysbus.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/error-report.h"
45 #include "sysemu/qtest.h"
46
47 static struct _loaderparams {
48 int ram_size;
49 const char *kernel_filename;
50 const char *kernel_cmdline;
51 const char *initrd_filename;
52 } loaderparams;
53
54 typedef struct ResetData {
55 MIPSCPU *cpu;
56 uint64_t vector;
57 } ResetData;
58
59 static int64_t load_kernel(void)
60 {
61 int64_t entry, kernel_high;
62 long kernel_size;
63 long initrd_size;
64 ram_addr_t initrd_offset;
65 int big_endian;
66
67 #ifdef TARGET_WORDS_BIGENDIAN
68 big_endian = 1;
69 #else
70 big_endian = 0;
71 #endif
72
73 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
74 NULL, (uint64_t *)&entry, NULL,
75 (uint64_t *)&kernel_high, big_endian,
76 EM_MIPS, 1, 0);
77 if (kernel_size >= 0) {
78 if ((entry & ~0x7fffffffULL) == 0x80000000)
79 entry = (int32_t)entry;
80 } else {
81 fprintf(stderr, "qemu: could not load kernel '%s'\n",
82 loaderparams.kernel_filename);
83 exit(1);
84 }
85
86 /* load initrd */
87 initrd_size = 0;
88 initrd_offset = 0;
89 if (loaderparams.initrd_filename) {
90 initrd_size = get_image_size (loaderparams.initrd_filename);
91 if (initrd_size > 0) {
92 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
93 if (initrd_offset + initrd_size > loaderparams.ram_size) {
94 fprintf(stderr,
95 "qemu: memory too small for initial ram disk '%s'\n",
96 loaderparams.initrd_filename);
97 exit(1);
98 }
99 initrd_size = load_image_targphys(loaderparams.initrd_filename,
100 initrd_offset, loaderparams.ram_size - initrd_offset);
101 }
102 if (initrd_size == (target_ulong) -1) {
103 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
104 loaderparams.initrd_filename);
105 exit(1);
106 }
107 }
108 return entry;
109 }
110
111 static void main_cpu_reset(void *opaque)
112 {
113 ResetData *s = (ResetData *)opaque;
114 CPUMIPSState *env = &s->cpu->env;
115
116 cpu_reset(CPU(s->cpu));
117 env->active_tc.PC = s->vector & ~(target_ulong)1;
118 if (s->vector & 1) {
119 env->hflags |= MIPS_HFLAG_M16;
120 }
121 }
122
123 static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd)
124 {
125 DeviceState *dev;
126 SysBusDevice *s;
127
128 dev = qdev_create(NULL, "mipsnet");
129 qdev_set_nic_properties(dev, nd);
130 qdev_init_nofail(dev);
131
132 s = SYS_BUS_DEVICE(dev);
133 sysbus_connect_irq(s, 0, irq);
134 memory_region_add_subregion(get_system_io(),
135 base,
136 sysbus_mmio_get_region(s, 0));
137 }
138
139 static void
140 mips_mipssim_init(MachineState *machine)
141 {
142 ram_addr_t ram_size = machine->ram_size;
143 const char *cpu_model = machine->cpu_model;
144 const char *kernel_filename = machine->kernel_filename;
145 const char *kernel_cmdline = machine->kernel_cmdline;
146 const char *initrd_filename = machine->initrd_filename;
147 char *filename;
148 MemoryRegion *address_space_mem = get_system_memory();
149 MemoryRegion *isa = g_new(MemoryRegion, 1);
150 MemoryRegion *ram = g_new(MemoryRegion, 1);
151 MemoryRegion *bios = g_new(MemoryRegion, 1);
152 MIPSCPU *cpu;
153 CPUMIPSState *env;
154 ResetData *reset_info;
155 int bios_size;
156
157 /* Init CPUs. */
158 if (cpu_model == NULL) {
159 #ifdef TARGET_MIPS64
160 cpu_model = "5Kf";
161 #else
162 cpu_model = "24Kf";
163 #endif
164 }
165 cpu = cpu_mips_init(cpu_model);
166 if (cpu == NULL) {
167 fprintf(stderr, "Unable to find CPU definition\n");
168 exit(1);
169 }
170 env = &cpu->env;
171
172 reset_info = g_malloc0(sizeof(ResetData));
173 reset_info->cpu = cpu;
174 reset_info->vector = env->active_tc.PC;
175 qemu_register_reset(main_cpu_reset, reset_info);
176
177 /* Allocate RAM. */
178 memory_region_allocate_system_memory(ram, NULL, "mips_mipssim.ram",
179 ram_size);
180 memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE,
181 &error_fatal);
182 vmstate_register_ram_global(bios);
183 memory_region_set_readonly(bios, true);
184
185 memory_region_add_subregion(address_space_mem, 0, ram);
186
187 /* Map the BIOS / boot exception handler. */
188 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
189 /* Load a BIOS / boot exception handler image. */
190 if (bios_name == NULL)
191 bios_name = BIOS_FILENAME;
192 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
193 if (filename) {
194 bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
195 g_free(filename);
196 } else {
197 bios_size = -1;
198 }
199 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
200 !kernel_filename && !qtest_enabled()) {
201 /* Bail out if we have neither a kernel image nor boot vector code. */
202 error_report("Could not load MIPS bios '%s', and no "
203 "-kernel argument was specified", bios_name);
204 exit(1);
205 } else {
206 /* We have a boot vector start address. */
207 env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
208 }
209
210 if (kernel_filename) {
211 loaderparams.ram_size = ram_size;
212 loaderparams.kernel_filename = kernel_filename;
213 loaderparams.kernel_cmdline = kernel_cmdline;
214 loaderparams.initrd_filename = initrd_filename;
215 reset_info->vector = load_kernel();
216 }
217
218 /* Init CPU internal devices. */
219 cpu_mips_irq_init_cpu(cpu);
220 cpu_mips_clock_init(cpu);
221
222 /* Register 64 KB of ISA IO space at 0x1fd00000. */
223 memory_region_init_alias(isa, NULL, "isa_mmio",
224 get_system_io(), 0, 0x00010000);
225 memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
226
227 /* A single 16450 sits at offset 0x3f8. It is attached to
228 MIPS CPU INT2, which is interrupt 4. */
229 if (serial_hds[0])
230 serial_init(0x3f8, env->irq[4], 115200, serial_hds[0],
231 get_system_io());
232
233 if (nd_table[0].used)
234 /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
235 mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
236 }
237
238 static void mips_mipssim_machine_init(MachineClass *mc)
239 {
240 mc->desc = "MIPS MIPSsim platform";
241 mc->init = mips_mipssim_init;
242 }
243
244 DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)