PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / mips_jazz.c
1 /*
2 * QEMU MIPS Jazz support
3 *
4 * Copyright (c) 2007-2008 Hervé Poussineau
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw.h"
26 #include "mips.h"
27 #include "mips_cpudevs.h"
28 #include "pc.h"
29 #include "isa.h"
30 #include "fdc.h"
31 #include "sysemu.h"
32 #include "arch_init.h"
33 #include "boards.h"
34 #include "net.h"
35 #include "esp.h"
36 #include "mips-bios.h"
37 #include "loader.h"
38 #include "mc146818rtc.h"
39 #include "blockdev.h"
40 #include "sysbus.h"
41 #include "exec-memory.h"
42
43 enum jazz_model_e
44 {
45 JAZZ_MAGNUM,
46 JAZZ_PICA61,
47 };
48
49 static void main_cpu_reset(void *opaque)
50 {
51 CPUState *env = opaque;
52 cpu_reset(env);
53 }
54
55 static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
56 {
57 return cpu_inw(0x71);
58 }
59
60 static void rtc_write(void *opaque, target_phys_addr_t addr,
61 uint64_t val, unsigned size)
62 {
63 cpu_outw(0x71, val & 0xff);
64 }
65
66 static const MemoryRegionOps rtc_ops = {
67 .read = rtc_read,
68 .write = rtc_write,
69 .endianness = DEVICE_NATIVE_ENDIAN,
70 };
71
72 static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
73 unsigned size)
74 {
75 /* Nothing to do. That is only to ensure that
76 * the current DMA acknowledge cycle is completed. */
77 return 0xff;
78 }
79
80 static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
81 uint64_t val, unsigned size)
82 {
83 /* Nothing to do. That is only to ensure that
84 * the current DMA acknowledge cycle is completed. */
85 }
86
87 static const MemoryRegionOps dma_dummy_ops = {
88 .read = dma_dummy_read,
89 .write = dma_dummy_write,
90 .endianness = DEVICE_NATIVE_ENDIAN,
91 };
92
93 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
94 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
95
96 static void cpu_request_exit(void *opaque, int irq, int level)
97 {
98 CPUState *env = cpu_single_env;
99
100 if (env && level) {
101 cpu_exit(env);
102 }
103 }
104
105 static void mips_jazz_init(MemoryRegion *address_space,
106 MemoryRegion *address_space_io,
107 ram_addr_t ram_size,
108 const char *cpu_model,
109 enum jazz_model_e jazz_model)
110 {
111 char *filename;
112 int bios_size, n;
113 CPUState *env;
114 qemu_irq *rc4030, *i8259;
115 rc4030_dma *dmas;
116 void* rc4030_opaque;
117 MemoryRegion *rtc = g_new(MemoryRegion, 1);
118 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
119 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
120 NICInfo *nd;
121 DeviceState *dev;
122 SysBusDevice *sysbus;
123 ISABus *isa_bus;
124 ISADevice *pit;
125 DriveInfo *fds[MAX_FD];
126 qemu_irq esp_reset, dma_enable;
127 qemu_irq *cpu_exit_irq;
128 MemoryRegion *ram = g_new(MemoryRegion, 1);
129 MemoryRegion *bios = g_new(MemoryRegion, 1);
130 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
131
132 /* init CPUs */
133 if (cpu_model == NULL) {
134 #ifdef TARGET_MIPS64
135 cpu_model = "R4000";
136 #else
137 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
138 cpu_model = "24Kf";
139 #endif
140 }
141 env = cpu_init(cpu_model);
142 if (!env) {
143 fprintf(stderr, "Unable to find CPU definition\n");
144 exit(1);
145 }
146 qemu_register_reset(main_cpu_reset, env);
147
148 /* allocate RAM */
149 memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
150 vmstate_register_ram_global(ram);
151 memory_region_add_subregion(address_space, 0, ram);
152
153 memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
154 vmstate_register_ram_global(bios);
155 memory_region_set_readonly(bios, true);
156 memory_region_init_alias(bios2, "mips_jazz.bios", bios,
157 0, MAGNUM_BIOS_SIZE);
158 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
159 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
160
161 /* load the BIOS image. */
162 if (bios_name == NULL)
163 bios_name = BIOS_FILENAME;
164 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
165 if (filename) {
166 bios_size = load_image_targphys(filename, 0xfff00000LL,
167 MAGNUM_BIOS_SIZE);
168 g_free(filename);
169 } else {
170 bios_size = -1;
171 }
172 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
173 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
174 bios_name);
175 exit(1);
176 }
177
178 /* Init CPU internal devices */
179 cpu_mips_irq_init_cpu(env);
180 cpu_mips_clock_init(env);
181
182 /* Chipset */
183 rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
184 address_space);
185 memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
186 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
187
188 /* ISA devices */
189 isa_bus = isa_bus_new(NULL, address_space_io);
190 i8259 = i8259_init(isa_bus, env->irq[4]);
191 isa_bus_irqs(isa_bus, i8259);
192 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
193 DMA_init(0, cpu_exit_irq);
194 pit = pit_init(isa_bus, 0x40, 0);
195 pcspk_init(pit);
196
197 /* ISA IO space at 0x90000000 */
198 isa_mmio_init(0x90000000, 0x01000000);
199 isa_mem_base = 0x11000000;
200
201 /* Video card */
202 switch (jazz_model) {
203 case JAZZ_MAGNUM:
204 dev = qdev_create(NULL, "sysbus-g364");
205 qdev_init_nofail(dev);
206 sysbus = sysbus_from_qdev(dev);
207 sysbus_mmio_map(sysbus, 0, 0x60080000);
208 sysbus_mmio_map(sysbus, 1, 0x40000000);
209 sysbus_connect_irq(sysbus, 0, rc4030[3]);
210 {
211 /* Simple ROM, so user doesn't have to provide one */
212 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
213 memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
214 vmstate_register_ram_global(rom_mr);
215 memory_region_set_readonly(rom_mr, true);
216 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
217 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
218 rom[0] = 0x10; /* Mips G364 */
219 }
220 break;
221 case JAZZ_PICA61:
222 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
223 break;
224 default:
225 break;
226 }
227
228 /* Network controller */
229 for (n = 0; n < nb_nics; n++) {
230 nd = &nd_table[n];
231 if (!nd->model)
232 nd->model = g_strdup("dp83932");
233 if (strcmp(nd->model, "dp83932") == 0) {
234 dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
235 rc4030_opaque, rc4030_dma_memory_rw);
236 break;
237 } else if (strcmp(nd->model, "?") == 0) {
238 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
239 exit(1);
240 } else {
241 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
242 exit(1);
243 }
244 }
245
246 /* SCSI adapter */
247 esp_init(0x80002000, 0,
248 rc4030_dma_read, rc4030_dma_write, dmas[0],
249 rc4030[5], &esp_reset, &dma_enable);
250
251 /* Floppy */
252 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
253 fprintf(stderr, "qemu: too many floppy drives\n");
254 exit(1);
255 }
256 for (n = 0; n < MAX_FD; n++) {
257 fds[n] = drive_get(IF_FLOPPY, 0, n);
258 }
259 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
260
261 /* Real time clock */
262 rtc_init(isa_bus, 1980, NULL);
263 memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
264 memory_region_add_subregion(address_space, 0x80004000, rtc);
265
266 /* Keyboard (i8042) */
267 i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
268 memory_region_add_subregion(address_space, 0x80005000, i8042);
269
270 /* Serial ports */
271 if (serial_hds[0]) {
272 serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
273 serial_hds[0], DEVICE_NATIVE_ENDIAN);
274 }
275 if (serial_hds[1]) {
276 serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
277 serial_hds[1], DEVICE_NATIVE_ENDIAN);
278 }
279
280 /* Parallel port */
281 if (parallel_hds[0])
282 parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
283 parallel_hds[0]);
284
285 /* Sound card */
286 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
287 audio_init(isa_bus, NULL);
288
289 /* NVRAM */
290 dev = qdev_create(NULL, "ds1225y");
291 qdev_init_nofail(dev);
292 sysbus = sysbus_from_qdev(dev);
293 sysbus_mmio_map(sysbus, 0, 0x80009000);
294
295 /* LED indicator */
296 jazz_led_init(address_space, 0x8000f000);
297 }
298
299 static
300 void mips_magnum_init (ram_addr_t ram_size,
301 const char *boot_device,
302 const char *kernel_filename, const char *kernel_cmdline,
303 const char *initrd_filename, const char *cpu_model)
304 {
305 mips_jazz_init(get_system_memory(), get_system_io(),
306 ram_size, cpu_model, JAZZ_MAGNUM);
307 }
308
309 static
310 void mips_pica61_init (ram_addr_t ram_size,
311 const char *boot_device,
312 const char *kernel_filename, const char *kernel_cmdline,
313 const char *initrd_filename, const char *cpu_model)
314 {
315 mips_jazz_init(get_system_memory(), get_system_io(),
316 ram_size, cpu_model, JAZZ_PICA61);
317 }
318
319 static QEMUMachine mips_magnum_machine = {
320 .name = "magnum",
321 .desc = "MIPS Magnum",
322 .init = mips_magnum_init,
323 .use_scsi = 1,
324 };
325
326 static QEMUMachine mips_pica61_machine = {
327 .name = "pica61",
328 .desc = "Acer Pica 61",
329 .init = mips_pica61_init,
330 .use_scsi = 1,
331 };
332
333 static void mips_jazz_machine_init(void)
334 {
335 qemu_register_machine(&mips_magnum_machine);
336 qemu_register_machine(&mips_pica61_machine);
337 }
338
339 machine_init(mips_jazz_machine_init);