trace: switch position of headers to what Meson requires
[qemu.git] / hw / misc / aspeed_sdmc.c
1 /*
2 * ASPEED SDRAM Memory Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/module.h"
13 #include "qemu/error-report.h"
14 #include "hw/misc/aspeed_sdmc.h"
15 #include "hw/misc/aspeed_scu.h"
16 #include "hw/qdev-properties.h"
17 #include "migration/vmstate.h"
18 #include "qapi/error.h"
19 #include "trace.h"
20 #include "qemu/units.h"
21 #include "qemu/cutils.h"
22 #include "qapi/visitor.h"
23
24 /* Protection Key Register */
25 #define R_PROT (0x00 / 4)
26 #define PROT_UNLOCKED 0x01
27 #define PROT_HARDLOCKED 0x10 /* AST2600 */
28 #define PROT_SOFTLOCKED 0x00
29
30 #define PROT_KEY_UNLOCK 0xFC600309
31 #define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
32
33 /* Configuration Register */
34 #define R_CONF (0x04 / 4)
35
36 /* Control/Status Register #1 (ast2500) */
37 #define R_STATUS1 (0x60 / 4)
38 #define PHY_BUSY_STATE BIT(0)
39 #define PHY_PLL_LOCK_STATUS BIT(4)
40
41 #define R_ECC_TEST_CTRL (0x70 / 4)
42 #define ECC_TEST_FINISHED BIT(12)
43 #define ECC_TEST_FAIL BIT(13)
44
45 /*
46 * Configuration register Ox4 (for Aspeed AST2400 SOC)
47 *
48 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
49 * what we care about right now as it is checked by U-Boot to
50 * determine the RAM size.
51 */
52
53 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
54 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
55 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
56 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
57 #define ASPEED_SDMC_ECC_ENABLE (1 << 7)
58 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
59 #define ASPEED_SDMC_DRAM_BANK (1 << 5)
60 #define ASPEED_SDMC_DRAM_BURST (1 << 4)
61 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
62 #define ASPEED_SDMC_VGA_8MB 0x0
63 #define ASPEED_SDMC_VGA_16MB 0x1
64 #define ASPEED_SDMC_VGA_32MB 0x2
65 #define ASPEED_SDMC_VGA_64MB 0x3
66 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
67 #define ASPEED_SDMC_DRAM_64MB 0x0
68 #define ASPEED_SDMC_DRAM_128MB 0x1
69 #define ASPEED_SDMC_DRAM_256MB 0x2
70 #define ASPEED_SDMC_DRAM_512MB 0x3
71
72 #define ASPEED_SDMC_READONLY_MASK \
73 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
74 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
75 /*
76 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
77 *
78 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
79 * should be set to 1 for the AST2500 SOC.
80 */
81 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
82 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
83 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
84 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
85 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
86 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
87 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
88 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
89 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
90
91 /* DRAM size definitions differs */
92 #define ASPEED_SDMC_AST2500_128MB 0x0
93 #define ASPEED_SDMC_AST2500_256MB 0x1
94 #define ASPEED_SDMC_AST2500_512MB 0x2
95 #define ASPEED_SDMC_AST2500_1024MB 0x3
96
97 #define ASPEED_SDMC_AST2600_256MB 0x0
98 #define ASPEED_SDMC_AST2600_512MB 0x1
99 #define ASPEED_SDMC_AST2600_1024MB 0x2
100 #define ASPEED_SDMC_AST2600_2048MB 0x3
101
102 #define ASPEED_SDMC_AST2500_READONLY_MASK \
103 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
104 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
105 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
106
107 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
108 {
109 AspeedSDMCState *s = ASPEED_SDMC(opaque);
110
111 addr >>= 2;
112
113 if (addr >= ARRAY_SIZE(s->regs)) {
114 qemu_log_mask(LOG_GUEST_ERROR,
115 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
116 __func__, addr);
117 return 0;
118 }
119
120 return s->regs[addr];
121 }
122
123 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
124 unsigned int size)
125 {
126 AspeedSDMCState *s = ASPEED_SDMC(opaque);
127 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
128
129 addr >>= 2;
130
131 if (addr >= ARRAY_SIZE(s->regs)) {
132 qemu_log_mask(LOG_GUEST_ERROR,
133 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
134 __func__, addr);
135 return;
136 }
137
138 asc->write(s, addr, data);
139 }
140
141 static const MemoryRegionOps aspeed_sdmc_ops = {
142 .read = aspeed_sdmc_read,
143 .write = aspeed_sdmc_write,
144 .endianness = DEVICE_LITTLE_ENDIAN,
145 .valid.min_access_size = 4,
146 .valid.max_access_size = 4,
147 };
148
149 static int ast2400_rambits(AspeedSDMCState *s)
150 {
151 switch (s->ram_size >> 20) {
152 case 64:
153 return ASPEED_SDMC_DRAM_64MB;
154 case 128:
155 return ASPEED_SDMC_DRAM_128MB;
156 case 256:
157 return ASPEED_SDMC_DRAM_256MB;
158 case 512:
159 return ASPEED_SDMC_DRAM_512MB;
160 default:
161 g_assert_not_reached();
162 break;
163 }
164 }
165
166 static int ast2500_rambits(AspeedSDMCState *s)
167 {
168 switch (s->ram_size >> 20) {
169 case 128:
170 return ASPEED_SDMC_AST2500_128MB;
171 case 256:
172 return ASPEED_SDMC_AST2500_256MB;
173 case 512:
174 return ASPEED_SDMC_AST2500_512MB;
175 case 1024:
176 return ASPEED_SDMC_AST2500_1024MB;
177 default:
178 g_assert_not_reached();
179 break;
180 }
181 }
182
183 static int ast2600_rambits(AspeedSDMCState *s)
184 {
185 switch (s->ram_size >> 20) {
186 case 256:
187 return ASPEED_SDMC_AST2600_256MB;
188 case 512:
189 return ASPEED_SDMC_AST2600_512MB;
190 case 1024:
191 return ASPEED_SDMC_AST2600_1024MB;
192 case 2048:
193 return ASPEED_SDMC_AST2600_2048MB;
194 default:
195 g_assert_not_reached();
196 break;
197 }
198 }
199
200 static void aspeed_sdmc_reset(DeviceState *dev)
201 {
202 AspeedSDMCState *s = ASPEED_SDMC(dev);
203 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
204
205 memset(s->regs, 0, sizeof(s->regs));
206
207 /* Set ram size bit and defaults values */
208 s->regs[R_CONF] = asc->compute_conf(s, 0);
209 }
210
211 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
212 void *opaque, Error **errp)
213 {
214 AspeedSDMCState *s = ASPEED_SDMC(obj);
215 int64_t value = s->ram_size;
216
217 visit_type_int(v, name, &value, errp);
218 }
219
220 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
221 void *opaque, Error **errp)
222 {
223 int i;
224 char *sz;
225 int64_t value;
226 AspeedSDMCState *s = ASPEED_SDMC(obj);
227 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
228
229 if (!visit_type_int(v, name, &value, errp)) {
230 return;
231 }
232
233 for (i = 0; asc->valid_ram_sizes[i]; i++) {
234 if (value == asc->valid_ram_sizes[i]) {
235 s->ram_size = value;
236 return;
237 }
238 }
239
240 sz = size_to_str(value);
241 error_setg(errp, "Invalid RAM size %s", sz);
242 g_free(sz);
243 }
244
245 static void aspeed_sdmc_initfn(Object *obj)
246 {
247 object_property_add(obj, "ram-size", "int",
248 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
249 NULL, NULL);
250 }
251
252 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
253 {
254 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
255 AspeedSDMCState *s = ASPEED_SDMC(dev);
256 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
257
258 assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
259 s->max_ram_size = asc->max_ram_size;
260
261 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
262 TYPE_ASPEED_SDMC, 0x1000);
263 sysbus_init_mmio(sbd, &s->iomem);
264 }
265
266 static const VMStateDescription vmstate_aspeed_sdmc = {
267 .name = "aspeed.sdmc",
268 .version_id = 1,
269 .minimum_version_id = 1,
270 .fields = (VMStateField[]) {
271 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
272 VMSTATE_END_OF_LIST()
273 }
274 };
275
276 static Property aspeed_sdmc_properties[] = {
277 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
278 DEFINE_PROP_END_OF_LIST(),
279 };
280
281 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
282 {
283 DeviceClass *dc = DEVICE_CLASS(klass);
284 dc->realize = aspeed_sdmc_realize;
285 dc->reset = aspeed_sdmc_reset;
286 dc->desc = "ASPEED SDRAM Memory Controller";
287 dc->vmsd = &vmstate_aspeed_sdmc;
288 device_class_set_props(dc, aspeed_sdmc_properties);
289 }
290
291 static const TypeInfo aspeed_sdmc_info = {
292 .name = TYPE_ASPEED_SDMC,
293 .parent = TYPE_SYS_BUS_DEVICE,
294 .instance_size = sizeof(AspeedSDMCState),
295 .instance_init = aspeed_sdmc_initfn,
296 .class_init = aspeed_sdmc_class_init,
297 .class_size = sizeof(AspeedSDMCClass),
298 .abstract = true,
299 };
300
301 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
302 {
303 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
304 ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
305
306 /* Make sure readonly bits are kept */
307 data &= ~ASPEED_SDMC_READONLY_MASK;
308
309 return data | fixed_conf;
310 }
311
312 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
313 uint32_t data)
314 {
315 if (reg == R_PROT) {
316 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
317 return;
318 }
319
320 if (!s->regs[R_PROT]) {
321 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
322 return;
323 }
324
325 switch (reg) {
326 case R_CONF:
327 data = aspeed_2400_sdmc_compute_conf(s, data);
328 break;
329 default:
330 break;
331 }
332
333 s->regs[reg] = data;
334 }
335
336 static const uint64_t
337 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
338
339 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
340 {
341 DeviceClass *dc = DEVICE_CLASS(klass);
342 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
343
344 dc->desc = "ASPEED 2400 SDRAM Memory Controller";
345 asc->max_ram_size = 512 * MiB;
346 asc->compute_conf = aspeed_2400_sdmc_compute_conf;
347 asc->write = aspeed_2400_sdmc_write;
348 asc->valid_ram_sizes = aspeed_2400_ram_sizes;
349 }
350
351 static const TypeInfo aspeed_2400_sdmc_info = {
352 .name = TYPE_ASPEED_2400_SDMC,
353 .parent = TYPE_ASPEED_SDMC,
354 .class_init = aspeed_2400_sdmc_class_init,
355 };
356
357 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
358 {
359 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
360 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
361 ASPEED_SDMC_CACHE_INITIAL_DONE |
362 ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
363
364 /* Make sure readonly bits are kept */
365 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
366
367 return data | fixed_conf;
368 }
369
370 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
371 uint32_t data)
372 {
373 if (reg == R_PROT) {
374 s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
375 return;
376 }
377
378 if (!s->regs[R_PROT]) {
379 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
380 return;
381 }
382
383 switch (reg) {
384 case R_CONF:
385 data = aspeed_2500_sdmc_compute_conf(s, data);
386 break;
387 case R_STATUS1:
388 /* Will never return 'busy' */
389 data &= ~PHY_BUSY_STATE;
390 break;
391 case R_ECC_TEST_CTRL:
392 /* Always done, always happy */
393 data |= ECC_TEST_FINISHED;
394 data &= ~ECC_TEST_FAIL;
395 break;
396 default:
397 break;
398 }
399
400 s->regs[reg] = data;
401 }
402
403 static const uint64_t
404 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
405
406 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
407 {
408 DeviceClass *dc = DEVICE_CLASS(klass);
409 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
410
411 dc->desc = "ASPEED 2500 SDRAM Memory Controller";
412 asc->max_ram_size = 1 * GiB;
413 asc->compute_conf = aspeed_2500_sdmc_compute_conf;
414 asc->write = aspeed_2500_sdmc_write;
415 asc->valid_ram_sizes = aspeed_2500_ram_sizes;
416 }
417
418 static const TypeInfo aspeed_2500_sdmc_info = {
419 .name = TYPE_ASPEED_2500_SDMC,
420 .parent = TYPE_ASPEED_SDMC,
421 .class_init = aspeed_2500_sdmc_class_init,
422 };
423
424 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
425 {
426 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
427 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
428 ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
429
430 /* Make sure readonly bits are kept (use ast2500 mask) */
431 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
432
433 return data | fixed_conf;
434 }
435
436 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
437 uint32_t data)
438 {
439 if (s->regs[R_PROT] == PROT_HARDLOCKED) {
440 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
441 __func__);
442 return;
443 }
444
445 if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
446 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
447 return;
448 }
449
450 switch (reg) {
451 case R_PROT:
452 if (data == PROT_KEY_UNLOCK) {
453 data = PROT_UNLOCKED;
454 } else if (data == PROT_KEY_HARDLOCK) {
455 data = PROT_HARDLOCKED;
456 } else {
457 data = PROT_SOFTLOCKED;
458 }
459 break;
460 case R_CONF:
461 data = aspeed_2600_sdmc_compute_conf(s, data);
462 break;
463 case R_STATUS1:
464 /* Will never return 'busy'. 'lock status' is always set */
465 data &= ~PHY_BUSY_STATE;
466 data |= PHY_PLL_LOCK_STATUS;
467 break;
468 case R_ECC_TEST_CTRL:
469 /* Always done, always happy */
470 data |= ECC_TEST_FINISHED;
471 data &= ~ECC_TEST_FAIL;
472 break;
473 default:
474 break;
475 }
476
477 s->regs[reg] = data;
478 }
479
480 static const uint64_t
481 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
482
483 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
484 {
485 DeviceClass *dc = DEVICE_CLASS(klass);
486 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
487
488 dc->desc = "ASPEED 2600 SDRAM Memory Controller";
489 asc->max_ram_size = 2 * GiB;
490 asc->compute_conf = aspeed_2600_sdmc_compute_conf;
491 asc->write = aspeed_2600_sdmc_write;
492 asc->valid_ram_sizes = aspeed_2600_ram_sizes;
493 }
494
495 static const TypeInfo aspeed_2600_sdmc_info = {
496 .name = TYPE_ASPEED_2600_SDMC,
497 .parent = TYPE_ASPEED_SDMC,
498 .class_init = aspeed_2600_sdmc_class_init,
499 };
500
501 static void aspeed_sdmc_register_types(void)
502 {
503 type_register_static(&aspeed_sdmc_info);
504 type_register_static(&aspeed_2400_sdmc_info);
505 type_register_static(&aspeed_2500_sdmc_info);
506 type_register_static(&aspeed_2600_sdmc_info);
507 }
508
509 type_init(aspeed_sdmc_register_types);