auxbus: Move QOM macros to header
[qemu.git] / hw / misc / auxbus.c
1 /*
2 * auxbus.c
3 *
4 * Copyright 2015 : GreenSocs Ltd
5 * http://www.greensocs.com/ , email: info@greensocs.com
6 *
7 * Developed by :
8 * Frederic Konrad <fred.konrad@greensocs.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option)any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
25 /*
26 * This is an implementation of the AUX bus for VESA Display Port v1.1a.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qemu/units.h"
31 #include "qemu/log.h"
32 #include "qemu/module.h"
33 #include "hw/misc/auxbus.h"
34 #include "hw/i2c/i2c.h"
35 #include "monitor/monitor.h"
36 #include "qapi/error.h"
37
38 #ifndef DEBUG_AUX
39 #define DEBUG_AUX 0
40 #endif
41
42 #define DPRINTF(fmt, ...) do { \
43 if (DEBUG_AUX) { \
44 qemu_log("aux: " fmt , ## __VA_ARGS__); \
45 } \
46 } while (0)
47
48
49 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
50 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge);
51
52 /* aux-bus implementation (internal not public) */
53 static void aux_bus_class_init(ObjectClass *klass, void *data)
54 {
55 BusClass *k = BUS_CLASS(klass);
56
57 /* AUXSlave has an MMIO so we need to change the way we print information
58 * in monitor.
59 */
60 k->print_dev = aux_slave_dev_print;
61 }
62
63 AUXBus *aux_bus_init(DeviceState *parent, const char *name)
64 {
65 AUXBus *bus;
66 Object *auxtoi2c;
67
68 bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
69 auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
70 &error_abort, NULL);
71
72 bus->bridge = AUXTOI2C(auxtoi2c);
73
74 /* Memory related. */
75 bus->aux_io = g_malloc(sizeof(*bus->aux_io));
76 memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB);
77 address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
78 return bus;
79 }
80
81 void aux_bus_realize(AUXBus *bus)
82 {
83 qdev_realize(DEVICE(bus->bridge), BUS(bus), &error_fatal);
84 }
85
86 void aux_map_slave(AUXSlave *aux_dev, hwaddr addr)
87 {
88 DeviceState *dev = DEVICE(aux_dev);
89 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
90 memory_region_add_subregion(bus->aux_io, addr, aux_dev->mmio);
91 }
92
93 static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
94 {
95 return (dev == DEVICE(bus->bridge));
96 }
97
98 I2CBus *aux_get_i2c_bus(AUXBus *bus)
99 {
100 return aux_bridge_get_i2c_bus(bus->bridge);
101 }
102
103 AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address,
104 uint8_t len, uint8_t *data)
105 {
106 AUXReply ret = AUX_NACK;
107 I2CBus *i2c_bus = aux_get_i2c_bus(bus);
108 size_t i;
109 bool is_write = false;
110
111 DPRINTF("request at address 0x%" PRIX32 ", command %u, len %u\n", address,
112 cmd, len);
113
114 switch (cmd) {
115 /*
116 * Forward the request on the AUX bus..
117 */
118 case WRITE_AUX:
119 case READ_AUX:
120 is_write = cmd == READ_AUX ? false : true;
121 for (i = 0; i < len; i++) {
122 if (!address_space_rw(&bus->aux_addr_space, address++,
123 MEMTXATTRS_UNSPECIFIED, data++, 1,
124 is_write)) {
125 ret = AUX_I2C_ACK;
126 } else {
127 ret = AUX_NACK;
128 break;
129 }
130 }
131 break;
132 /*
133 * Classic I2C transactions..
134 */
135 case READ_I2C:
136 case WRITE_I2C:
137 is_write = cmd == READ_I2C ? false : true;
138 if (i2c_bus_busy(i2c_bus)) {
139 i2c_end_transfer(i2c_bus);
140 }
141
142 if (i2c_start_transfer(i2c_bus, address, is_write)) {
143 ret = AUX_I2C_NACK;
144 break;
145 }
146
147 ret = AUX_I2C_ACK;
148 while (len > 0) {
149 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
150 ret = AUX_I2C_NACK;
151 break;
152 }
153 len--;
154 }
155 i2c_end_transfer(i2c_bus);
156 break;
157 /*
158 * I2C MOT transactions.
159 *
160 * Here we send a start when:
161 * - We didn't start transaction yet.
162 * - We had a READ and we do a WRITE.
163 * - We changed the address.
164 */
165 case WRITE_I2C_MOT:
166 case READ_I2C_MOT:
167 is_write = cmd == READ_I2C_MOT ? false : true;
168 ret = AUX_I2C_NACK;
169 if (!i2c_bus_busy(i2c_bus)) {
170 /*
171 * No transactions started..
172 */
173 if (i2c_start_transfer(i2c_bus, address, is_write)) {
174 break;
175 }
176 } else if ((address != bus->last_i2c_address) ||
177 (bus->last_transaction != cmd)) {
178 /*
179 * Transaction started but we need to restart..
180 */
181 i2c_end_transfer(i2c_bus);
182 if (i2c_start_transfer(i2c_bus, address, is_write)) {
183 break;
184 }
185 }
186
187 bus->last_transaction = cmd;
188 bus->last_i2c_address = address;
189 while (len > 0) {
190 if (i2c_send_recv(i2c_bus, data++, is_write) < 0) {
191 i2c_end_transfer(i2c_bus);
192 break;
193 }
194 len--;
195 }
196 if (len == 0) {
197 ret = AUX_I2C_ACK;
198 }
199 break;
200 default:
201 qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd);
202 return AUX_NACK;
203 }
204
205 DPRINTF("reply: %u\n", ret);
206 return ret;
207 }
208
209 static const TypeInfo aux_bus_info = {
210 .name = TYPE_AUX_BUS,
211 .parent = TYPE_BUS,
212 .instance_size = sizeof(AUXBus),
213 .class_init = aux_bus_class_init
214 };
215
216 /* aux-i2c implementation (internal not public) */
217 struct AUXTOI2CState {
218 /*< private >*/
219 DeviceState parent_obj;
220
221 /*< public >*/
222 I2CBus *i2c_bus;
223 };
224
225 static void aux_bridge_class_init(ObjectClass *oc, void *data)
226 {
227 DeviceClass *dc = DEVICE_CLASS(oc);
228
229 /* This device is private and is created only once for each
230 * aux-bus in aux_bus_init(..). So don't allow the user to add one.
231 */
232 dc->user_creatable = false;
233 }
234
235 static void aux_bridge_init(Object *obj)
236 {
237 AUXTOI2CState *s = AUXTOI2C(obj);
238
239 s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
240 }
241
242 static inline I2CBus *aux_bridge_get_i2c_bus(AUXTOI2CState *bridge)
243 {
244 return bridge->i2c_bus;
245 }
246
247 static const TypeInfo aux_to_i2c_type_info = {
248 .name = TYPE_AUXTOI2C,
249 .parent = TYPE_AUX_SLAVE,
250 .class_init = aux_bridge_class_init,
251 .instance_size = sizeof(AUXTOI2CState),
252 .instance_init = aux_bridge_init
253 };
254
255 /* aux-slave implementation */
256 static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
257 {
258 AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
259 AUXSlave *s;
260
261 /* Don't print anything if the device is I2C "bridge". */
262 if (aux_bus_is_bridge(bus, dev)) {
263 return;
264 }
265
266 s = AUX_SLAVE(dev);
267
268 monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
269 indent, "",
270 object_property_get_uint(OBJECT(s->mmio), "addr", NULL),
271 memory_region_size(s->mmio));
272 }
273
274 void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
275 {
276 assert(!aux_slave->mmio);
277 aux_slave->mmio = mmio;
278 }
279
280 static void aux_slave_class_init(ObjectClass *klass, void *data)
281 {
282 DeviceClass *k = DEVICE_CLASS(klass);
283
284 set_bit(DEVICE_CATEGORY_MISC, k->categories);
285 k->bus_type = TYPE_AUX_BUS;
286 }
287
288 static const TypeInfo aux_slave_type_info = {
289 .name = TYPE_AUX_SLAVE,
290 .parent = TYPE_DEVICE,
291 .instance_size = sizeof(AUXSlave),
292 .abstract = true,
293 .class_init = aux_slave_class_init,
294 };
295
296 static void aux_register_types(void)
297 {
298 type_register_static(&aux_bus_info);
299 type_register_static(&aux_slave_type_info);
300 type_register_static(&aux_to_i2c_type_info);
301 }
302
303 type_init(aux_register_types)