hw/misc: QOM'ify exynos4210_pmu.c
[qemu.git] / hw / misc / exynos4210_pmu.c
1 /*
2 * Exynos4210 Power Management Unit (PMU) Emulation
3 *
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov <m.kozlov@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * This model implements PMU registers just as a bulk of memory. Currently,
23 * the only reason this device exists is that secondary CPU boot loader
24 * uses PMU INFORM5 register as a holding pen.
25 */
26
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29
30 #ifndef DEBUG_PMU
31 #define DEBUG_PMU 0
32 #endif
33
34 #ifndef DEBUG_PMU_EXTEND
35 #define DEBUG_PMU_EXTEND 0
36 #endif
37
38 #if DEBUG_PMU
39 #define PRINT_DEBUG(fmt, args...) \
40 do { \
41 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
42 } while (0)
43
44 #if DEBUG_PMU_EXTEND
45 #define PRINT_DEBUG_EXTEND(fmt, args...) \
46 do { \
47 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
48 } while (0)
49 #else
50 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
51 #endif /* EXTEND */
52
53 #else
54 #define PRINT_DEBUG(fmt, args...) do {} while (0)
55 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
56 #endif
57
58 /*
59 * Offsets for PMU registers
60 */
61 #define OM_STAT 0x0000 /* OM status register */
62 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */
63 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */
64 /* Decides whether system-level low-power mode is used. */
65 #define SYSTEM_POWER_DOWN_CTRL 0x0200
66 /* Sets control options for CENTRAL_SEQ */
67 #define SYSTEM_POWER_DOWN_OPTION 0x0208
68 #define SWRESET 0x0400 /* Generate software reset */
69 #define RST_STAT 0x0404 /* Reset status register */
70 #define WAKEUP_STAT 0x0600 /* Wakeup status register */
71 #define EINT_WAKEUP_MASK 0x0604 /* Configure External INTerrupt mask */
72 #define WAKEUP_MASK 0x0608 /* Configure wakeup source mask */
73 #define HDMI_PHY_CONTROL 0x0700 /* HDMI PHY control register */
74 #define USBDEVICE_PHY_CONTROL 0x0704 /* USB Device PHY control register */
75 #define USBHOST_PHY_CONTROL 0x0708 /* USB HOST PHY control register */
76 #define DAC_PHY_CONTROL 0x070C /* DAC control register */
77 #define MIPI_PHY0_CONTROL 0x0710 /* MIPI PHY control register */
78 #define MIPI_PHY1_CONTROL 0x0714 /* MIPI PHY control register */
79 #define ADC_PHY_CONTROL 0x0718 /* TS-ADC control register */
80 #define PCIe_PHY_CONTROL 0x071C /* TS-PCIe control register */
81 #define SATA_PHY_CONTROL 0x0720 /* TS-SATA control register */
82 #define INFORM0 0x0800 /* Information register 0 */
83 #define INFORM1 0x0804 /* Information register 1 */
84 #define INFORM2 0x0808 /* Information register 2 */
85 #define INFORM3 0x080C /* Information register 3 */
86 #define INFORM4 0x0810 /* Information register 4 */
87 #define INFORM5 0x0814 /* Information register 5 */
88 #define INFORM6 0x0818 /* Information register 6 */
89 #define INFORM7 0x081C /* Information register 7 */
90 #define PMU_DEBUG 0x0A00 /* PMU debug register */
91 /* Registers to set system-level low-power option */
92 #define ARM_CORE0_SYS_PWR_REG 0x1000
93 #define ARM_CORE1_SYS_PWR_REG 0x1010
94 #define ARM_COMMON_SYS_PWR_REG 0x1080
95 #define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0
96 #define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4
97 #define CMU_ACLKSTOP_SYS_PWR_REG 0x1100
98 #define CMU_SCLKSTOP_SYS_PWR_REG 0x1104
99 #define CMU_RESET_SYS_PWR_REG 0x110C
100 #define APLL_SYSCLK_SYS_PWR_REG 0x1120
101 #define MPLL_SYSCLK_SYS_PWR_REG 0x1124
102 #define VPLL_SYSCLK_SYS_PWR_REG 0x1128
103 #define EPLL_SYSCLK_SYS_PWR_REG 0x112C
104 #define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG 0x1138
105 #define CMU_RESET_GPS_ALIVE_SYS_PWR_REG 0x113C
106 #define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140
107 #define CMU_CLKSTOP_TV_SYS_PWR_REG 0x1144
108 #define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148
109 #define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C
110 #define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150
111 #define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154
112 #define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158
113 #define CMU_CLKSTOP_GPS_SYS_PWR_REG 0x115C
114 #define CMU_RESET_CAM_SYS_PWR_REG 0x1160
115 #define CMU_RESET_TV_SYS_PWR_REG 0x1164
116 #define CMU_RESET_MFC_SYS_PWR_REG 0x1168
117 #define CMU_RESET_G3D_SYS_PWR_REG 0x116C
118 #define CMU_RESET_LCD0_SYS_PWR_REG 0x1170
119 #define CMU_RESET_LCD1_SYS_PWR_REG 0x1174
120 #define CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178
121 #define CMU_RESET_GPS_SYS_PWR_REG 0x117C
122 #define TOP_BUS_SYS_PWR_REG 0x1180
123 #define TOP_RETENTION_SYS_PWR_REG 0x1184
124 #define TOP_PWR_SYS_PWR_REG 0x1188
125 #define LOGIC_RESET_SYS_PWR_REG 0x11A0
126 #define OneNANDXL_MEM_SYS_PWR_REG 0x11C0
127 #define MODEMIF_MEM_SYS_PWR_REG 0x11C4
128 #define USBDEVICE_MEM_SYS_PWR_REG 0x11CC
129 #define SDMMC_MEM_SYS_PWR_REG 0x11D0
130 #define CSSYS_MEM_SYS_PWR_REG 0x11D4
131 #define SECSS_MEM_SYS_PWR_REG 0x11D8
132 #define PCIe_MEM_SYS_PWR_REG 0x11E0
133 #define SATA_MEM_SYS_PWR_REG 0x11E4
134 #define PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
135 #define PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204
136 #define PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
137 #define PAD_RETENTION_UART_SYS_PWR_REG 0x1224
138 #define PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
139 #define PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
140 #define PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
141 #define PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
142 #define PAD_ISOLATION_SYS_PWR_REG 0x1240
143 #define PAD_ALV_SEL_SYS_PWR_REG 0x1260
144 #define XUSBXTI_SYS_PWR_REG 0x1280
145 #define XXTI_SYS_PWR_REG 0x1284
146 #define EXT_REGULATOR_SYS_PWR_REG 0x12C0
147 #define GPIO_MODE_SYS_PWR_REG 0x1300
148 #define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340
149 #define CAM_SYS_PWR_REG 0x1380
150 #define TV_SYS_PWR_REG 0x1384
151 #define MFC_SYS_PWR_REG 0x1388
152 #define G3D_SYS_PWR_REG 0x138C
153 #define LCD0_SYS_PWR_REG 0x1390
154 #define LCD1_SYS_PWR_REG 0x1394
155 #define MAUDIO_SYS_PWR_REG 0x1398
156 #define GPS_SYS_PWR_REG 0x139C
157 #define GPS_ALIVE_SYS_PWR_REG 0x13A0
158 #define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */
159 #define ARM_CORE0_STATUS 0x2004 /* Check power mode of ARM_CORE0 */
160 #define ARM_CORE0_OPTION 0x2008 /* Sets control options for ARM_CORE0 */
161 #define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */
162 #define ARM_CORE1_STATUS 0x2084 /* Check power mode of ARM_CORE1 */
163 #define ARM_CORE1_OPTION 0x2088 /* Sets control options for ARM_CORE0 */
164 #define ARM_COMMON_OPTION 0x2408 /* Sets control options for ARM_COMMON */
165 /* Configure power mode of ARM_CPU_L2_0 */
166 #define ARM_CPU_L2_0_CONFIGURATION 0x2600
167 #define ARM_CPU_L2_0_STATUS 0x2604 /* Check power mode of ARM_CPU_L2_0 */
168 /* Configure power mode of ARM_CPU_L2_1 */
169 #define ARM_CPU_L2_1_CONFIGURATION 0x2620
170 #define ARM_CPU_L2_1_STATUS 0x2624 /* Check power mode of ARM_CPU_L2_1 */
171 /* Sets control options for PAD_RETENTION_MAUDIO */
172 #define PAD_RETENTION_MAUDIO_OPTION 0x3028
173 /* Sets control options for PAD_RETENTION_GPIO */
174 #define PAD_RETENTION_GPIO_OPTION 0x3108
175 /* Sets control options for PAD_RETENTION_UART */
176 #define PAD_RETENTION_UART_OPTION 0x3128
177 /* Sets control options for PAD_RETENTION_MMCA */
178 #define PAD_RETENTION_MMCA_OPTION 0x3148
179 /* Sets control options for PAD_RETENTION_MMCB */
180 #define PAD_RETENTION_MMCB_OPTION 0x3168
181 /* Sets control options for PAD_RETENTION_EBIA */
182 #define PAD_RETENTION_EBIA_OPTION 0x3188
183 /* Sets control options for PAD_RETENTION_EBIB */
184 #define PAD_RETENTION_EBIB_OPTION 0x31A8
185 #define PS_HOLD_CONTROL 0x330C /* PS_HOLD control register */
186 #define XUSBXTI_CONFIGURATION 0x3400 /* Configure the pad of XUSBXTI */
187 #define XUSBXTI_STATUS 0x3404 /* Check the pad of XUSBXTI */
188 /* Sets time required for XUSBXTI to be stabilized */
189 #define XUSBXTI_DURATION 0x341C
190 #define XXTI_CONFIGURATION 0x3420 /* Configure the pad of XXTI */
191 #define XXTI_STATUS 0x3424 /* Check the pad of XXTI */
192 /* Sets time required for XXTI to be stabilized */
193 #define XXTI_DURATION 0x343C
194 /* Sets time required for EXT_REGULATOR to be stabilized */
195 #define EXT_REGULATOR_DURATION 0x361C
196 #define CAM_CONFIGURATION 0x3C00 /* Configure power mode of CAM */
197 #define CAM_STATUS 0x3C04 /* Check power mode of CAM */
198 #define CAM_OPTION 0x3C08 /* Sets control options for CAM */
199 #define TV_CONFIGURATION 0x3C20 /* Configure power mode of TV */
200 #define TV_STATUS 0x3C24 /* Check power mode of TV */
201 #define TV_OPTION 0x3C28 /* Sets control options for TV */
202 #define MFC_CONFIGURATION 0x3C40 /* Configure power mode of MFC */
203 #define MFC_STATUS 0x3C44 /* Check power mode of MFC */
204 #define MFC_OPTION 0x3C48 /* Sets control options for MFC */
205 #define G3D_CONFIGURATION 0x3C60 /* Configure power mode of G3D */
206 #define G3D_STATUS 0x3C64 /* Check power mode of G3D */
207 #define G3D_OPTION 0x3C68 /* Sets control options for G3D */
208 #define LCD0_CONFIGURATION 0x3C80 /* Configure power mode of LCD0 */
209 #define LCD0_STATUS 0x3C84 /* Check power mode of LCD0 */
210 #define LCD0_OPTION 0x3C88 /* Sets control options for LCD0 */
211 #define LCD1_CONFIGURATION 0x3CA0 /* Configure power mode of LCD1 */
212 #define LCD1_STATUS 0x3CA4 /* Check power mode of LCD1 */
213 #define LCD1_OPTION 0x3CA8 /* Sets control options for LCD1 */
214 #define GPS_CONFIGURATION 0x3CE0 /* Configure power mode of GPS */
215 #define GPS_STATUS 0x3CE4 /* Check power mode of GPS */
216 #define GPS_OPTION 0x3CE8 /* Sets control options for GPS */
217 #define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */
218 #define GPS_ALIVE_STATUS 0x3D04 /* Check power mode of GPS */
219 #define GPS_ALIVE_OPTION 0x3D08 /* Sets control options for GPS */
220
221 #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c
222
223 typedef struct Exynos4210PmuReg {
224 const char *name; /* for debug only */
225 uint32_t offset;
226 uint32_t reset_value;
227 } Exynos4210PmuReg;
228
229 static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
230 {"OM_STAT", OM_STAT, 0x00000000},
231 {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000},
232 {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001},
233 {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000},
234 {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000},
235 {"SWRESET", SWRESET, 0x00000000},
236 {"RST_STAT", RST_STAT, 0x00000000},
237 {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000},
238 {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000},
239 {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000},
240 {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000},
241 {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000},
242 {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000},
243 {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000},
244 {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000},
245 {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000},
246 {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001},
247 {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000},
248 {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000},
249 {"INFORM0", INFORM0, 0x00000000},
250 {"INFORM1", INFORM1, 0x00000000},
251 {"INFORM2", INFORM2, 0x00000000},
252 {"INFORM3", INFORM3, 0x00000000},
253 {"INFORM4", INFORM4, 0x00000000},
254 {"INFORM5", INFORM5, 0x00000000},
255 {"INFORM6", INFORM6, 0x00000000},
256 {"INFORM7", INFORM7, 0x00000000},
257 {"PMU_DEBUG", PMU_DEBUG, 0x00000000},
258 {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF},
259 {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF},
260 {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF},
261 {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF},
262 {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF},
263 {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
264 {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
265 {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF},
266 {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
267 {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
268 {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
269 {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
270 {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
271 0xFFFFFFFF},
272 {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
273 0xFFFFFFFF},
274 {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF},
275 {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF},
276 {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF},
277 {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF},
278 {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
279 {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
280 {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
281 0xFFFFFFFF},
282 {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF},
283 {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF},
284 {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF},
285 {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF},
286 {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF},
287 {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
288 {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
289 {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
290 {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF},
291 {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF},
292 {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF},
293 {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF},
294 {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF},
295 {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF},
296 {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF},
297 {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF},
298 {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF},
299 {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
300 {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
301 {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF},
302 {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF},
303 {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
304 0xFFFFFFFF},
305 {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
306 0xFFFFFFFF},
307 {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
308 0xFFFFFFFF},
309 {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
310 0xFFFFFFFF},
311 {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
312 0xFFFFFFFF},
313 {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
314 0xFFFFFFFF},
315 {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
316 0xFFFFFFFF},
317 {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
318 0xFFFFFFFF},
319 {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF},
320 {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF},
321 {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF},
322 {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF},
323 {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF},
324 {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF},
325 {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
326 {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF},
327 {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF},
328 {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF},
329 {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF},
330 {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF},
331 {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF},
332 {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
333 {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF},
334 {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF},
335 {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003},
336 {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003},
337 {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001},
338 {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003},
339 {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003},
340 {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001},
341 {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001},
342 {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003},
343 {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003},
344 {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003},
345 {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003},
346 {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000},
347 {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000},
348 {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000},
349 {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000},
350 {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
351 {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
352 {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
353 {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200},
354 {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
355 {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
356 {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
357 {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001},
358 {"XXTI_STATUS", XXTI_STATUS, 0x00000001},
359 {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000},
360 {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF},
361 {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007},
362 {"CAM_STATUS", CAM_STATUS, 0x00060007},
363 {"CAM_OPTION", CAM_OPTION, 0x00000001},
364 {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007},
365 {"TV_STATUS", TV_STATUS, 0x00060007},
366 {"TV_OPTION", TV_OPTION, 0x00000001},
367 {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007},
368 {"MFC_STATUS", MFC_STATUS, 0x00060007},
369 {"MFC_OPTION", MFC_OPTION, 0x00000001},
370 {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007},
371 {"G3D_STATUS", G3D_STATUS, 0x00060007},
372 {"G3D_OPTION", G3D_OPTION, 0x00000001},
373 {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007},
374 {"LCD0_STATUS", LCD0_STATUS, 0x00060007},
375 {"LCD0_OPTION", LCD0_OPTION, 0x00000001},
376 {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007},
377 {"LCD1_STATUS", LCD1_STATUS, 0x00060007},
378 {"LCD1_OPTION", LCD1_OPTION, 0x00000001},
379 {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007},
380 {"GPS_STATUS", GPS_STATUS, 0x00060007},
381 {"GPS_OPTION", GPS_OPTION, 0x00000001},
382 {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007},
383 {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007},
384 {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001},
385 };
386
387 #define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs)
388
389 #define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
390 #define EXYNOS4210_PMU(obj) \
391 OBJECT_CHECK(Exynos4210PmuState, (obj), TYPE_EXYNOS4210_PMU)
392
393 typedef struct Exynos4210PmuState {
394 SysBusDevice parent_obj;
395
396 MemoryRegion iomem;
397 uint32_t reg[PMU_NUM_OF_REGISTERS];
398 } Exynos4210PmuState;
399
400 static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
401 unsigned size)
402 {
403 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
404 unsigned i;
405 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
406
407 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
408 if (reg_p->offset == offset) {
409 PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
410 (uint32_t)offset, s->reg[i]);
411 return s->reg[i];
412 }
413 reg_p++;
414 }
415 PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
416 return 0;
417 }
418
419 static void exynos4210_pmu_write(void *opaque, hwaddr offset,
420 uint64_t val, unsigned size)
421 {
422 Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
423 unsigned i;
424 const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
425
426 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
427 if (reg_p->offset == offset) {
428 PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
429 (uint32_t)offset, (uint32_t)val);
430 s->reg[i] = val;
431 return;
432 }
433 reg_p++;
434 }
435 PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
436 }
437
438 static const MemoryRegionOps exynos4210_pmu_ops = {
439 .read = exynos4210_pmu_read,
440 .write = exynos4210_pmu_write,
441 .endianness = DEVICE_NATIVE_ENDIAN,
442 .valid = {
443 .min_access_size = 4,
444 .max_access_size = 4,
445 .unaligned = false
446 }
447 };
448
449 static void exynos4210_pmu_reset(DeviceState *dev)
450 {
451 Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
452 unsigned i;
453
454 /* Set default values for registers */
455 for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
456 s->reg[i] = exynos4210_pmu_regs[i].reset_value;
457 }
458 }
459
460 static void exynos4210_pmu_init(Object *obj)
461 {
462 Exynos4210PmuState *s = EXYNOS4210_PMU(obj);
463 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
464
465 /* memory mapping */
466 memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s,
467 "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE);
468 sysbus_init_mmio(dev, &s->iomem);
469 }
470
471 static const VMStateDescription exynos4210_pmu_vmstate = {
472 .name = "exynos4210.pmu",
473 .version_id = 1,
474 .minimum_version_id = 1,
475 .fields = (VMStateField[]) {
476 VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS),
477 VMSTATE_END_OF_LIST()
478 }
479 };
480
481 static void exynos4210_pmu_class_init(ObjectClass *klass, void *data)
482 {
483 DeviceClass *dc = DEVICE_CLASS(klass);
484
485 dc->reset = exynos4210_pmu_reset;
486 dc->vmsd = &exynos4210_pmu_vmstate;
487 }
488
489 static const TypeInfo exynos4210_pmu_info = {
490 .name = TYPE_EXYNOS4210_PMU,
491 .parent = TYPE_SYS_BUS_DEVICE,
492 .instance_size = sizeof(Exynos4210PmuState),
493 .instance_init = exynos4210_pmu_init,
494 .class_init = exynos4210_pmu_class_init,
495 };
496
497 static void exynos4210_pmu_register(void)
498 {
499 type_register_static(&exynos4210_pmu_info);
500 }
501
502 type_init(exynos4210_pmu_register)